JP2699283B2 - Bonding method for integrated circuit chips - Google Patents
Bonding method for integrated circuit chipsInfo
- Publication number
- JP2699283B2 JP2699283B2 JP1069219A JP6921989A JP2699283B2 JP 2699283 B2 JP2699283 B2 JP 2699283B2 JP 1069219 A JP1069219 A JP 1069219A JP 6921989 A JP6921989 A JP 6921989A JP 2699283 B2 JP2699283 B2 JP 2699283B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- chip
- substrate
- circuit chip
- laser beam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
- H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は集積回路チップのボンディング方法に関す
る。The present invention relates to a method for bonding integrated circuit chips.
［従来の技術］ 従来、ICチップ等の集積回路チップを基板に形成され
た接続端子にボンディングする方法として、リフロー処
理方式のものがある。この種のボンディング方法は、IC
チップの一面に複数の半田バンプを突出させて形成し、
このICチップを300〜400℃程度の雰囲気中で加熱して各
半田バンプを溶融し、この溶融した半田バンプを基板に
形成された各接続端子にボンディングする方法である。
しかし、このようなボンディング方法では、300〜400℃
程度の雰囲気中でICチップを加熱して半田バンプを溶融
するため、基板側には半田の流延を防止するためのメッ
キレジストを接続端子の周囲に被覆する必要がある。そ
のため、ボンディング工程が複雑となり、作業性が悪い
という問題がある。また、このような方法は半田を溶融
するのに時間がかかるため、生産性が悪く、しかも温度
管理が難しく、歩留りが悪いという問題もある。[Related Art] Conventionally, there is a reflow processing method as a method of bonding an integrated circuit chip such as an IC chip to a connection terminal formed on a substrate. This type of bonding method uses IC
Form a plurality of solder bumps protruding on one side of the chip,
In this method, the IC chip is heated in an atmosphere of about 300 to 400 ° C. to melt each solder bump, and the melted solder bump is bonded to each connection terminal formed on the substrate.
However, with such a bonding method, 300-400 ° C
In order to heat the IC chip in a moderate atmosphere to melt the solder bumps, it is necessary to coat a plating resist around the connection terminals on the substrate side to prevent the flow of the solder. Therefore, there is a problem that the bonding process is complicated and workability is poor. In addition, such a method has a problem that it takes a long time to melt the solder, so that productivity is low, temperature control is difficult, and yield is low.
そこで、最近では基板の接続端子にレザー光線を照射
してボンディングする方法が検討されている。この種の
ボンディング方法は、基板に透明なガラス基板を用い、
この透明なガラス基板を通してレザー光線を接続端子に
照射し、この接続端子を加熱して半田バンプを溶融する
ことによりボンディングする方法である。そのため、上
述したリフロー処理方式のように接続端子の周囲に半田
の流延を防止するメッキレジストを被覆する必要がない
ので、ボンディング工程が簡単となり、しかも半田を溶
融するのに時間がかからず、温度管理も容易である。Therefore, recently, a method of irradiating the connection terminal of the substrate with a laser beam to perform bonding has been studied. This type of bonding method uses a transparent glass substrate as the substrate,
In this method, a laser beam is applied to the connection terminals through the transparent glass substrate, and the connection terminals are heated to melt the solder bumps to perform bonding. Therefore, unlike the reflow processing method described above, there is no need to cover the periphery of the connection terminal with a plating resist for preventing the flow of solder, which simplifies the bonding process, and furthermore, it does not take much time to melt the solder. Also, temperature control is easy.
［発明が解決しようとする課題］ しかし、上述したようなレザー光線を用いたボンディ
ング方法では、レザー光線を接続端子に照射する必要が
あるため、基板としてガラス基板等の透明な基板を用い
なければならないという制約がある。しかも、ICチップ
の半田バンプが対応する基板の接続端子に１つずつレザ
ー光線を照射してボンディングする方式であるから、作
業能率が悪く、生産性が悪いという問題もある。[Problems to be Solved by the Invention] However, in the bonding method using the laser beam as described above, since it is necessary to irradiate the laser beam to the connection terminal, a transparent substrate such as a glass substrate must be used as the substrate. There is a restriction that it must not. In addition, since the solder bumps of the IC chip are bonded one by one to the corresponding connection terminals of the substrate by irradiating laser beams one by one, there is a problem that work efficiency is low and productivity is low.
この発明の目的は、接続端子が形成される基板に制約
がなく、集積回路チップとほぼ同じ平面サイズでかつ照
射形状が四角形状に絞られたレザー光線を用いてICチッ
プ等の集積回路チッブに形成された複数の半田バンプを
基板の各接続端子に一度にボンディングすることがで
き、生産能率のよい集積回路チップのボンディング方法
を提供することにある。An object of the present invention is to provide an integrated circuit chip such as an IC chip by using a laser beam having substantially the same plane size as an integrated circuit chip and a narrowed irradiation shape without any restriction on a substrate on which connection terminals are formed. It is an object of the present invention to provide a method of bonding an integrated circuit chip which can bond a plurality of formed solder bumps to each connection terminal of a substrate at one time and has high productivity.
［課題を解決するための手段］ この発明は、集積回路チップの一面に複数の外部接続
用パッドを形成して、各外部接続用パッド上に半田バン
プを設け、各半田バンプを基板に形成された接続端子上
に載置し、この状態で前記集積回路チップの裏面全体に
前記集積回路チップとほぼ同じ平面サイズでかつ照射形
状が四角形状に絞られたレザー光線を照射し、前記複数
の半田バンプを一度に前記各接続端子にボンディングす
る方法である。Means for Solving the Problems According to the present invention, a plurality of external connection pads are formed on one surface of an integrated circuit chip, solder bumps are provided on each external connection pad, and each solder bump is formed on a substrate. In this state, the entire back surface of the integrated circuit chip is irradiated with a laser beam whose plane size is substantially the same as that of the integrated circuit chip and whose irradiation shape is narrowed into a square shape, and the plurality of solders are applied. In this method, bumps are bonded to the connection terminals at a time.
［作 用］ この発明によれば、集積回路チップの一面に設けられ
た複数の半田バンプを基板に形成された接続端子上に載
置し、この状態で集積回路チップの裏面全体に集積回路
チップとほぼ同じ平面サイズでかつ照射形状が四角形状
に絞られたレザー光線を照射するので、集積回路チップ
の周囲をレザー光線照射により加熱することなく集積回
路チップ全体を効率的且つ均一に加熱することができ、
これにより集積回路チップの各半田バンプを均一に溶か
すことができる。そのため、接続端子が形成される基板
がガラス基板等の透明な基板を用いなければならないと
いう制約を受けることがなく、集積回路チップの各半田
バンプを基板の各接続端子に一度に均一にボンディング
することができ、ボンディング能率がよく、生産性の向
上を図ることができる。According to the present invention, a plurality of solder bumps provided on one surface of an integrated circuit chip are mounted on connection terminals formed on a substrate, and in this state, the integrated circuit chip is mounted on the entire back surface of the integrated circuit chip. The laser beam is radiated with the same plane size as that of the laser beam and the irradiation shape is narrowed down to a square shape, so that the entire integrated circuit chip is efficiently and uniformly heated without heating the periphery of the integrated circuit chip by laser beam irradiation. Can be
Thereby, each solder bump of the integrated circuit chip can be uniformly melted. Therefore, there is no restriction that the substrate on which the connection terminals are formed must be a transparent substrate such as a glass substrate, and each solder bump of the integrated circuit chip is uniformly bonded to each connection terminal of the substrate at once. The bonding efficiency is good and the productivity can be improved.
［実施例］ 以下、第１図〜第３図を参照して、この発明の実施例
を説明する。Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
第１図はICチップにレザー光線を照射して基板の接続
端子にボンディングする状態を示し、第２図および第３
図はICチップの半田バンプを示す。これらの図におい
て、１はICチップ、２は基板、３はレザー装置である。FIG. 1 shows a state in which a laser beam is irradiated to an IC chip and bonded to a connection terminal of a substrate.
The figure shows the solder bumps on the IC chip. In these figures, 1 is an IC chip, 2 is a substrate, and 3 is a laser device.
ICチップ１は内部に集積回路を有するものであり、第
１図に示すように、その下面に多数の半田バンプ４…が
突出して形成されている。この半田バンプ４は第２図お
よび第３図に示すように形成されている。すなわち、所
定の集積回路が形成されたシリコン基板５の上面には酸
化シリコン（SiO2）の絶縁膜６が形成され、この絶縁膜
６上には集積回路のゲート等の内部電極に接続されるパ
ッド電極７がパターン形成されている。このパッド電極
７はアルミニウム、アルミニウム合金等の金属よりな
り、正方形に形成されている。このパッド電極７および
絶縁膜６上には窒化シリコンの絶縁膜８がパターン形成
され、この絶縁膜８にはパッド電極７と対応する部分に
開口部９が形成されている。この絶縁膜８の上面および
開口部９内のパッド電極７上にはアンダーバンプメタル
層10が蒸着またはスパッタリングにより形成されてい
る。このアンダーバンプメタル層10はチタン（Ti）等の
接着メタルと銅（Cu）等のバリアメタルの２層構造とな
っているが、接着メタルとバリアメタルの合金よりなる
１層構造でもよい。このアンダーバンプメタル層10上に
は銅メッキにより拡散防止を補強するバリア補強層11が
電解メッキにより形成され、このバリア補強層11上には
半田バンプ４が電解メッキにより形成されている。この
半田バンプ４はリフロー処理により半田を溶融し、その
表面張力により球形状に形成されている。The IC chip 1 has an integrated circuit inside, and as shown in FIG. 1, a large number of solder bumps 4 project from the lower surface thereof. The solder bumps 4 are formed as shown in FIGS. That is, an insulating film 6 of silicon oxide (SiO 2 ) is formed on the upper surface of the silicon substrate 5 on which a predetermined integrated circuit is formed, and the insulating film 6 is connected to an internal electrode such as a gate of the integrated circuit. The pad electrode 7 is patterned. The pad electrode 7 is made of a metal such as aluminum or an aluminum alloy, and is formed in a square shape. A silicon nitride insulating film 8 is formed on the pad electrode 7 and the insulating film 6 by patterning, and an opening 9 is formed in the insulating film 8 at a portion corresponding to the pad electrode 7. An under bump metal layer 10 is formed on the upper surface of the insulating film 8 and the pad electrode 7 in the opening 9 by vapor deposition or sputtering. The under-bump metal layer 10 has a two-layer structure of an adhesion metal such as titanium (Ti) and a barrier metal such as copper (Cu), but may have a one-layer structure of an alloy of the adhesion metal and the barrier metal. On the under bump metal layer 10, a barrier reinforcing layer 11 for reinforcing diffusion prevention is formed by copper plating, and the solder bumps 4 are formed on the barrier reinforcing layer 11 by electrolytic plating. The solder bumps 4 are formed in a spherical shape by melting the solder by a reflow process and by the surface tension.
このようなICチップ１がボンディングされる基板２
は、第１図に示すように、その上面に多数の接続端子12
…がICチップ１の各半田バンプ４…と対応して形成され
ている。すなわち、基板２はエポキシ樹脂等よりなる硬
質の樹脂ボードや、あるいはポリイミド樹脂等よりなる
軟質の樹脂フィルム等である。この基板２上に形成され
る接続端子12は、基板２の上面に銅箔をラミネートし、
この銅箔をフォトエッチングによりパターン形成し、そ
の表面にニッケル（Ni）メッキおよび金（Au）メッキを
順に施すことにより形成されている。Substrate 2 to which such IC chip 1 is bonded
As shown in FIG. 1, a large number of connection terminals 12
Are formed corresponding to the solder bumps 4 of the IC chip 1. That is, the substrate 2 is a hard resin board made of an epoxy resin or the like, or a soft resin film made of a polyimide resin or the like. The connection terminals 12 formed on the substrate 2 are formed by laminating a copper foil on the upper surface of the substrate 2,
This copper foil is formed by patterning by photoetching, and then applying nickel (Ni) plating and gold (Au) plating on the surface in that order.
また、ICチップ１にレザー光線を照射するレザー装置
３は、レザー発振器（図示せず）、スコープ13、および
集光レンズ14等により構成されている。レザー発振器は
レザー光線を所定の熱エネルギで発生するものである。
スコープ13はレザー発振器で発生したレザー光線をICチ
ップ１の照射面形状、例えば四角形状に絞るものであ
る。集光レンズ14はスコープ13でICチップ１の照射面形
状に絞られたレザー光線を集光してICチップ１の上面全
体に照射する。この場合、レザー光線の照射面の大きさ
は集光レンズ14の焦点距離を調整することにより任意に
変えることができる。これにより、レザー光線はICチッ
プ１の上面全体にのみ照射される。The laser device 3 for irradiating the IC chip 1 with a laser beam includes a laser oscillator (not shown), a scope 13, a condenser lens 14, and the like. The laser oscillator generates a laser beam with a predetermined heat energy.
The scope 13 narrows the laser beam generated by the laser oscillator to the irradiation surface shape of the IC chip 1, for example, a square shape. The condensing lens 14 condenses the laser beam focused by the scope 13 on the irradiation surface shape of the IC chip 1 and irradiates the entire upper surface of the IC chip 1. In this case, the size of the laser beam irradiation surface can be arbitrarily changed by adjusting the focal length of the condenser lens 14. Thus, the laser beam is irradiated only on the entire upper surface of the IC chip 1.
次に、このようなレザー装置３を用いて、ICチップ１
を基板２にボンディングするボンディグ方法について説
明する。Next, using such a laser device 3, the IC chip 1
A bonding method for bonding the substrate to the substrate 2 will be described.
第１図に示すように、基板２の上面に設けられた接続
端子12…上にICチップ１の各半田バンプ４…を対応させ
て載置する。この状態で、レザー装置３のレザー発振器
でレザー光線を発生すると、このレザー光線はスコープ
13でICチップ１の上面と同じ形状に絞られ、集光レンズ
14で集光されてICチップ１の上面全体に照射されるので
あるが、このようにレザー光線がスコープ13でICチップ
１と同じ形状に絞られて集光レンズ14により集光される
と、レザー光線はICチップ１の側方へはみだして基板２
等の本来熱を加えてはならない部分に照射されることが
なく、必要な部分つまりICチップ１の上面全体のみにム
ラなく照射される。このように集積回路チップとほぼ同
じ平面サイズでかつ照射形状が四角形状に絞られたレザ
ー光線がICチップ１の上面全体に照射されると、ICチッ
プ１は短時間で全体が均一に加熱され、この熱により各
半田バンプ４…が同時に均一に溶けて基板２の各接続端
子12…に一度に接合する。As shown in FIG. 1, the solder bumps 4 of the IC chip 1 are placed on the connection terminals 12 provided on the upper surface of the substrate 2 in a corresponding manner. In this state, when a laser beam is generated by the laser oscillator of the laser device 3, the laser beam is scoped.
At 13 the lens is narrowed down to the same shape as the top surface of the IC chip 1 and a condenser lens
The laser beam is condensed at 14 and irradiates the entire upper surface of the IC chip 1. In this manner, when the laser beam is narrowed down to the same shape as the IC chip 1 by the scope 13 and condensed by the condenser lens 14, The laser beam protrudes to the side of the IC chip 1 and the substrate 2
Irradiation is not evenly applied to a portion to which heat should not be applied, but only to a necessary portion, that is, the entire upper surface of the IC chip 1. In this way, when the laser beam, which is almost the same plane size as the integrated circuit chip and the irradiation shape is narrowed down to a square shape, is irradiated on the entire upper surface of the IC chip 1, the entire IC chip 1 is uniformly heated in a short time. Due to this heat, the solder bumps 4... Are simultaneously melted uniformly and joined to the connection terminals 12.
したがって、このようなICチップ１のボンディング方
法によれば、集積回路チップとほぼ同じ平面サイズでか
つ照射形状が四角形状に絞られたレザー光線を直接ICチ
ップ１の上面全体に照射するので、従来のように基板２
が透明でなければならないという制約を受けることがな
く、ICチップ１全体を短時間で均一に加熱することがで
き、この熱でICチップ１に設けられた各半田バンプ４…
を均一に溶かすことができる。そのため、ICチップ１の
総ての半田バンプ４…を一度に基板２の各接続端子12…
にボンディングすることができ、能率よくボンディング
を行なうことができ、生産性の向上を図ることができ
る。しかも、半田バンプ４と接続端子12との間、および
半田バンプ４とICチップ１のパッド電極７との間に生じ
る化合物の成長を抑制することができる。Therefore, according to such a bonding method of the IC chip 1, a laser beam having substantially the same plane size as that of the integrated circuit chip and the irradiation shape narrowed down to a square shape is directly radiated to the entire upper surface of the IC chip 1. Like substrate 2
Is not limited, and the entire IC chip 1 can be uniformly heated in a short time. This heat allows each of the solder bumps 4 provided on the IC chip 1 to be heated.
Can be uniformly dissolved. Therefore, all the solder bumps 4 of the IC chip 1 are simultaneously connected to each of the connection terminals 12 of the substrate 2.
Bonding can be performed efficiently, and the productivity can be improved. In addition, it is possible to suppress the growth of compounds generated between the solder bumps 4 and the connection terminals 12 and between the solder bumps 4 and the pad electrodes 7 of the IC chip 1.
［発明の効果］ 以上詳細に説明したように、この発明のボンディグ方
法によれば、集積回路チップの一面に設けられた複数の
半田バンプを基板に形成された接続端子上に載置し、こ
の状態で集積回路チップの裏面全体に集積回路チップと
ほぼ同じ平面サイズでかつ照射形状が四角形状に絞られ
たレザー光線を照射するので、集積回路チップの周囲を
レザー光線照射により加熱することなく短時間で集積回
路チップ全体を効率的且つ均一に加熱することができ、
これにより集積回路チップの各半田バンプを均一に溶か
すことができる。そのため、接続端子が形成される基板
がガラス基板等の透明な基板を用いなければならないと
いう制約を受けることがなく、集積回路チップの各半田
バンプを基板の各接続端子に一度に均一にボンディング
することができ、能率よくボンディングができ、生産性
の向上を図ることができる。[Effects of the Invention] As described above in detail, according to the bonding method of the present invention, a plurality of solder bumps provided on one surface of an integrated circuit chip are placed on connection terminals formed on a substrate, and In this state, the entire back surface of the integrated circuit chip is irradiated with a laser beam having substantially the same plane size as that of the integrated circuit chip and the irradiation shape is narrowed to a square shape, so that the periphery of the integrated circuit chip is not heated without being heated by laser beam irradiation. The entire integrated circuit chip can be efficiently and uniformly heated in time,
Thereby, each solder bump of the integrated circuit chip can be uniformly melted. Therefore, there is no restriction that the substrate on which the connection terminals are formed must be a transparent substrate such as a glass substrate, and each solder bump of the integrated circuit chip is uniformly bonded to each connection terminal of the substrate at once. Bonding can be performed efficiently and productivity can be improved.
第１図〜第３図はこの発明の実施例を示し、第１図はIC
チップを基板にボンディグする状態を示す図、第２図は
ICチップの半田バンプ部分の拡大断面図、第３図は第２
図のＡ−Ａ断面図である。 １……ICチップ、２……基板、３……レザー装置、４…
…半田バンプ、７……パッド電極、12……接続端子。1 to 3 show an embodiment of the present invention, and FIG.
FIG. 2 shows a state in which a chip is bonded to a substrate, and FIG.
FIG. 3 is an enlarged cross-sectional view of a solder bump portion of an IC chip.
It is AA sectional drawing of a figure. 1 ... IC chip, 2 ... Substrate, 3 ... Leather device, 4 ...
... solder bumps, 7 ... pad electrodes, 12 ... connection terminals.
Claims (1)
パッドを形成して、各外部接続用パッド上に半田バンプ
を設け、各半田バンプを基板に形成された接続端子上に
載置したうえ、前記集積回路チップの裏面全体に前記集
積回路チップとほぼ同じ平面サイズでかつ照射形状が四
角形状に絞られたレザー光線を照射し、前記複数の半田
バンプを一度に前記各接続端子にボンディングすること
を特徴とする集積回路チップのボンディング方法。A plurality of external connection pads are formed on one surface of an integrated circuit chip, solder bumps are provided on each external connection pad, and each solder bump is mounted on a connection terminal formed on a substrate. Further, the entire back surface of the integrated circuit chip is irradiated with a laser beam having substantially the same plane size as that of the integrated circuit chip and the irradiation shape is narrowed down to a square shape, and bonding the plurality of solder bumps to the connection terminals at once. A bonding method for an integrated circuit chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1069219A JP2699283B2 (en) | 1989-03-23 | 1989-03-23 | Bonding method for integrated circuit chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1069219A JP2699283B2 (en) | 1989-03-23 | 1989-03-23 | Bonding method for integrated circuit chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02249247A JPH02249247A (en) | 1990-10-05 |
| JP2699283B2 true JP2699283B2 (en) | 1998-01-19 |
Family
ID=13396391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1069219A Expired - Fee Related JP2699283B2 (en) | 1989-03-23 | 1989-03-23 | Bonding method for integrated circuit chips |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2699283B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006147880A (en) * | 2004-11-19 | 2006-06-08 | Citizen Miyota Co Ltd | Method and device for bonding semiconductor with solder bump |
| JP5126712B2 (en) * | 2007-10-01 | 2013-01-23 | 澁谷工業株式会社 | Bonding equipment |
| JP2022112184A (en) | 2021-01-21 | 2022-08-02 | 株式会社ディスコ | Electrode welding method and electrode welding apparatus |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6053039A (en) * | 1983-09-02 | 1985-03-26 | Hitachi Ltd | Bonding method of semiconductor |
| JP2522796Y2 (en) * | 1987-07-08 | 1997-01-16 | カシオ計算機株式会社 | Semiconductor element mounting structure |
| JPH0671135B2 (en) * | 1989-01-26 | 1994-09-07 | 富士電機株式会社 | IC chip soldering method |
-
1989
- 1989-03-23 JP JP1069219A patent/JP2699283B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02249247A (en) | 1990-10-05 |
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