JP2695778B2 - Thin film formation method - Google Patents

Thin film formation method

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Publication number
JP2695778B2
JP2695778B2 JP62061237A JP6123787A JP2695778B2 JP 2695778 B2 JP2695778 B2 JP 2695778B2 JP 62061237 A JP62061237 A JP 62061237A JP 6123787 A JP6123787 A JP 6123787A JP 2695778 B2 JP2695778 B2 JP 2695778B2
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JP
Japan
Prior art keywords
substrate
thin film
processed
gas
film
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JP62061237A
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Japanese (ja)
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JPS63228625A (en
Inventor
誠 関根
晴雄 岡野
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Toshiba Corp
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Toshiba Corp
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Priority to JP62061237A priority Critical patent/JP2695778B2/en
Priority to DE3856483T priority patent/DE3856483T2/en
Priority to EP88302415A priority patent/EP0283311B1/en
Priority to KR1019880002874A priority patent/KR910006164B1/en
Publication of JPS63228625A publication Critical patent/JPS63228625A/en
Priority to US07/686,283 priority patent/US5156881A/en
Priority to US08/203,757 priority patent/US5385763A/en
Priority to US08/323,693 priority patent/US5458919A/en
Priority to US08/474,312 priority patent/US5591486A/en
Priority to US08/728,613 priority patent/US5776557A/en
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Publication of JP2695778B2 publication Critical patent/JP2695778B2/en
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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は、超LSIデバイスなどの半導体装置の製造に
用いられる薄膜形成方法に係わる。 (従来の技術) 薄膜形成方法を大別すると、化学的気相成長法(Chen
ical Vapor Deposition:CVD)と物理的気相成長法(P
hysical Vapor Deposition:PVD)に分類される。CVD
法は、基板表面や気相中での化学反応を利用して、基板
上に薄膜を形成する方法であり、主にシリコン酸化膜や
シリコン窒化膜などの絶縁膜の形成に用いられている。
また、PVD法は、スパッタリングなどで気相中へたたき
出した堆積粒子を基板へ衝突させて薄膜を形成するもの
で、主に金属膜の形成に用いられてきた。一方、最近の
超LSIデバイスでは、アスペクト比(深さ/幅)の高い
溝内への薄膜堆積技術が必須となりつつある。しかし、
第7図(a)に示すように従来のプラズマCVD法(例え
ばJ、L、Vossen & W、Kerr、Thin Film Processes:A
cademic Press、1978)などを用いてSi基板(17)内に
形成された深い溝(18)内へ絶縁物(19)を堆積する
と、気相中で生じた堆積種の角部23への堆積が大きく、
堆積種が次第に溝底部へ入りにくくなり空洞21を生じ段
差被覆特性が劣化する。この段差被覆形状を改善する方
法として、PVD法の1つであるバイアスパッタ法と称さ
れる技術が用いられている(例えば、T,Mogami,M,Morim
oto & H,Okabayashi:Extended Abstracts 16 th Conf.
Solid State Devices & Materiale,Kobe,1984,P43)。
この方法はArイオンで基板表面を物理的スパッタリング
しながら例えば、シリコン酸化膜を形成するため第7図
(a)の角部23での堆積は起こらず、平担部22、24での
み堆積を生じる。したがって、溝内への埋込みが可能と
なるが気相中の堆積種が構内へ斜めに入射してくるた
め、アスペクト比>1の溝ではやはり埋込み困難とな
る。さらに、物理的スパッタリングによる堆積膜の除去
と堆積の競争反応を用いているので、正味の堆積速度が
低く生産性が極めて悪い。さらに、最近、堆積種の溝内
への斜め入射の成分を少なくしたECRバイアススパッタ
法(例えば、H、OiKawa、SEMI TECHNOLOGY SYM、198
6、E3−1)が提案されているが、掲記の問題は軽減さ
れるものの、本質的な解決策にはならない。この他、例
えば、TEOSの熱分解法(例えばR,D,Rung,Y,Momose &
Y,Nagakubo,IEDM,Tech,Dig,1982,P237を用いて、シリコ
ンSi酸化膜を形成すると、堆積種の大きな表面移動度に
より第7図(b)のように優れた段差被覆特性を示す。
しかし、この方法により、溝内へ埋込んだ酸化膜を、例
えば希釈したHF溶液で洗浄処理すると第7図(c)のよ
うに中央部25での酸化膜の除去速度が異常に速く結局埋
込み平担化が実現できないのが現状である。この原因
は、溝の壁の両側から成長してきた酸化膜同志の歪が中
央部付近で残存するためと考えられる。このようにコン
フォーマブルに基板に均一な膜厚で薄膜を形成する方法
でも高アスペクト比の溝を良好に埋込むことは極めて困
難と考えられる。 (発明が解決しようとする問題点) 本発明は、上記した半導体等の被処理基板に形成され
た高アスペクト比の溝を薄膜で埋め込むのに際し、前記
溝内部に空洞が生じる。あるいは基板表面の段差被覆特
性が良好でない等の従来の問題点を解決する薄膜形成方
法を提供することを目的とする。 〔発明の構成〕 (問題点を解決するための手段) 本発明は、反応容器内に、表面に凹部の形成された被
処理基体を収納し、前記反応容器内に反応ガスを導入
し、前記反応容器内でプラズマを発生させることにより
前記反応ガスより中間生成物を形成し、前記被処理基体
を前記中間生成物の沸点以下の温度に冷却保持すること
により、前記被処理基体表面に前記中間生成物を主体と
する液層を生じせしめ、前記液層が前記凹部底面コーナ
ー部に集積され、分解固化されることにより前記凹部を
埋め込むように薄膜が形成されることを特徴とする薄膜
形成方法を提供する。 (作用) (1) 本発明によれば、アスペクト比の高い溝の底か
ら順次積み上げ式に薄膜を形成していくため溝の内部に
選択的にかつ理想的な完全埋め込みが可能である。 (2) 又、溝を完全に埋め込んだ後は、そのまま上へ
堆積を続けるため埋め込みと同時に超平坦化が可能とな
る。 (3) 更に上記のプロセスを低温で実現できるため、
将来の超LSIに最適である。 (実施例) 以下、本発明の詳細を図示の実施例によって説明す
る。 第1図は本発明の一実施例に係わる薄膜形成装置を示
す概略構成図である。図中1は接地された真空容器であ
り、反応容器となる。反応容器1内には、ガス導入口2
から所定の第一および第二の反応性ガスが導入される。
反応容器内のガスはガス排気口3から排気される。反応
容器1には、陽極(第二の電極)として作用する真空容
器の上壁4と対向する位置に陰極(第一の電極)5が配
置されている。この第一の電極には被処理基体6が載置
され、その内部に冷却した窒素ガス7を流し、冷却を行
っている。また、昇温のための加熱手段も備えている。
さらに、第一の電極には、マッチング回路8を介して高
周波電源9が接続される。また、前記反応容器の被処理
基体以外の領域、例えば反応容器の壁10にはヒータ11が
巻かれておりこれにより堆積膜の付着を防いでいる。ま
た、図示はしていないが、被処理基体6の出し入れに際
し、前記反応容器1と大気の間に真空または不活性ガス
を満した他の真空容器を設け、この真空容器を介して出
し入れを行う手段が具備されている。このように反応容
器をいわゆるロードロックとすることでプロセスの信頼
性が大幅に向上する。図中16は絶縁物である。さらに他
の実施例を第2図に示す。第1図と同一部分は、同一符
号を付して示した。この実施例においては、先の実施例
と同様にして被処理基体6に薄膜を堆積した後、この基
体6を搬送係(図示せず)を介して他の反応容器12まで
運び、加熱手段(図示せず)を備えたホルダ13上に配置
し熱処理を施せるようにしてある。この熱処理の手段
は、前記基体側からの加熱以外に、例えば基体6の上か
ら赤外線ランプ14などを照射し、瞬時に基体温度を上げ
るようにしても良い。また、この熱処理時にガス導入口
2aから不活性ガスあるいは第1の反応性ガスを導入する
こともできる。さらに、加熱中にプラズマを発生するこ
ともできるように高周波電源9がマッチング回路8を介
し接続されている。図中15はゲートバルブである。な
お、本発明は種々応用が可能であり、例えば、プラズマ
を生成する手段として前記のRF電力を印加した平行平板
電極間にさらに外部から磁界を与え高密度のプラズマを
形成してもよい。また、その他のECR(Electron Scycro
tron Resonance)放電、ホロカソード放電、あるいは、
石英などの絶縁物の真空容器に被処理基体を配置し、外
部から高周波電力を与え放電を起こしてもよい。 次に、第1図に示した装置を用いた本発明による薄膜
堆積方法の実施例について説明する。ここでは、第一の
反応性ガスとしてO2、第二の反応性ガスとしてテトラメ
チルシランsi(cH3)4(TMS)を反応容器1内に導入し
た。その時、被処理基体1のSi(シリコン)基板表面に
シリコン酸化膜が形成される様子を第3図に示す。横軸
は、基板温度縦軸は、堆積速度を示し、基板温度に応じ
て、シリコン基板(17)に形成されたシリコントレンチ
溝への埋め込み形状が異なる様子を断面図で示した。プ
ラズマは第一と第二の電極間に、13.56MHZのRF電力を印
加し高周波放電を起こして生成した。反応容器内にはO2
を40cc/分、TMSを5cc/分だけ導入し、全圧力は5×10-3
Torrとした。また第二の電極側に磁石を配置し高密度プ
ラズマを得られるような条件にした。第3図より基板温
度の変化に対して、堆積速度は最大値を示すことがわか
った。また、シリコントレンチ溝への埋め込み形状を観
察するとトレンチ溝のアスペクト比が1以上では室温よ
り高温側において第3図(c)のように気相中でOラジ
カルとTMSが反応して生じたSiO2が雪がふり積もるよう
に基板へ堆積し、いわゆる従来のプラズマCVDとなるた
め、空洞19を生じることがわかった。一方、基板温度の
低下とともに第3図(b)に示されるように溝の入口の
角部分で優先的な堆積が減少し基板温度−20℃以下にお
いて、トレンチ内へ完全に埋め込めることがわかった。
この現象は以下のような機構で生じると考えられる。ま
ず、OラジカルとTMSの反応物であるヘキサメチルジシ
ロキサン(Si(CH32OやトリメチルシラノールSi
(CH33OHなどの中間生成物が第3図に示した温度で液
化し、基板表面に液層が形成される。この液層には気相
中でさらに反応の進んだSiO2の粒子が取込まれる。さら
に、Oラジカルの浸入やOイオンが打込まれながら酸化
が進行していくと考えられる。一方、上記液層は基板表
面に良くなじむために、基板表面と広い接触面積の取れ
るトレンチ溝の底のコーナ部で最も安定に存在できる。
その結果、堆積の時間変化を観察するとこのトレンチ溝
の底のコーナ部分から上記液層が分解固化され、それに
より形成されたシリコン酸化膜の堆積が始まる。したが
って、この堆積では第4図に示したようにトレンチ溝の
底から積みあげ式に膜が形成されるため、従来は不可能
であった、高アスペクト比溝への埋め込み、および超平
坦化が可能となった。また低温で膜形成が可能であるた
め多層配線プロセスにおける層間絶縁膜の形成にも有効
である。なお、O2を導入する代わりにN2やNH4などを用
いれば、シリコン窒化膜(Si3N4)の形成が可能であ
る。また、第2の反応性ガスとして、元素の周期律表に
おいて第2族から第6族に含まれる少なくとも1つの元
素を含ら原料を用い、基板温度を適宜変化させることに
よって、それらの酸化物や窒化物などを容易に形成でき
ることは言うまでもない。 また、反応容器内のガス圧力は上述の10-3Torr代に限
らず、使用する放電の方法、反応性ガスに合わせ最も効
率の良い圧力領域を選択することは言うまでもない。 なお、第1の反応性ガスにArやHeなどの不活性ガスを
添加すると堆積種がメタステイブルな活性種として長寿
命化し、一層効率よく堆積を行なえる。また、反応性ガ
スは、一種類のガスを用い、熱分解法等の手法により所
望の膜を堆積するようにしてもよい。また、膜形成時
に、例えば、波長193nmのエキシマレーザ光やイオン、
電子などを表面に照射すると、前述の液化層が活性化さ
れ、層内の活性種の表面泳動が大きくなって、埋め込
み、平坦化がさらに完全に行われることが実験的に確め
られた。なお前記シリコン酸化膜の形成において、例え
ばTMSにPOCI3、PCI3、PH3、BCI3、B2H6、ASH4などの不
純物を添加すると、これらの不純物を含んだ酸化膜が形
成され、これをトレンチ内に埋め込み、その後、例えば
ヒータやランプによる瞬間的な加熱によってシリコン基
板内に不純物を拡散することができる。従来は、例え
ば、図5のように熱CVD法などにより側壁にそって不純
物を含んだ酸化膜を形成していたが、実際には、シリコ
ントレンチ側壁部に形成した酸化膜に含まれる不純物濃
度は平坦部の物よりも低く、側壁では所望の比抵抗を得
ることができなかった。本発明の酸化膜は第4図に示し
た堆積の時間経過から明らかなように、膜中に取り込ま
れた不純物の量は極めて均一であり、したがって第6図
に示すように堆積した後、熱処理を加えることで上記問
題が一挙に解決された。なお、第6図のような拡散層
は、将来の16Mや64MDRAMのような大容量メモリデバイス
のメモリ容量を十分大きくとるために必須である。上記
加熱処理は膜形成後、例えば第1図あるいは第2図の処
理室でIn−Situで行えば、所定の不純物以外の不純物、
例えば炭素やニッケルといった重金属汚染を完全に避け
ることができ、高品質の膜が堆積される。なお、反応性
ガス中に、例えば、H2やハロゲン元素を含むガスを混在
させることにより、TMS中のメチル基が還元され、より
安定なCH4やCH3CIなどが形成され除去されるため、膜中
の炭素不純物濃度が低下し、より高品質化が図られる。
また、たとえば、H2やN2などとAI(CH3、Ti(C
2H5などの有機金属化合物、W(CO)、Cr(CO)
などのカルボニール金属やハロゲン化金属などを用い
ると、金属をコンタクトホールなどの高アスペクト比ス
ペースへ埋め込めることが確認された。なお、以上のよ
うな薄膜形成の他に、例えば、GeH4、SiH4、SiCI4、GeC
I4などの少なくともSiを含むガスを用いれば、SiやGeの
堆積が可能である。また、AS(CH3、ASH3、Ga(C
H3、GaH3などを用いれば、GaAsなどのIII−V族化
合物、さらにIn、Pを含む反応性ガスを用いればInPな
どのII−VI族化合物などを堆積することが可能である。 さらに、少なくとも炭素および水素を含む反応性ガス
を用いることにより種々の高分子有機膜の堆積が可能と
なる。例えばメタクリルサンメチル(MMA)を導入し、
基板温度を−30度以下まで下げ堆積を行うことによっ
て、電子線レジストに用いられるPMMAを形成できる。 〔発明の効果〕 以上詳述したように本発明によれば高アスペクト比の
微細溝を空洞の発生なく低温で完全に埋め込むことが可
能であり、更にまた、堆積膜表面の平坦化および、多層
配線の層間絶縁膜形成に極めて有効である。更に、被処
理基体に対して均一なプラズマを用いることができるの
で、本発明は、特に大口径ウエハに対して高い均一な膜
の形成が可能であり、同時に高い堆積速度が得られる。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method of forming a thin film used for manufacturing a semiconductor device such as an VLSI device. (Prior art) The thin film forming method is roughly classified into chemical vapor deposition (Chen).
ical Vapor Deposition (CVD) and physical vapor deposition (P
hysical Vapor Deposition (PVD). CVD
The method is a method of forming a thin film on a substrate by using a chemical reaction in a substrate surface or in a gas phase, and is mainly used for forming an insulating film such as a silicon oxide film or a silicon nitride film.
In addition, the PVD method forms a thin film by colliding deposited particles struck into a gas phase by sputtering or the like to form a thin film, and has been mainly used for forming a metal film. On the other hand, in recent VLSI devices, a technique of depositing a thin film in a trench having a high aspect ratio (depth / width) is becoming essential. But,
As shown in FIG. 7A, a conventional plasma CVD method (for example, J, L, Vossen & W, Kerr, Thin Film Processes: A)
When insulator (19) is deposited in deep groove (18) formed in Si substrate (17) using cademic Press, 1978, etc., deposition species deposited in the gas phase are deposited on corner 23. Is large,
The deposited species gradually become difficult to enter the bottom of the groove, so that a cavity 21 is formed and the step coverage characteristics deteriorate. As a method for improving the step covering shape, a technique called a via sputtering method, which is one of the PVD methods, is used (for example, T, Mogami, M, Morim).
oto & H, Okabayashi: Extended Abstracts 16 th Conf.
Solid State Devices & Materiale, Kobe, 1984, P43).
In this method, for example, a silicon oxide film is formed while the substrate surface is physically sputtered with Ar ions, so that the deposition does not occur at the corner 23 in FIG. Occurs. Therefore, it is possible to embed in the groove, but since the deposited species in the gas phase obliquely enter the premises, it is still difficult to embed the groove in the aspect ratio> 1. Further, since a competitive reaction between removal and deposition of the deposited film by physical sputtering is used, the net deposition rate is low and productivity is extremely poor. Furthermore, recently, an ECR bias sputtering method (for example, H, OiKawa, SEMI TECHNOLOGY SYM, 198
6, E3-1) has been proposed, but the problem described above is reduced, but it is not an essential solution. In addition, for example, the pyrolysis method of TEOS (for example, R, D, Rung, Y, Momose &
When a silicon Si oxide film is formed using Y, Nagakubo, IEDM, Tech, Dig, 1982, P237, excellent step coverage characteristics as shown in FIG. 7B are exhibited due to the large surface mobility of the deposited species.
However, when the oxide film embedded in the groove is cleaned by, for example, a diluted HF solution by this method, the removal speed of the oxide film in the central portion 25 is abnormally high as shown in FIG. At present, equalization cannot be realized. It is considered that this is because the strain of the oxide films grown from both sides of the trench wall remains near the center. It is considered that it is extremely difficult to satisfactorily fill a groove having a high aspect ratio even by a method of forming a thin film with a uniform film thickness on a substrate in a conformable manner. (Problems to be Solved by the Invention) In the present invention, when a groove having a high aspect ratio formed in a substrate to be processed such as a semiconductor described above is buried with a thin film, a cavity is formed inside the groove. Another object of the present invention is to provide a method for forming a thin film that solves the conventional problems such as poor step coverage characteristics on a substrate surface. [Structure of the Invention] (Means for Solving the Problems) The present invention provides a method for storing a substrate to be processed having a concave portion formed on a surface thereof in a reaction vessel, and introducing a reaction gas into the reaction vessel. An intermediate product is formed from the reaction gas by generating plasma in the reaction vessel, and the substrate to be processed is cooled and maintained at a temperature equal to or lower than the boiling point of the intermediate product, thereby forming the intermediate on the surface of the substrate to be processed. A method of forming a thin film, wherein a thin film is formed so as to fill the concave portion by forming a liquid layer mainly composed of a product, and the liquid layer is accumulated at the bottom corner of the concave portion and solidified by decomposition. I will provide a. (Operation) (1) According to the present invention, thin films are sequentially formed in a stacked manner from the bottom of a groove having a high aspect ratio, so that it is possible to selectively and ideally completely fill the inside of the groove. (2) After the trench is completely buried, since the deposition is continued as it is, ultra-planarization can be performed simultaneously with the burying. (3) Further, since the above process can be realized at a low temperature,
Ideal for future LSI. (Examples) Hereinafter, details of the present invention will be described with reference to the illustrated examples. FIG. 1 is a schematic diagram showing a thin film forming apparatus according to one embodiment of the present invention. In the figure, reference numeral 1 denotes a grounded vacuum vessel, which is a reaction vessel. A gas inlet 2 is provided in the reaction vessel 1.
A predetermined first and second reactive gas is introduced from the reactor.
The gas in the reaction vessel is exhausted from the gas exhaust port 3. In the reaction vessel 1, a cathode (first electrode) 5 is disposed at a position facing the upper wall 4 of the vacuum vessel acting as an anode (second electrode). A substrate 6 to be processed is placed on the first electrode, and a cooled nitrogen gas 7 flows through the substrate to cool the substrate. Further, a heating means for raising the temperature is provided.
Further, a high frequency power supply 9 is connected to the first electrode via a matching circuit 8. Further, a heater 11 is wound around a region other than the substrate to be processed of the reaction vessel, for example, a wall 10 of the reaction vessel, thereby preventing deposition of a deposited film. Although not shown, another vacuum vessel filled with a vacuum or an inert gas is provided between the reaction vessel 1 and the atmosphere for loading and unloading of the substrate 6 to be processed, and loading and unloading is performed via this vacuum vessel. Means are provided. By using a so-called load lock for the reaction vessel, the reliability of the process is greatly improved. In the figure, reference numeral 16 denotes an insulator. FIG. 2 shows still another embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, a thin film is deposited on the substrate 6 to be processed in the same manner as in the previous embodiment, and then the substrate 6 is transported to another reaction vessel 12 via a transporter (not shown) and heated. (Not shown) on a holder 13 provided with a heat treatment. The heat treatment may be performed by irradiating an infrared lamp 14 or the like from above the base 6, for example, in addition to the heating from the base side so as to instantaneously increase the base temperature. Also, the gas inlet during this heat treatment
An inert gas or a first reactive gas can be introduced from 2a. Further, a high frequency power supply 9 is connected via a matching circuit 8 so that plasma can be generated during heating. In the figure, reference numeral 15 denotes a gate valve. The present invention can be applied in various ways. For example, as means for generating plasma, a high-density plasma may be formed by further applying an external magnetic field between the parallel plate electrodes to which the RF power is applied. Other ECR (Electron Scycro)
tron Resonance) discharge, hollow cathode discharge, or
The substrate to be processed may be arranged in a vacuum vessel made of an insulating material such as quartz, and external high-frequency power may be applied to cause discharge. Next, an embodiment of a thin film deposition method according to the present invention using the apparatus shown in FIG. 1 will be described. Here, O 2 was introduced into the reaction vessel 1 as the first reactive gas, and tetramethylsilane si (cH 3 ) 4 (TMS) was introduced as the second reactive gas. At this time, a state in which a silicon oxide film is formed on the surface of the Si (silicon) substrate of the substrate 1 to be processed is shown in FIG. The abscissa indicates the substrate temperature, and the ordinate indicates the deposition rate. The cross-sectional view shows the manner in which the shape of the silicon trench (17) formed in the silicon substrate (17) is different depending on the substrate temperature. Plasma was generated by applying RF power of 13.56 MHZ between the first and second electrodes and causing a high-frequency discharge. O 2 in the reaction vessel
40 cc / min and TMS at 5 cc / min, total pressure 5 × 10 -3
Torr. In addition, a magnet was arranged on the second electrode side so that high-density plasma was obtained. From FIG. 3, it was found that the deposition rate showed the maximum value with respect to the change in the substrate temperature. Observation of the buried shape in the silicon trench groove shows that, when the aspect ratio of the trench groove is 1 or more, as shown in FIG. 2 was deposited on the substrate so that snow was piled up, and so-called conventional plasma CVD was performed. On the other hand, as shown in FIG. 3 (b), as the substrate temperature decreases, preferential deposition decreases at the corner of the groove entrance, and it can be seen that the trench can be completely buried at the substrate temperature of −20 ° C. or less. Was.
This phenomenon is considered to occur by the following mechanism. First, hexamethyldisiloxane (Si (CH 3 ) 2 ) 2 O, which is a reaction product of O radical and TMS, and trimethylsilanol Si
An intermediate product such as (CH 3 ) 3 OH liquefies at the temperature shown in FIG. 3, and a liquid layer is formed on the substrate surface. SiO 2 particles that have further reacted in the gas phase are taken into this liquid layer. Further, it is considered that the oxidation proceeds while O radicals enter and O ions are implanted. On the other hand, the liquid layer can be most stably present at the corner of the bottom of the trench where a large contact area can be obtained with the substrate surface, since the liquid layer is well adapted to the substrate surface.
As a result, when observing the time change of the deposition, the liquid layer is decomposed and solidified from the corner at the bottom of the trench groove, and the deposition of the silicon oxide film formed thereby starts. Accordingly, in this deposition, as shown in FIG. 4, a film is formed in a stacked manner from the bottom of the trench groove, so that the filling into the high aspect ratio groove and the ultra-flattening, which were conventionally impossible, can be performed. It has become possible. Further, since the film can be formed at a low temperature, it is effective for forming an interlayer insulating film in a multilayer wiring process. If N 2 or NH 4 is used instead of introducing O 2 , a silicon nitride film (Si 3 N 4 ) can be formed. In addition, as a second reactive gas, a raw material containing at least one element included in Groups 2 to 6 in the periodic table of the elements is used, and by appropriately changing the substrate temperature, the oxides thereof can be used. It is needless to say that nitrides and nitrides can be easily formed. Further, the gas pressure in the reaction vessel is not limited to the above-mentioned 10 -3 Torr, and it goes without saying that the most efficient pressure region is selected according to the discharge method to be used and the reactive gas. Note that when an inert gas such as Ar or He is added to the first reactive gas, the deposited species becomes a metastable active species and has a long life, so that deposition can be performed more efficiently. Alternatively, a single kind of reactive gas may be used to deposit a desired film by a technique such as a thermal decomposition method. During film formation, for example, excimer laser light of 193 nm wavelength or ions,
It has been experimentally confirmed that when the surface is irradiated with electrons or the like, the above-mentioned liquefied layer is activated, the surface migration of the active species in the layer is increased, and the embedding and flattening are performed more completely. In addition, in the formation of the silicon oxide film, for example, when impurities such as POCI 3 , PCI 3 , PH 3 , BCI 3 , B 2 H 6 , and ASH 4 are added to TMS, an oxide film containing these impurities is formed, This is buried in the trench, and thereafter, impurities can be diffused into the silicon substrate by, for example, instantaneous heating using a heater or a lamp. Conventionally, for example, as shown in FIG. 5, an oxide film containing impurities was formed along the side wall by a thermal CVD method or the like. However, in practice, the impurity concentration in the oxide film formed on the side wall of the silicon trench was changed. Was lower than that of the flat portion, and the desired specific resistance could not be obtained on the side wall. As is apparent from the time course of the deposition shown in FIG. 4, the amount of impurities incorporated in the oxide film of the present invention is extremely uniform. Therefore, after the deposition as shown in FIG. The above problem was solved all at once. The diffusion layer as shown in FIG. 6 is indispensable for obtaining a sufficiently large memory capacity of a large-capacity memory device such as 16M or 64MDRAM in the future. If the above-mentioned heat treatment is performed in-situ after the film is formed, for example, in the treatment chamber of FIG. 1 or FIG.
Heavy metal contamination such as carbon or nickel can be completely avoided and a high quality film deposited. Incidentally, in the reactive gas, for example, by mixing the gas containing H 2 and a halogen element, is reduced a methyl group in the TMS, more stable CH 4 and CH 3 for such CI is formed is removed In addition, the concentration of carbon impurities in the film is reduced, and higher quality is achieved.
Further, for example, H 2 , N 2, etc. and AI (CH 3 ) 3 , Ti (C
Organometallic compounds such as 2 H 5) 2, W ( CO) 6, Cr (CO)
It has been confirmed that when a carbonyl metal or a metal halide such as No. 6 is used, the metal can be embedded in a high aspect ratio space such as a contact hole. In addition to the above-mentioned thin film formation, for example, GeH 4 , SiH 4 , SiCI 4 , GeC
By using a gas containing at least Si, such as I 4, it is possible to deposition of Si and Ge. AS (CH 3 ) 3 , ASH 3 , Ga (C
If H 3 ) 3 or GaH 3 is used, it is possible to deposit a group III-V compound such as GaAs, and if a reactive gas containing In and P is used, a group II-VI compound such as InP can be deposited. . Further, by using a reactive gas containing at least carbon and hydrogen, it becomes possible to deposit various polymer organic films. For example, introducing methacrylsan methyl (MMA)
By lowering the substrate temperature to −30 ° C. or less and performing deposition, PMMA used for an electron beam resist can be formed. [Effects of the Invention] As described in detail above, according to the present invention, it is possible to completely bury high-aspect-ratio fine grooves at a low temperature without generating cavities. This is extremely effective for forming an interlayer insulating film of wiring. Further, since a uniform plasma can be used for the substrate to be processed, the present invention can form a highly uniform film particularly on a large-diameter wafer, and at the same time, can obtain a high deposition rate.

【図面の簡単な説明】 第1図〜第4図及び第6図は本発明の実施例を説明する
ための図、第5図及び第7図は従来例を説明するための
図である。 17……基板(Siなど)、 18……堆積膜、19……空洞、 20……拡散層形成用不純物を含んだ堆積膜、 21……拡散層。
BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 4 and 6 are views for explaining an embodiment of the present invention, and FIGS. 5 and 7 are views for explaining a conventional example. 17: substrate (such as Si), 18: deposited film, 19: cavity, 20: deposited film containing impurity for forming diffusion layer, 21: diffusion layer.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭61−218134(JP,A) 特開 昭57−172741(JP,A) 特開 昭57−178317(JP,A) 特開 昭61−247035(JP,A) 特開 昭59−168643(JP,A) 特開 昭63−207121(JP,A)   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-61-218134 (JP, A)                 JP-A-57-172741 (JP, A)                 JP-A-57-178317 (JP, A)                 JP-A-61-247035 (JP, A)                 JP-A-59-168643 (JP, A)                 JP-A-63-207121 (JP, A)

Claims (1)

(57)【特許請求の範囲】 1.反応容器内に、表面に凹部の形成された被処理基体
を収納し、前記反応容器内に反応ガスを導入し、前記反
応容器内でプラズマを発生させることにより前記反応ガ
スより中間生成物を形成し、前記被処理基体を前記中間
生成物の沸点以下の温度に冷却保持することにより、前
記被処理基体表面に前記中間生成物を主体とする液層を
生じせしめ、前記液層を、前記凹部に流れ込ませて前記
凹部底面より分解固化させることにより、前記凹部を埋
め込むように薄膜を堆積させてなることを特徴とする薄
膜形成方法。 2.前記反応ガスが酸素および有機シラン系ガスを含
み、前記沸点以下の温度が−20℃以下であることを特徴
とする特許請求の範囲第1項記載の薄膜形成方法。 3.前記被処理基体がシリコン基板であり、前記薄膜が
シリコン酸化膜であり、前記反応ガス中に前記シリコン
基板中でn型不純物、乃至、p型不純物となる元素を含
むガスが添加されていることを特徴とする特許請求の範
囲第1項記載の薄膜形成方法。
(57) [Claims] An intermediate product is formed from the reaction gas by housing a substrate to be processed having a concave portion formed on the surface thereof, introducing a reaction gas into the reaction container, and generating plasma in the reaction container. Then, the substrate to be processed is cooled and maintained at a temperature equal to or lower than the boiling point of the intermediate product, whereby a liquid layer mainly composed of the intermediate product is formed on the surface of the substrate to be processed, and the liquid layer is formed in the concave portion. Characterized in that the thin film is deposited so as to fill the concave portion by flowing into the substrate and decomposing and solidifying from the bottom surface of the concave portion. 2. 2. The thin film forming method according to claim 1, wherein the reaction gas contains oxygen and an organic silane-based gas, and the temperature below the boiling point is -20 [deg.] C. or less. 3. The substrate to be processed is a silicon substrate, the thin film is a silicon oxide film, and a gas containing an element serving as an n-type impurity or a p-type impurity in the silicon substrate is added to the reaction gas. 2. The method for forming a thin film according to claim 1, wherein:
JP62061237A 1987-03-18 1987-03-18 Thin film formation method Expired - Fee Related JP2695778B2 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP62061237A JP2695778B2 (en) 1987-03-18 1987-03-18 Thin film formation method
DE3856483T DE3856483T2 (en) 1987-03-18 1988-03-18 Process for the production of thin layers
EP88302415A EP0283311B1 (en) 1987-03-18 1988-03-18 Thin film forming method
KR1019880002874A KR910006164B1 (en) 1987-03-18 1988-03-18 Making method and there device of thin film
US07/686,283 US5156881A (en) 1987-03-18 1991-04-16 Method for forming a film on a substrate by activating a reactive gas
US08/203,757 US5385763A (en) 1987-03-18 1994-03-01 Method for forming a film on a substrate by activating a reactive gas
US08/323,693 US5458919A (en) 1987-03-18 1994-10-18 Method for forming a film on a substrate by activating a reactive gas
US08/474,312 US5591486A (en) 1987-03-18 1995-06-07 Method for forming a film on a substrate by activating a reactive gas
US08/728,613 US5776557A (en) 1987-03-18 1996-10-10 Method for forming a film on a substrate by activating a reactive gas

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62061237A JP2695778B2 (en) 1987-03-18 1987-03-18 Thin film formation method

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JPS63228625A JPS63228625A (en) 1988-09-22
JP2695778B2 true JP2695778B2 (en) 1998-01-14

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Publication number Priority date Publication date Assignee Title
JP2643406B2 (en) * 1989-01-18 1997-08-20 日本電気株式会社 Method of forming oxide film and oxidation device

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Publication number Priority date Publication date Assignee Title
JPS55113335A (en) * 1979-02-23 1980-09-01 Fujitsu Ltd Manufacture of semiconductor device
JPS57172741A (en) * 1981-04-17 1982-10-23 Nippon Telegr & Teleph Corp <Ntt> Method for forming insulating film for semiconductor device
JPS57178317A (en) * 1981-04-27 1982-11-02 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor single crystal
JPS59168643A (en) * 1983-03-15 1984-09-22 Fuji Electric Corp Res & Dev Ltd Compacting treatment method of oxide film
JPS59175730A (en) * 1983-03-26 1984-10-04 Mitsubishi Electric Corp Electron beam polymerized film forming apparatus
JPH0697660B2 (en) * 1985-03-23 1994-11-30 日本電信電話株式会社 Thin film formation method
JPS61234531A (en) * 1985-04-11 1986-10-18 Canon Inc Formation of silicon oxide
JPS61247035A (en) * 1985-04-24 1986-11-04 Toshiba Corp Surface treating device

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