JP2691619B2 - Compound semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a compound semiconductor device using a two-dimensional carrier gas generated in an InAlAs / InGaAs heterojunction as a channel layer and a method of manufacturing the same. In order to ensure that the gate electrode can maintain Schottky contact even if there is variation, and that the source parasitic resistance R _s does not rise, the InGaAs channel on the semi-insulating compound semiconductor substrate is used. Layers and
InAlAs carrier supply layer and a single-layer or multi-layer first gate of a material that is thin enough to prevent transfer and capable of forming a Schottky barrier with the metal.
A recess forming layer and a second gate / recess forming layer are sequentially formed, and the second gate / recess forming layer is isotropically etched by a dry etching method to form a gate recess, and a dry / A gate formed on the second gate recess forming layer by anisotropically etching only the first gate recess forming layer or an upper layer of the first gate recess forming layer by an etching method. A gate recess narrower than that of the recess is formed, the second gate recess forming layer is not touched, and the first gate recess forming layer or the first gate recess forming layer is formed. The gate electrode is formed only through the upper layer.

[Industrial applications]

The present invention relates to a compound semiconductor device using a two-dimensional carrier gas generated in an InAlAs / InGaAs heterojunction as a channel and a method for manufacturing the same.

In general, InAlAs / InGaAs high electron mobility transistors (HEMTs) are
The GaAs channel layer has a high carrier saturation rate and a high carrier mobility, and the InAlAs carrier supply layer can be heavily doped and has few deep impurity levels. Moreover, the band gap between InAlAs and InGaAs is small. There are many advantages, such as a large continuous value and a large carrier gas concentration, and therefore the HEMT of this system.
Research and development regarding

[Conventional technology]

Normally, in InAlAs / InGaAs HEMT, the InGaAs cap layer formed on the InAlAs carrier supply layer is selectively dry-etched to form a recess, and the recess is formed on the InAlAs carrier supply layer exposed in the recess. The gate electrode is formed.

FIG. 8 shows a cutaway side view of an essential part for explaining an example of InAlAs / InGaAs HEMT. Note that, here, the case where the carrier is an electron will be described.

In the figure, 1 is a semi-insulating InP substrate, 2 is an undoped InGaAs channel layer, 3 is an n-type InAlAs electron supply layer, 4
Is an n-type InGaAs cap layer, 4A is a gate recess, 5 is a source electrode, 6 is a drain electrode, 7 is a gate electrode, and 8 is a two-dimensional electron gas layer.

In recent years, when forming the gate recess 4A in the cap layer 4 of the HEMT, an optical dry etching method has been applied. In this technique, ultraviolet rays are irradiated while a required gas is allowed to flow in the reaction chamber, the gas is decomposed, the generated substance is reacted with the constituent material of the cap layer 4, and etching is performed. InAlAs / InGaAs It is possible to perform selective etching in the system, and further, although it is dry etching, isotropic etching can be performed similarly to wet etching.

[Problems to be solved by the invention]

As described above, the optical dry etching method is applied,
When forming the recess 4A in the cap layer 4, the side
If the etching amount is not constant, it will have a great influence on the characteristic variation of HEMT in the enhancement mode.

FIG. 9 is a cutaway side view of the main part of the HEMT for explaining the case where the side etching amount when forming the recess 4A is too small, and the same symbols as those used in FIG. 8 are the same parts. Or have the same meaning.

In the illustrated example, the side etching amount is too small,
A partial side circumference of the gate electrode 7 is in contact with the cap layer 4.

As is well known, since the barrier height of InGaAs is as small as 0.2 [ev], the gate electrode 7 becomes ohmic contact instead of Schottky contact in the state shown in the figure, and the gate action is obtained. Will not do.

FIG. 10 is a cutaway side view of the essential part of the HEMT for explaining the case where the side etching amount when forming the recess 4A is excessive, and is the same as the symbols used in FIGS. 8 and 9. Symbols indicate the same part or have the same meaning.

In the illustrated example, since the side etching amount is too large,
A part of the electron supply layer 3 is exposed between the side periphery of the gate electrode 7 and the cap layer 4.

In this case, in the enhancement mode, the depletion layer extends from the exposed portion,
The two-dimensional electron gas layer 8 below it partially disappears, the source parasitic resistance R _s increases, and the characteristics deteriorate.

The present invention ensures that the gate electrode can always maintain Schottky contact even if there is variation in the amount of side etching due to the optical dry etching method, and that the source parasitic resistance R _s does not rise. try to.

[Means for solving the problem]

FIG. 1 is a cutaway side view of a main part of a compound semiconductor device for explaining the principle of the present invention, and the same symbols as those used in FIGS. 8 to 10 indicate the same parts or have the same meanings. Shall have.

In the figure, 9 is a layer for forming a GaAs first gate recess,
Reference numeral 10 denotes an InGaAs second gate recess forming layer, and the conductivity type of these gate recess forming layers 9 and 10 is n type if the carriers are electrons.

In this compound semiconductor device, when the recess is formed in the second gate recess forming layer 10, isotropic etching is performed by applying a selective optical dry etching method, and When forming the recess in the first gate / recess forming layer 9, anisotropic etching is performed by applying a selective reactive ion etching (RIE) method. is there.
As a result, the gate electrode 7 can be in contact with the first gate / recess forming layer 9 but separated from the second gate / recess forming layer 10, and the carrier can be supplied. The surface of the layer 3 is covered with the first gate recess forming layer 9 and is not exposed at all.

From the above, in the compound semiconductor device and the manufacturing method thereof according to the present invention, (1) a semi-insulating compound semiconductor substrate (for example, semi-insulating InP
An InGaAs channel layer (for example, an i-type InGaAs channel layer 2) and an InAlAs carrier supply layer (for example, an n-type InAlAs carrier supply layer 3) sequentially formed on the substrate 1);
It is made of a material that can form a Schottky barrier between itself and a metal (for example, Al) formed on the carrier supply layer, and is thin enough (for example, 4 [nm]) so that no transition occurs, and dry etching (for example, 4 nm) Etching gas is CCl ₂
A first gate recess forming layer (eg, a first gate recess made of GaAs) having a gate recess (eg, gate recess 9A) formed by anisotropic etching by RIE method using F ₂ + He) A forming layer 9) and the first gate
A gate that is formed on the recess forming layer and is isotropically etched by a dry etching method (for example, a photo dry etching method using CH ₃ Br based gas as an etching gas) and has a wider width than the gate recess. A second gate recess forming layer having a recess (for example, a second gate recess forming layer 10 made of InGaAs);
Through the gate recess formed in the first gate recess forming layer without touching the recess forming layer,
Or a gate electrode (for example, a gate electrode 7) which is in Schottky contact with the InAlAs carrier supply layer, or (2) in the configuration of (1) above, the first gate recess forming layer is a GaAs layer. Whether the gate electrode is composed of two layers including an AlGaAs layer, and the gate electrode is in Schottky contact with the AlGaAs layer through the gate recess formed in the GaAs layer, or (3) on the semi-insulating compound semiconductor substrate Formed in order
InGaAs channel layer and InAlAs carrier supply layer, and the InAlAs
A material formed on the As carrier supply layer and capable of forming a Schottky barrier with the metal;
A first gate recess forming layer that is thinly formed on the InAlAs carrier supply layer to the extent that no transition occurs, and a first gate recess forming layer formed on the first gate recess forming layer and by a dry etching method, etc. A second gate recess forming layer having a wide gate recess formed by isotropic etching so as not to touch the gate electrode; and the first gate recess forming layer without touching the second gate recess forming layer. A gate electrode for making a Schottky contact with the layer for forming the gate recess, or (4) InGaAs channel layer and InAlAs carrier supply layer on the semi-insulating compound semiconductor substrate, and a thin metal so as not to cause dislocation A step of sequentially growing a first gate recess forming layer and a second gate recess forming layer made of a material capable of forming a Schottky barrier between And a step of isotropically etching the second gate recess forming layer by dry etching to form a gate recess, and then a reactive ion etching method for forming the first gate recess. Forming a gate recess narrower than the gate recess formed in the second gate recess forming layer by anisotropically etching the use layer, and then forming the second gate recess Or a step of forming a gate electrode through the first gate / recess forming layer without touching the working layer, or (5) in the configuration of (4) above, A GaAs layer is grown in order to form a first gate recess forming layer, the gate recess in the first gate recess forming layer is formed only in the GaAs layer, and the gate electrode is formed in the AlGaAs layer. Schottky contact (6) InGaAs channel layer and InAlAs carrier supply layer on the semi-insulating compound semiconductor substrate, and a Schottky barrier between the InAl channel layer and the InAlAs carrier supply layer, which is thin enough to prevent dislocation A step of sequentially growing a first gate recess forming layer and a second gate recess forming layer made of a material that can be generated, and then the second gate recess forming by a dry etching method. Forming a gate recess by isotropically etching the first gate layer without contacting the second gate recess forming layer.
A step of forming a gate electrode in Schottky contact with the recess forming layer.

[Action]

By adopting the above-mentioned means, the gate electrode contacts the first gate / recess forming layer but does not touch the second gate / recess forming layer at all, and thus maintains a good Schottky barrier. Further, since the carrier supply layer is completely covered with the first gate recess forming layer and is not exposed in the vicinity of the gate electrode, the depletion layer spreads and the parasitic source resistance R _s is increased. A compound semiconductor device having uniform characteristics can be realized without any fear of increase in

〔Example〕

FIG. 2 shows a cutaway side view of an essential part of an embodiment of the present invention. The same symbols as those used in FIGS. 1 and 8 to 10 indicate the same parts or have the same meaning. And

In the figure, 11 represents a buffer layer formed on the semi-insulating InP substrate 1.

The following is an example of the main data in each part of this embodiment.

(1) About buffer layer 11 Material: i-type In _0.52 Al _0.48 As Thickness: 350 [nm] (2) About channel layer 2 Material: i-type In _0.53 Ga _0.47 As Thickness: 80 [nm] (2) Electron Supply layer 3 Material: n-type In _0.52 Al _0.48 As Thickness: 35 [nm] Impurity: Si Impurity concentration: 1 × 10 ¹⁸ [cm ^-3 ] (4) First gate / recess formation layer 9 Material : n-type GaAs thickness: 4 [nm] Impurity: Si Impurity concentration: 1 × 10 ¹⁸ [cm ^-3 ] (5) Second gate / recess formation layer 10 Material: n-type In _0.53 Ga _0.47 As thickness Length: 80 [nm] Impurity: Si Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] FIGS. 3 to 6 are steps for explaining the embodiment for manufacturing the embodiment shown in FIG. FIG. 3 is a side view of a cutaway portion of a compound semiconductor device at a key portion, which will be described below with reference to these figures. Incidentally, FIGS. 1 and 8 to 10
The same symbols as those used in the drawings indicate the same parts or have the same meanings.

See Fig. 3 (3) -1 metalorganic chemical vapor deposition
The semiconductor layers described with reference to FIG. 2 are epitaxially grown on the semi-insulating InP substrate 1 by applying the r deposition (MOCVD) method.

(3) -2 Resist in ordinary photolithography technology
A mask film (not shown) made of photoresist is formed by applying a process, and then an acceleration energy of 110 [Ke
V], the dose amount is 1 × 10 ¹³ [cm ⁻² ], and
Acceleration energy is 50 [KeV] and dose is 1 × 10 ¹² [cm
^-2 ], the element isolation region 12 is formed by implanting oxygen ions. Incidentally, the elements can be separated from each other by, for example, mesa etching.

(3) -3 By applying the resist process and the vacuum deposition method in photolithography technology, AuGe / Au = 100
The electrode material film of [nm] / 200 [nm] is patterned by lift-off to form the source electrode 5 and the drain electrode 6 of ohmic contact.

(3) -4 Heat treatment is performed at a temperature of 350 [° C.] and a time of 1 [minute].

See FIG. 4. (4) -1 By applying a resist process in the photolithography technique, a photoresist film 13 having an opening corresponding to a portion where a gate electrode is to be formed is formed.

(4) -2 By applying a photo dry etching method using a gas containing CH ₃ Br as a main component as an etching gas,
Using the photoresist film 13 as a mask, the second gate
The recess forming layer 10 is etched to form a recess 10A.

At this time, the first gate / recess formation layer 9 is formed of CH ₃ Br.
Since it is not etched with a system gas, so-called etching
It serves as a stopper, and therefore selective etching is possible. Further, since this etching is isotropic etching, the recess 10A can be made wider than the opening in the photoresist film 13, and the side etching amount is 100 [nm], for example.

See Fig. 5 (5) -1 Halogen gas such as CC as etching gas
Reactive ion etching using l ₂ F ₂ + He (reactive
By applying the ion etching (RIE) method, the first gate recess forming layer 9 is also etched by using the photoresist film 13 as a mask to form a recess 9A.

At this time, since the second gate / recess forming layer 10 and the electron supply layer 3 are not etched with CCl ₂ F ₂ + He, selective etching is possible as well. Further, since this etching is anisotropic etching, the recess 9A has substantially the same pattern as the opening in the photoresist film 13.

See FIG. 6 (6) -1 An Al film, for example, is formed by applying a vacuum deposition method with the photoresist film 13 left as it is.

(6) -2 The Al film is patterned by the lift-off method of removing the photo resist film 13 to form the Schottky contact gate electrode 7.

In the compound semiconductor device manufactured in this manner, the second gate recess forming layer 10 and the first gate recess forming layer 9 made of different materials, that is, InGaAs and GaAs, are used.
On the other hand, by adopting different etching methods, that is, the optical dry etching method and the RIE method, and therefore the isotropic etching and the anisotropic etching, the gate electrode 7 is recessed.
Good Schottky contact can be maintained without contact with sidewalls at 10A, and InAlAs
Since the electron supply layer 3 composed of is not exposed, the parasitic source resistance R _s due to the generation of the depletion layer does not increase.

In the embodiment described with reference to FIGS. 2 and 3 to 6, the gate electrode 7 is in direct contact with the n-type InAlAs electron supply layer 3, but this may be the first gate recess formation if necessary. It may be formed so as to contact the working layer 9.

FIG. 7 is a cutaway side view of a main part of a compound semiconductor device for explaining another embodiment of the present invention, which is the same as the symbols used in FIGS. 2 and 3 to 6. Indicate the same part or have the same meaning.

In the figure, 13 indicates an i-type AlGaAs gate recess layer.

The main data regarding the gate recess layer 13 is exemplified below.

Material: i-type Al _0.3 Ga _0.7 As Thickness: 4 [nm] In this embodiment, similarly to the above, when the first gate / recess forming layer 9 made of GaAs is selectively etched by the RIE method. , The gate recess layer 13 made of AlGaAs is Ga
Since only about 1/200 is etched against As,
Practically acts as an etching stopper.

Further, here, since the gate electrode 7 is in contact with the gate recess layer 13 made of AlGaAs, the forward rising voltage is 0.3 [V] as compared with the case where it is directly contacted with the electron supply layer made of InAlAs. ], The device characteristics are further improved.

〔The invention's effect〕

In the compound semiconductor device and the method for manufacturing the same according to the present invention, a Schottky barrier is formed between the InGaAs channel layer and the InAlAs carrier supply layer and the metal on the semi-insulating compound semiconductor substrate, and thin enough to prevent dislocation. A single-layer or multiple-layer first gate recess forming layer and a second gate recess forming layer made of a material capable of forming the second gate recess forming layer by a dry etching method. Isotropically etched to form a gate recess, and the dry etching method is used to anisotropically etch only the first gate recess forming layer or the upper layer of the first gate recess forming layer. And forming a narrower gate recess as compared with the gate recess formed in the second gate recess forming layer, and touching the second gate recess forming layer. Ku and the first gate
The gate electrode is formed only through the recess forming layer or the upper layer of the first gate / recess forming layer.

By adopting the above configuration, the gate electrode contacts the first gate / recess forming layer, but does not touch the second gate / recess forming layer at all, thus maintaining a good Schottky barrier. Further, since the carrier supply layer is completely covered with the first gate recess forming layer and is not exposed in the vicinity of the gate electrode, the depletion layer spreads and the parasitic source resistance R _s is increased. A compound semiconductor device having uniform characteristics can be realized without any fear of increase in

[Brief description of the drawings]

FIG. 1 is a side view of a compound semiconductor device for explaining the principle of the present invention, FIG. 2 is a side view for the essential part of a first embodiment of the present invention, and FIGS. 3 to 6 are FIG. FIG. 7 is a sectional side view of a main part of a compound semiconductor device at a process step for explaining an example when manufacturing the example shown in FIG. 8 is a sectional side view of an essential part of the compound semiconductor device shown in FIG. 8, FIG. 8 is a sectional side view of an essential part for explaining an example of InAlAs / InGaAs HEMT, and FIG. 9 is an excessive side etching amount when forming the recess 4A. The main part cut side view of the HEMT for explaining the case where is, FIG. 10 is a main part cut side view of the HEMT for explaining the case where the amount of side etching when forming the recess 4A is excessive, respectively. Represent In the figure, 1 is a semi-insulating InP substrate, 2 is an undoped InGaAs channel layer, 3 is an n-type InAlAs electron supply layer, 4
Is an n-type InGaAs cap layer, 4A is a gate recess, 5 is a source electrode, 6 is a drain electrode, 7 is a gate electrode, 8 is a two-dimensional electron gas layer, 9 is a GaAs first gate recess forming layer, and 10 is The respective layers for forming the InGaAs second gate recess are shown.

Claims (6)

(57) [Claims] 1. A Schottky barrier is formed between an InGaAs channel layer and an InAlAs carrier supply layer sequentially formed on a semi-insulating compound semiconductor substrate and a metal formed on the InAlAs carrier supply layer. A first gate recess forming layer having a gate recess which is made of a possible material and is thin enough not to cause dislocation and which is formed by anisotropic etching by a dry etching method; and the first gate recess. A second gate recess forming layer formed on the forming layer and formed by isotropic etching by a dry etching method and having a wider gate recess than the gate recess; and the second gate recess forming layer. A Schottky film is formed on the InAlAs carrier supply layer through the gate recess formed in the first gate recess forming layer without touching the recess forming layer.
A compound semiconductor device, comprising: a gate electrode that contacts. 2. The first gate recess forming layer is a GaAs layer.
The compound according to claim 1, wherein the compound is composed of two layers including an AlGaAs layer, and the gate electrode is in Schottky contact with the AlGaAs layer through a gate recess formed in the GaAs layer. Semiconductor device. 3. A Schottky barrier is formed between an InGaAs channel layer and an InAlAs carrier supply layer sequentially formed on a semi-insulating compound semiconductor substrate and a metal formed on the InAlAs carrier supply layer. A first gate recess forming layer which is made of a possible material and is formed thin enough not to cause dislocation, and a first gate recess forming layer formed on the first gate recess forming layer and by a dry etching method, etc. A second gate recess forming layer having a wide gate recess formed by isotropic etching so as not to touch the gate electrode; and the first gate recess forming layer without touching the second gate recess forming layer. A compound semiconductor device, comprising: a gate electrode which is in Schottky contact with a layer for forming a gate recess. 4. An InGaAs channel layer and an InAlAs carrier supply layer on a semi-insulating compound semiconductor substrate and a material which is thin enough not to cause dislocation and is capable of forming a Schottky barrier with a metal. The step of growing the gate / recess forming layer and the second gate / recess forming layer in order, and then isotropically etching the second gate / recess forming layer by a dry etching method. A step of forming a recess, and then comparing the gate recess formed in the second gate recess forming layer by anisotropically etching the first gate recess forming layer by a dry etching method. To form a narrow gate recess, and then, without touching the second gate recess forming layer and via the first gate recess forming layer. Method of manufacturing a compound semiconductor device characterized by comprising contains a step of forming an electrode. 5. An AlGaAs layer and a GaAs layer are sequentially grown to form a first gate recess forming layer, and the gate recess in the first gate recess forming layer is formed only in the GaAs layer. The method of manufacturing a compound semiconductor device according to claim 4, further comprising the step of forming a gate electrode so as to make Schottky contact with the AlGaAs layer. 6. An InGaAs channel layer and an InAlAs carrier supply layer on a semi-insulating compound semiconductor substrate and a material which is thin enough not to cause dislocation and is capable of forming a Schottky barrier with a metal. The step of growing the gate / recess forming layer and the second gate / recess forming layer in order, and then isotropically etching the second gate / recess forming layer by a dry etching method. And a step of forming a gate electrode which is in Schottky contact with the first gate / recess forming layer without touching the second gate / recess forming layer. A method of manufacturing a compound semiconductor device, comprising: