JP2690585B2 - Semiconductor element cooling structure - Google Patents
Semiconductor element cooling structureInfo
- Publication number
- JP2690585B2 JP2690585B2 JP2031631A JP3163190A JP2690585B2 JP 2690585 B2 JP2690585 B2 JP 2690585B2 JP 2031631 A JP2031631 A JP 2031631A JP 3163190 A JP3163190 A JP 3163190A JP 2690585 B2 JP2690585 B2 JP 2690585B2
- Authority
- JP
- Japan
- Prior art keywords
- cooling
- semiconductor element
- substrate
- bubbles
- refrigerant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体素子の冷却構造に係り、特に基板に実装された
半導体素子を浸漬冷却にて冷却してなる半導体素子の冷
却構造に関し、 浸漬冷却を行うに際し、上流側の半導体素子から発さ
れる気泡が下流側の半導体素子に悪影響を与えないよう
にすることを目的とし、 冷媒の供給流路と帰還流路とが形成された冷却ブロッ
クと、半導体素子を複数実装してなる基板とを有し、該
冷却ブロックと基板との間の冷却室に冷媒を流動させ、
当該半導体素子を浸漬冷却にて冷却してなる半導体素子
の冷却構造において、前記基板を所定角度の傾斜をもっ
て配置し、且つ前記半導体素子対応に気泡を逃がすバイ
パスを前記冷却ブロックに設けるように構成する。The present invention relates to a semiconductor element cooling structure, and more particularly to a semiconductor element cooling structure in which a semiconductor element mounted on a substrate is cooled by immersion cooling. When performing immersion cooling, an upstream side is provided. For the purpose of preventing bubbles generated from the semiconductor element from adversely affecting the semiconductor element on the downstream side, a plurality of semiconductor elements are mounted together with a cooling block in which a coolant supply channel and a return channel are formed. Having a substrate formed of, and flowing a coolant into a cooling chamber between the cooling block and the substrate,
In a semiconductor element cooling structure in which the semiconductor element is cooled by immersion cooling, the substrate is arranged with an inclination of a predetermined angle, and a bypass for releasing bubbles corresponding to the semiconductor element is provided in the cooling block. .
本発明は、半導体素子の冷却構造に係り、特に基板に
実装された半導体素子を浸漬冷却にて冷却してなる半導
体素子の冷却構造に関するものである。The present invention relates to a semiconductor element cooling structure, and more particularly to a semiconductor element cooling structure in which a semiconductor element mounted on a substrate is cooled by immersion cooling.
従来の浸漬冷却は第２図の如く構成となっている。 The conventional immersion cooling has a structure as shown in FIG.
つまり、フロリナート等の化学的に安定な冷媒が供給
される冷媒供給流路および帰還される冷媒帰還流路が形
成された冷却ブロックに、フランジを介して複数の半導
体素子が実装されてなる基板が平行に取り付けられる。In other words, a substrate having a plurality of semiconductor elements mounted via flanges on a cooling block in which a coolant supply channel for supplying a chemically stable coolant such as Fluorinert and a coolant return channel for returning are formed. Mounted in parallel.
冷却ブロックに基板を取り付けるこで冷却室が形成さ
れる。The cooling chamber is formed by mounting the substrate on the cooling block.
この冷却室にフロリナート等の冷媒を供給すること
で、半導体素子はその気化熱によって沸騰冷却される。By supplying a coolant such as Fluorinert to this cooling chamber, the semiconductor element is boiled and cooled by its heat of vaporization.
尚、冷却ブロックには、図示しない配管と接続される
カプラ等の接続部品が、供給側および帰還側に取り付け
られている。It should be noted that the cooling block is provided with connecting parts such as a coupler connected to a pipe (not shown) on the supply side and the return side.
浸漬冷却にて半導体素子を冷却すると、その冷媒の一
部が気化することによって、気泡が発生する。When the semiconductor element is cooled by immersion cooling, a part of the cooling medium is vaporized to generate bubbles.
従来は、半導体素子が搭載された基板が冷却ブロック
に対して平行に位置していたため、上流側の半導体素子
を冷却することで発生する気泡が、その下流側の半導体
素子の放熱を妨げることで、熱抵抗が大きくなってしま
い、冷却効率が悪くなるという欠点があった。Conventionally, since the substrate on which the semiconductor element is mounted is positioned parallel to the cooling block, air bubbles generated by cooling the semiconductor element on the upstream side block heat dissipation of the semiconductor element on the downstream side. However, there is a drawback that the heat resistance becomes large and the cooling efficiency becomes poor.
従って、本発明は、浸漬冷却を行うに際し、上流側の
半導体素子から発される気泡が下流側の半導体素子に悪
影響を与えないようにすることを目的とするものであ
る。Therefore, it is an object of the present invention to prevent bubbles generated from a semiconductor element on the upstream side from adversely affecting the semiconductor element on the downstream side during immersion cooling.
上記目的は、冷媒の供給流路７と帰還流路８とが形成
された冷却ブロック１と、 半導体素子３を複数実装してなる基板２とを有し、 該冷却ブロック１と基板２との間の冷却室４に冷媒を
流動させ、当該半導体素子３を浸漬冷却にて冷却してな
る半導体素子の冷却構造において、 前記基板２を所定角度の傾斜をもって配置し、且つ前
記半導体素子３対応に気泡６を逃がすバイパス11を前記
冷却ブロック１に設けたことを特徴とする半導体素子の
冷却構造、により達成される。The above object has a cooling block 1 in which a coolant supply flow path 7 and a return flow path 8 are formed, and a substrate 2 on which a plurality of semiconductor elements 3 are mounted. In a semiconductor element cooling structure in which a cooling medium 4 is caused to flow between them and the semiconductor element 3 is cooled by immersion cooling, the substrate 2 is arranged with an inclination of a predetermined angle, and the semiconductor element 3 is supported. The cooling structure for a semiconductor device is characterized in that the cooling block 1 is provided with a bypass 11 for allowing the bubbles 6 to escape.
本発明においては、基板を冷却ブロックに対して所定
角度をもって傾斜しているので、半導体素子を冷却する
ことで発生する気泡と冷媒とをその比重差によって分離
される。In the present invention, since the substrate is inclined at a predetermined angle with respect to the cooling block, the bubbles and the refrigerant generated by cooling the semiconductor element are separated by the difference in their specific gravities.
この分離された気泡を、半導体素子対応に冷却ブロッ
クに形成されたバイパスによって帰還流路側に逃がすこ
とができる。The separated bubbles can be released to the return flow passage side by a bypass formed in the cooling block corresponding to the semiconductor element.
以下、本発明の実施例を第１図を用いて詳細に説明す
る。Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG.
第１図は、本発明の実施例を示す図である。 FIG. 1 is a diagram showing an embodiment of the present invention.
図において、１は冷却ブロック,2は基板,3は半導体素
子,4は冷却室,5はサブマニホールド,6は気泡,7は冷媒供
給流路,8は冷媒帰還流路,9はフランジ,10は接続部品,11
はバイパスをそれぞれ示す。In the figure, 1 is a cooling block, 2 is a substrate, 3 is a semiconductor element, 4 is a cooling chamber, 5 is a sub-manifold, 6 is a bubble, 7 is a refrigerant supply channel, 8 is a refrigerant return channel, 9 is a flange, 10 Connection parts, 11
Indicate bypasses, respectively.
第１図に示すように、フロリナート等の化学的に安定
な冷媒が供給される冷媒供給流路７および帰還される冷
媒帰還流路８が形成された冷却ブロック１に、フランジ
９を介して複数の半導体素子３が実装されてなる基板２
を取り付けられる。As shown in FIG. 1, a plurality of cooling block 1 is formed through a flange 9 in a cooling block 1 in which a refrigerant supply flow path 7 for supplying a chemically stable refrigerant such as Fluorinert and a refrigerant return flow path 8 for returning are formed. Substrate 2 on which the semiconductor element 3 is mounted
Can be attached.
尚、10は図示しない配管を接続するための接続部品で
ある。Incidentally, 10 is a connecting part for connecting a pipe (not shown).
本発明においては、この基板２が冷却ブロック１に対
して所定角度をもって傾斜するようにして取り付けられ
る。この角度は冷媒が冷却室４を循環する際の流速に従
って設定される。In the present invention, the substrate 2 is attached so as to be inclined with respect to the cooling block 1 at a predetermined angle. This angle is set according to the flow velocity of the refrigerant circulating in the cooling chamber 4.
冷却ブロック１に基板２を取り付けることで冷却室４
が形成され、この冷却室４に半導体素子３が位置され
る。By attaching the substrate 2 to the cooling block 1, the cooling chamber 4
Is formed, and the semiconductor element 3 is located in the cooling chamber 4.
一方、冷却ブロック１には、半導体素子３側上面から
冷媒帰還流路８に対して、冷却ブロック１外面と平行に
バイパス11およびサブマニホールド５から構成される一
連のルートが形成されている。これは、半導体素子３を
冷却することで発生する気泡６を冷媒帰還流路８へ逃が
すものである。尚、バイパス11の径よりサブマニホール
ド５の径の方を大きく設定しておく。On the other hand, in the cooling block 1, a series of routes including a bypass 11 and a sub-manifold 5 are formed in parallel with the outer surface of the cooling block 1 from the upper surface of the semiconductor element 3 side to the refrigerant return flow path 8. This allows bubbles 6 generated by cooling the semiconductor element 3 to escape to the refrigerant return flow path 8. The diameter of the sub-manifold 5 is set to be larger than the diameter of the bypass 11.
本発明では、上記の如く冷却ブロック１に対して基板
２を傾斜して構成しているので、冷媒を冷却室４に供給
し半導体素子３の冷却を行うことで発生する気泡６を、
冷媒と分離することでできる。即ち、液体である冷媒と
気泡６とでは、その比重差が異なっているため（気泡＜
冷媒）である。In the present invention, since the substrate 2 is inclined with respect to the cooling block 1 as described above, the bubbles 6 generated by cooling the semiconductor element 3 by supplying the cooling medium to the cooling chamber 4,
It can be separated from the refrigerant. That is, the difference in specific gravity between the liquid refrigerant and the bubbles 6 is different (bubble <
Refrigerant).
従って、気泡６は冷却ブロック１に形成されたバイパ
ス11に侵入し、一方、気泡６が取り除かれた冷媒は下流
側の半導体素子３に向かって流動する。Therefore, the bubbles 6 enter the bypass 11 formed in the cooling block 1, while the coolant from which the bubbles 6 have been removed flows toward the semiconductor element 3 on the downstream side.
よって、上流側の半導体素子３を冷却することで発生
する気泡６が、下流側の半導体素子３に悪影響を与える
ことがなくなる。Therefore, the bubbles 6 generated by cooling the semiconductor element 3 on the upstream side do not adversely affect the semiconductor element 3 on the downstream side.
尚、上記サブマニホールド５は冷媒が循環する流速が
速い程、位置的に低くする必要がある。The sub-manifold 5 needs to be lower in position as the flow rate of the circulating refrigerant is higher.
以上の如く本発明においては、上流側の半導体素子の
浸漬冷却を行う際に発生する気泡が、下流側の半導体素
子に悪影響を与えることがなくなり、下流側の熱抵抗が
大きくなるといった状態が発生しない。As described above, in the present invention, the bubbles generated when the semiconductor element on the upstream side is immersed and cooled do not adversely affect the semiconductor element on the downstream side, and the thermal resistance on the downstream side increases. do not do.
従って、半導体素子から冷媒への熱伝達を阻害せず、
故に冷却効率が増大する。Therefore, it does not hinder the heat transfer from the semiconductor element to the refrigerant,
Therefore, the cooling efficiency is increased.
第１図は、本発明の実施例を示す図であり、 第２図は、従来の構造を示す図である。 図において、 １は冷却ブロック， ２は基板， ３は半導体素子， ４は冷却室， ５はサブマニホールド， ６は気泡， ７は冷媒供給流路， ８は冷媒帰還流路， 11はバイパス， をそれぞれ示す。 FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional structure. In the figure, 1 is a cooling block, 2 is a substrate, 3 is a semiconductor element, 4 is a cooling chamber, 5 is a sub-manifold, 6 is a bubble, 7 is a refrigerant supply passage, 8 is a refrigerant return passage, 11 is a bypass, Shown respectively.
Claims (1)
が形成された冷却ブロック（１）と、 半導体素子（３）を複数実装してなる基板（２）とを有
し、 該冷却ブロック（１）と基板（２）との間の冷却室
（４）に冷媒を流動させ、当該半導体素子（３）を浸漬
冷却にて冷却してなる半導体素子の冷却構造において、 前記基板（２）を所定角度の傾斜をもって配置し、且つ
前記半導体素子（３）対応に気泡（６）を逃がすバイパ
ス（11）を前記冷却ブロック（１）に設けたことを特徴
とする半導体素子の冷却構造。1. A cooling block (1) having a coolant supply channel (7) and a return channel (8) formed therein, and a substrate (2) having a plurality of semiconductor elements (3) mounted thereon. Then, in a cooling structure for a semiconductor element, wherein a cooling medium (4) between the cooling block (1) and the substrate (2) is caused to flow a cooling medium to cool the semiconductor element (3) by immersion cooling, A semiconductor device characterized in that the substrate (2) is arranged at an inclination of a predetermined angle, and a bypass (11) for allowing the bubbles (6) to escape is provided in the cooling block (1) corresponding to the semiconductor device (3). Cooling structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2031631A JP2690585B2 (en) | 1990-02-14 | 1990-02-14 | Semiconductor element cooling structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2031631A JP2690585B2 (en) | 1990-02-14 | 1990-02-14 | Semiconductor element cooling structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03236268A JPH03236268A (en) | 1991-10-22 |
| JP2690585B2 true JP2690585B2 (en) | 1997-12-10 |
Family
ID=12336563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2031631A Expired - Fee Related JP2690585B2 (en) | 1990-02-14 | 1990-02-14 | Semiconductor element cooling structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2690585B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2682784B2 (en) * | 1993-02-23 | 1997-11-26 | 大同メタル工業株式会社 | Oldham ring of scroll type compressor |
| US5777384A (en) * | 1996-10-11 | 1998-07-07 | Motorola, Inc. | Tunable semiconductor device |
| AU2003246165A1 (en) * | 2003-06-30 | 2005-01-21 | Advantest Corporation | Cover for cooling heat generating element, heat generating element mounter and test head |
-
1990
- 1990-02-14 JP JP2031631A patent/JP2690585B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03236268A (en) | 1991-10-22 |
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| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080829 Year of fee payment: 11 |
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| LAPS | Cancellation because of no payment of annual fees |