JP2689591B2 - Method for manufacturing multilayer printed wiring board - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer printed wiring board, and in particular, multilayer printing partially having through holes formed by dividing conductor layers for high-density mounting. The present invention relates to a method for manufacturing a wiring board.

[4 Technology] High density integration of multilayer printed wiring boards (hereinafter referred to as “multilayer boards”) is progressing in order to achieve high integration of LSIs and ICs, high performance of electronic devices and improvement of economic efficiency.

Two main measures are taken to increase the density of multilayer boards. The first is to increase the number of conductor layers, that is, to increase the number of layers, and the second is to increase the number of wires between basic lattices. However, in the first measure, the number of via holes for connecting the conductor layers between the layers increases, and the multiplicity of wiring measures in the second measure, and consequently, the wiring accommodating ability is significantly limited. Therefore, in particular, when this via hole is provided as a through hole in the multilayer board, it is dealt with by reducing the diameter of the via hole.
The plate thickness / pore diameter ratio (aspect ratio) increases, which significantly impairs the productivity of the multilayer plate.

Therefore, as a means for eliminating the above-mentioned drawbacks, as shown in FIG. 3 (A), two sets of the catalyst-containing insulating substrates 4 on which the conductor circuit patterns 1 are formed are arranged in the outermost layer, and the multilayer plate penetrates inside thereof. Hole part 16 hollowed out in a concentric circle larger than the diameter of the hole
Insulating substrate 2 without catalyst and prepreg with catalyst 5
And a step of forming a multi-layered substrate 7 by heating and pressurizing the multi-layered substrate 7 as shown in FIG. 3 (B), and a predetermined process for forming the multi-layered substrate 7 as shown in FIG. 3 (C). And the step of forming the through hole 8 at the position of the conductive circuit pattern 1 on the end surface of the insulating substrate 3 containing the catalyst on the inner wall of the through hole 8 of the multilayer substrate 7 as shown in FIG. 3D. There is an example in which high density is achieved by selectively forming divided via holes 12 and normal through holes 13 through a step of forming a conductor layer 11 to be connected by electroless plating (Japanese Patent Application No. 61-61). −029361).

[Problems to be solved by the invention]

However, in the above-mentioned conventional manufacturing method, in order to provide a hole formed in a concentric circle having a diameter larger than the diameter of the through hole at the drilling position of the through hole for forming a normal through hole on the insulating substrate without a catalyst inside the multilayer substrate. However, there is a drawback in that a clearance is required between the through hole and the hole portion, the basic lattice in the plane direction cannot be made small, and it becomes a factor that hinders high density in the plane direction.

Further, since it is necessary to fill the above-mentioned holes only with the resin containing the catalyst impregnated in the catalyst-containing prepreg, if the thickness of the insulating substrate without the catalyst is too thick, voids will occur, which causes a restriction on the thickness. There is a drawback that it becomes a limiting factor for the electrical characteristics, especially the impedance characteristics, of the multilayer board.

Furthermore, it is necessary to adjust the amount of resin in the catalyst-containing prepreg layer according to the number of holes, and it is difficult to control the smoothness of the multilayer plate and the interlayer thickness depending on the degree of concentration of the holes in the plane direction. There is a drawback that

An object of the present invention is to provide a method of manufacturing a multilayer printed wiring board which has a high density, has no restriction on impedance characteristics, and can control smoothness and interlayer thickness.

[Means for solving the problem]

The method for manufacturing a multilayer printed wiring board according to the present invention comprises two sets of catalyst-containing insulating substrates each having a catalyst-free insulating substrate having conductor circuit patterns provided on both front and back surfaces in advance as an inner layer and having a copper foil on one entire surface outside thereof. A step of forming a multi-layer substrate by inserting a catalyst-containing prepreg with the copper foil on the outside and heating and pressurizing the step; forming a through hole at a predetermined position of the multi-layer substrate; Formed by a step of adsorbing a catalyst on the inner wall of the through hole that has not been masked after masking a part of the above, a step of removing the mask, and an insulating substrate containing the catalyst on the inner wall of the through hole and the prepreg containing the catalyst. And a step of forming a conductor layer by electroless plating including a catalyst-containing insulating plug and a portion where the catalyst is adsorbed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (A) to 1 (F) are vertical cross-sectional views showing the manufacturing process of the first embodiment of the present invention in the order of steps.

In the first embodiment, first, as shown in FIG. 1 (A), an insulating substrate 2 without a catalyst, in which conductor circuit patterns 1 are formed on both front and back surfaces in advance by a photoprinting method, is arranged as an inner layer, and the outside thereof is provided. Two sets of catalyst-containing insulating substrates 4 each having a copper foil 3 on one side are set with the copper foil 3 facing outward and a prepreg 5 containing a catalyst interposed therebetween.

Next, as shown in FIG. 1 (B), heating and pressurization are performed to obtain a multilayer substrate 7 including the catalyst-containing insulating layer 6 and the catalyst-free insulating substrate 2.

Next, as shown in FIG. 2 (C), through holes 8a and 8b are drilled at predetermined positions by an N / C drilling device.

 Next, the through hole 8a forming the divided via hole is formed.
By the photo printing method, for example, a dry film manufactured by Du Pont
Rumliston 1220 After forming the mask 9 using
Dip in a catalyst solution based on palladium chloride to
The catalyst 10 is absorbed on the entire inner wall of the through hole 8b not provided with the groove 9.
To wear.

Next, as shown in FIG. 1 (E), after removing the mask 9 with an organic solvent (not shown), electroless copper plating is applied to both the front and back surfaces of the multilayer substrate 7 and the inner walls of the through holes 8a, 8b. The conductor layer 11 is formed. In this case, in the through hole 8a, the conductor layer 11 is formed only on the catalyst-containing insulating layer 6, and the catalyst-free insulating substrate 2 is formed.
Therefore, the conductor layer 11 is separated at the inner wall of the through hole 8a, and the conductor circuit pattern 1 and the copper foil 3 of the outer layer are connected to each other, while the through hole 8a is first adsorbed. The catalyst 10 forms the conductor layer 1 on the entire inner wall.

Next, as shown in FIG. 1 (F), a multilayer printed wiring board including via holes 12 and normal through holes 13 which are divided by forming a circuit of the outermost layer by a photo printing method.
14 is obtained.

FIG. 2 is a vertical cross-sectional view showing the manufacturing method of the second embodiment of the present invention in the order of steps.

In the first embodiment, as shown in FIG. 1 (F), the insulating substrate 2 without catalyst was used as the inner layer, but in the second embodiment, as shown in FIG. 2 (A), the catalyst was used. A thin resin layer containing a catalyst between the insulating substrate 2 without the conductor and the conductor circuit pattern 1.
A multilayer printed wiring board 14 shown in FIG. 2 (B) is manufactured by the same manufacturing method as in the first embodiment, using the inner layer provided with 15.
Get.

The second embodiment has the advantage that the connection between the conductor layer 11 and the conductor circuit pattern 1 has a T-shaped structure in the separated via hole 12, and the connection reliability in this portion is improved.

[Effects of the Invention] As described above, according to the present invention, when the divided via holes are selectively formed in the multilayer printed wiring board, the basic grid arrangement, the interlayer thickness, the characteristic impedance design, etc., as in the prior art, can be obtained. There is an effect that it is possible to obtain a high-density multi-layer printed wiring board having various wiring restraint properties without various design constraints.

[Brief description of the drawings]

1 (A) to 1 (F) are longitudinal sectional views showing the manufacturing method of the first embodiment of the present invention in the order of steps, FIG. 2 (A),
(B) is a longitudinal sectional view showing the manufacturing method of the second embodiment of the present invention in the order of steps, and FIGS. 3 (A) to (D) are examples of the conventional method for manufacturing a multilayer printed wiring board. FIG. 6 is a vertical cross-sectional view showing in the order of steps to be performed. 1 ... Conductor circuit pattern, 2 ... Insulating substrate without catalyst,
3 ... Copper foil, 4 ... Catalyst-containing insulating substrate, 5 ... Catalyst-containing prepreg, 6 ... Catalyst-containing insulating layer, 7 ... Multilayer substrate, 8a, 8b ... Through holes, 9 ... Mask, 10 ...... Catalyst, 11
...... Conductor layer, 12 …… Divided via holes, 13 …… Normal through holes, 14 …… Multilayer printed wiring board, 15 …… Thin catalyst-containing resin layer, 16 …… Hole part.

Continuation of the front page (56) Reference JP-A-54-43568 (JP, A) JP-A-62-186595 (JP, A) JP-A-63-280496 (JP, A) JP-A-51-27458 (JP , A) JP-A-60-101996 (JP, A) JP-A-62-186594 (JP, A)

Claims (1)

(57) [Claims] 1. A catalyst-free insulating substrate having conductor circuit patterns provided on both front and back surfaces in advance is disposed on an inner layer, and two sets of catalyst-containing insulating substrates each having a copper foil on one entire surface are provided on the outer side with the copper foil on the outer side. And then heat and pressurize the catalyst-containing prepreg to form a multilayer substrate, form a through hole at a predetermined position of the multilayer substrate, and mask a part of the through hole. A step of adsorbing a catalyst on the inner wall of the through hole that is not masked, a step of removing the mask, a catalyst-containing insulating layer and a catalyst formed by the catalyst-containing insulating substrate and the catalyst-containing prepreg on the through-hole inner wall And a step of forming a conductor layer by electroless plating, including a portion to which is adsorbed, a method for manufacturing a multilayer printed wiring board.