JP2689543B2 - Dynamic frequency divider - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic frequency divider circuit that operates in a high frequency region such as a microwave band, such as a GaAs dynamic frequency divider circuit.

[Prior Art] A dynamic frequency dividing circuit capable of realizing high-speed operation with a simple circuit configuration has been frequently used in a high frequency region such as a microwave band as compared with the related art. FIG. 2 shows the configuration of this dynamic frequency dividing circuit. The dynamic frequency dividing circuit is configured by connecting an inverter circuit 21, a first transfer gate 22, a buffer circuit 23, and a second transfer gate 24 in a ring shape. In this circuit, the input signal is given to the first transfer gate 22 as a gate signal, and the input inverted signal from the input inverting circuit 25 is given to the second transfer gate 24 as a gate signal, which is based on the phase difference between the two signals. The frequency division operation is performed by the delay of the feedback signal. Generally, in a GaAs integrated circuit, a circuit as shown in FIG. 3 is used as the inverter circuit 21 which operates at high speed, and a circuit as shown in FIG. 4 is used as the buffer circuit 23.

[Problems to be Solved by the Invention] In order to increase the upper limit operating frequency (fmax) of the dynamic frequency dividing circuit configured as described above, it is effective to increase the gate width (Wg) of the transfer gate FET. There is a transfer gate if the gate width is increased.
The leakage current at the FET cutoff also increases, the potential holding time of the transfer gate terminal becomes shorter, and the lower limit operating frequency (fmin) also increases. Therefore, there is a drawback that a frequency divider circuit having a wide operating frequency band cannot be realized.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a dynamic frequency dividing circuit having a wide operating frequency band.

[Means for Solving the Problems] According to the present invention, a first transfer gate interposed between an inverter output and a buffer input is provided as a first transfer gate FET having a large gate width and a second transfer gate having a small gate width. The second transfer gate, which is configured by parallel connection with the transfer gate FET and is interposed between the buffer output and the inverter input, is connected to the third transfer gate FET having a large gate width and the fourth transfer gate having a small gate width. It is configured by parallel connection with the gate FET. Then, a first high-pass filter and a first low-pass filter for low-pass filtering and a high-pass filtering of the input signal, and a second high-pass filter and a second low-pass filter for low-pass filtering and high-pass filtering of the input inverted signal. Is provided, and the output of the first high-pass filter is given as the gate signal of the first transfer gate FET, and the output of the first low-pass filter is supplied to the second transfer gate FE.
The gate signal of T, the output of the second high-pass filter is given as the gate signal of the third transfer gate FET, and the output of the second low-pass filter is given as the gate signal of the fourth transfer gate FET. .

[Operation] According to the present invention, for an input signal having a high frequency,
Since the first and second high-pass filter outputs are given to the gates of the first and third transfer gate FETs, a transfer gate FET having a large gate width (Wg) is selected,
The upper limit frequency can be increased. On the other hand, for low-frequency input signals, the output of the first and second low-pass filters is given to the gates of the second and fourth transfer gate FETs, so a transfer gate FET with a small gate width (Wg) is selected. It is possible to reduce the lower limit frequency.

Such a high-pass filter and a low-pass filter function as switching means for switching between the FET having a large gate width and the FET having a small gate width according to the frequency of the input signal. Therefore, according to the present invention, a wide operating frequency can be realized.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of a dynamic frequency divider circuit according to an embodiment of the present invention. The output of the inverter circuit 1 is
It is connected to the input of the buffer circuit 2 via the transfer gate FETs 3 and 5 connected in parallel.
Is connected to the input of the inverter circuit 1 via transfer gate FETs 4 and 6 connected in parallel. The transfer gate FETs 3 and 4 have a relatively large Wg (for example, 50μ
m) FET, whose gate electrode terminals 7 and 8 are MIM (Met
al Insulator Metal) Input terminals IN and ▲ via high-pass filters 11 and 12 composed of capacitors 15 and 16 and R elements, respectively.
Connected to ▼. On the other hand, the transfer gate FETs 5 and 6 have relatively small Wg (for example, 10 μm)
The gate electrode terminals 9 and 10 are connected to the input terminal IN and ▲ ▼ via the low-pass filters 13 and 14, respectively.

Now, when an input signal and an input inverted signal are applied to the input terminals (IN, ▲ ▼), respectively, signals attenuated according to the characteristics of each filter are added to the transfer gate FETs 3, 4, 5, 6. Here, the cutoff frequency of the high-pass and low-pass filters is selected, for example, by making an appropriate overlap between the fmax determined by Wg of the transfer gate FETs 3 and 4 and the fmin determined by Wg of the transfer gate FETs 5 and 6. Moreover, if the cutoff level of the filter is set below the input sensitivity level of the transfer gate FETs 3, 4 and 5, 6, the transfer gate FETs 3 and 4 will operate in the region near the upper limit operating frequency, and the transfer gate FETs 5 and 6 will operate. Does not operate, the transfer gate FETs 5 and 6 operate in a region close to the lower limit operating frequency, and it is possible to prevent the transfer gate FETs 3 and 4 from operating.

As a result, the operating frequency can be expanded according to the characteristics of the transfer gate FETs 3, 4, 5, and 6.

The present invention is not limited to the embodiments described above. Although the MIM capacitors 15 and 16 are used for the high-pass filters 11 and 12 in the above-mentioned embodiment, it is possible to use diodes instead of them or to use reverse bias to the FETs to use them as capacitors. In this case, the capacitance value can be adjusted by adjusting the reverse bias value.

[Effects of the Invention] As is clear from the above description, the present invention focuses on Wg of the transfer gate FET, which is one of the factors that determine the operating frequency band of the frequency dividing circuit, and focuses on the high frequency region and the low frequency region. Two different transfer gate FETs with Wg suitable for each are prepared and switched according to the frequency band used, so it is possible to raise the maximum operating frequency and lower the minimum operating frequency. This has the effect of expanding the operating frequency range.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a dynamic divider circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional dynamic divider circuit, and FIG. 3 is a circuit diagram of an inverter circuit in FIG. FIG. 4 is a circuit diagram of the buffer circuit in FIG. 1, 21; Inverter circuit, 2, 23; Buffer circuit, 3 to 6; Transfer gate FET, 7 to 10; Gate electrode terminal, 1
1,21; High-pass filter, 13,14; Low-pass filter, 15,
16; MIM capacitor, 17; output terminal, IN, ▲ ▼; input terminal, 22, 24; transfer gate, 25; input inverting circuit

Claims (1)

(57) [Claims] 1. An inverter, a first transfer gate, a buffer and a second transfer gate are circularly connected in this order, and an input signal is gated to the first transfer gate and an input inverted signal is gated to the second transfer gate. In a dynamic frequency divider circuit which is inputted as a signal and whose output is taken out from the buffer, a first high-pass filter for high-pass filtering the input signal, a first low-pass filter for low-pass filtering the input signal, A second high-pass filter for high-pass filtering the input inverted signal; and a second low-pass filter for low-pass filtering the input inverted signal, wherein the first transfer gate comprises:
A first transfer gate having a large gate width for inputting the output of the first high-pass filter as a gate signal
An FET and a second transfer gate FET having a small gate width for inputting the output of the first low-pass filter as a gate signal are connected in parallel, and the second transfer gate is the second high-pass filter. With a large gate width that inputs the output of
Of the second low-pass filter and a fourth transfer gate having a small gate width for inputting the output of the second low-pass filter as a gate signal are connected in parallel to each other. circuit.