JP2687893B2 - Image memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory control device, and more particularly to a MUSE decoder field memory control device.

[0002]

2. Description of the Related Art As a method of band-compressing a wideband high-definition television signal to a practical level for transmission, the original high-definition television signal is subjected to a sub-Nyquist sample that makes a round in four fields. MUSE (Multiple Sub-Ny)
There is a qist Sampling Encoding method.

[0003] The MUSE system is a system developed by NHK (Japan Broadcasting Corporation), and various documents (eg, December 1, 1990)
Since it is described in "MUSE-High-Definition Transmission System" published by IEICE, Yuichi Ninomiya, etc., detailed description is omitted.

In the MUSE system, the luminance signal is 22 MH
z, high-definition television signal (hereinafter, baseband signal) with a band up to about 7 MHz for color signals, bandwidth 27 MHz
About 8MHz to transmit on one satellite broadcasting channel
Wideband compression processing to. The MUSE decoder demodulates the band-compressed signal (hereinafter referred to as MUSE signal) to the original baseband signal.

FIG. 4 is a schematic diagram showing the structure of the MUSE signal. In the MUSE method, interlaced scanning is used, and the first field 24 of 563 lines and the second field 25 of 562 lines form one frame. VITS in the figure
The data portion of # 1 signal 24 / VITS # 2 signal 25, frame pulse # 1 signal 28 / frame pulse # 2 signal 29, audio / independent data 30, control signal 31, and clamp level 32 is not image data but these data. A certain line (1 line to 46 lines, 563 line to 604 lines, 1125 line) is called a vertical blanking period. In FIG. 5, the vertical blanking period 33 is indicated by diagonal lines, and the image data period 34 is indicated by white outline.

FIG. 3 is a block diagram showing a part of the conventional MUSE day code processing. The MUSE signal is supplied to the input terminal 1. The selector 2 is a selector for inserting a still image signal in a frame, and switches the signal one frame before and the current signal for each sample of the 32 MHz clock to perform interpolation. As the signal to be interpolated, the signal one frame before which is delayed by the two field memories 23 and 5 is used.
Inter-frame interpolation is a process of performing image reproduction by using sample points of two consecutive frames, as described in the above-mentioned document "MUSE-Hi-Vision transmission system" P17. With motion vector correction as noted. The motion correction processing of the MUSE decoder is proposed by Japanese Patent Laid-Open No. 59-221090, "Motion Correction Subsample Transmission System". According to the publication, in the motion correction process, the motion information detected on the encoder side (hereinafter referred to as a motion vector) is delayed based on the position information obtained by adding the information of the sample position based on the predetermined sample position relationship between the adjacent frames. The interpolation position of the sample value to be interpolated is corrected. According to the above-mentioned document "MUSE-Hi-Vision transmission system" P120,
The motion vector is transmitted in the range of 4 bits (+7 to -8 clocks) horizontally and 3 bits (+3 to -4 lines) vertically (see Tables 1 and 2).

[0007]

[Table 1]

[0008]

[Table 2]

FIG. 6 shows the state of image data reproduced by interframe interpolation. ∘35 represents even frame data, and × 36 represents odd frame data.

The field memories 23 and 5 necessary for the interframe interpolation processing shown in FIG. 3 are the MUSE shown in FIG.
It is necessary to store the signal for one field period. The data capacity of the interpolated signal in one field period is as follows: First field: 960 samples × 563 lines × 8 bits = 540,4
80 words x 8 bits Second field: 960 samples x 562 lines x 8 bits = 539,5
It is 20 words x 8 bits. In a conventional MUSE decoder, a field memory for interframe interpolation processing is disclosed in, for example, Japanese Patent Laid-Open No.
One as proposed in 207425 gazette
Since a memory having a sufficient capacity for storing the field period is used, the address is reset by the VD signal (pulse signal generated at the beginning of the field, waveform 14 in FIG. 2) generated from the synchronization processing 6 shown in FIG. Then, a delay of one field period could be obtained. Also, this memory has a built-in vertical motion vector correction function,
Correction was performed in the field memory 5. Since the delay amount for one frame period in consideration of vertical motion vector correction (+3 to -4 lines) is 1121 to 1128 lines,
In the conventional example, this delay amount is divided into two memories, and the delay amount is constituted by the field memory 23: 560 lines and the field memories 5: 561 to 568 lines (delay amount variable for each line).

As described above, the conventional memory has a very large capacity as compared with a memory corresponding to the NTSC signal described later, and therefore, it tends to be specialized for the MUSE signal.

On the other hand, as a frequently used image memory, a field memory corresponding to an NTSC signal which is a current television system (hereinafter referred to as an NTSC signal memory) is known. This memory has a FIFO structure and a capacity of 256K.
It is about word x 8 bits. This capacity is NTS
Number of pixels in one field of C signal 910 samples x 263 lines x 8 bits = 239,3
Sufficient to store 30 words x 8 bits. This memory is controlled by a write / read clock, a write / read enable signal, and a write / read reset signal. Write / read clock: A clock for performing a write / read operation, and the write / read address is also incremented. : Write / Read Enable (WE / RE) Write / Read operations can be prohibited. The address is retained when the operation is prohibited. Write / read reset (hereinafter WRST / RRS
T): Reset input for initializing the write / read address.

By the way, since many high-definition television receivers including a MUSE decoder have a manufacturing process such as a three-dimensional YC separation of NTSC signals (for example, the device described in Japanese Patent Laid-Open No. 1-259694), it is used for NTSC signals. Memory is often used as well. Therefore, if an NTSC signal memory can be used for the MUSE decoding process, the memory can be reduced, and by using a general NTSC system memory rather than the MUSE system, the cost can be significantly reduced. be able to. However, the data capacity of one field period of the MUSE signal (data of 560 lines in consideration of vertical motion vector correction processing = 53760)
0 word × 8 bits is more than twice the field memory capacity (256 K words × 8 bits) corresponding to the NTSC signal. Therefore, three NTSC signal memories are required to store the MUSE signal for one field period. 1 in the video processing of the NTSC signal as described above.
Since it is general to use the delay signal of the frame (two fields) period, one more memory must be used for delaying the MUSE signal.

[0014]

When the interframe interpolating section of the MUSE decoder is constructed with the memory for the NTSC signal as described above, three NTSC signals are stored to store the decoder capacity in one field period of the MUSE signal. Memory is required. However, since two NTSC signal memories compose a delay of one frame period of the NTSC signal, even the configuration of the MUSE decoder requires two NTSC signals.
It is a problem to be solved by the present invention that the SC signal memory can delay one field period of the MUSE signal.

[0015]

In order to solve such a problem, the present invention demodulates a MUSE signal band-compressed by sub-samples that make a cycle of four fields into an original broadband high-definition television signal. MUS to play
In the E decoder, horizontal lines are counted based on the synchronization signal detected by the synchronization process, the line number in the MUSE signal is detected, and it is detected in order to control the operation of the memory in the vertical blanking period. By decoding the line number to generate a control signal, and using the image memory for NTSC signal having a capacity less than the data capacity of one field period of the MUSE signal, the MUSE signal is controlled by the control signal.
A means for obtaining a delayed signal for one field period of the signal is provided.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a memory control device according to the present invention will be described below with reference to the drawings.

As described in the prior art, the NTSC signal memory has a capacity of 256 K words × 8 bits, and this capacity is 256 K words × 8 bits / 960 samples = 273 when converted to the number of lines of the MUSE signal. ．
066. . . It becomes a line and it can be seen that 273 lines of MUSE signal can be stored. By the way, as shown in FIG. 5, the MUSE signal has a vertical blanking period 33, and since this period is not video data, it is not necessary to perform interframe interpolation processing. Therefore, the data capacity that must be held per field is 520 lines shown in the image data 34 of FIG. In this case, the capacity is sufficient by using two NTSC signal memories (520 lines <273 lines × 2 = 546 lines).

FIG. 1 is a block diagram showing an embodiment. The MUSE signal supplied to the input terminal 1 is delayed for one frame period, interpolated between frames by the selector 2, and output terminal 1
Outputting a still image signal from 5 is the same as in the conventional example.
The difference from the conventional example is that a delayed signal for one field period can be obtained by two memories for NTSC signals. To obtain a delayed signal for another field period, the same field memory for MUSE signal as in the conventional example is used. The memories A3 and B4 in FIG. 1 are memories for NTSC signals, and have a control signal generation circuit 7 for controlling these memories. The control signal generation circuit 7 generates a signal required for memory control based on the field head signal (VD signal) and line head signal (HD signal) from the synchronization processing 6. Two kinds of enable signals EN are used to control the memory.
BA / ENBB (8/10 in Fig. 1) and reset signal RS
Perform with TA / RSTB (9/11 in FIG. 1). The correspondence between each signal and the memory control signal is as follows.

ENBA ... WE / RE of memory A, WE RSTA of memory B ... WRST / RRST of memory A, WRST of memory B ENBB ... RERSTB of memory B ... RRST of memory B Read clock is MU
The SE system 32.4 MHz system clock is used.

Next, the operation of the memory according to the control signal will be described with reference to the timing chart of FIG. In the figure, the portion corresponding to the vertical blanking period is represented by a halftone dot, the data portion to be stored is represented by an outline, the WE and RE signals are at the “H” level, data writing and reading are prohibited, and the WRST and RRST signals have an address at the falling edge. It shall be initialized. In addition, the waveform representing the data is connected by the curved line of the arrow to show the movement of the data. (1) Writing of Memory A Regarding the input data (waveform 13) of the memory A, the WE signal (waveform 15) is input so as to inhibit writing of 43 lines in the odd field and 42 lines in the even field during the vertical blanking period. .

Since the write address is initialized at the same time that the memory is made writable, the WRST signal is input so as to fall when the waveform 15 becomes "L". Further, since the amount of data to be written in the memory is 260 lines, the WRST signal is fallen every 260 lines. Therefore, the WRST signal is 2 per field.
The waveform 16 has a rising pulse. (2) Reading of memory A The RE signal of memory A is the WE signal (waveform 15) and the RRS
As the T signal, the same signal as the WRST signal (waveform 16) is input. As a result, the output data of the memory A has the waveform 1
7, the signal has a shape such that the vertical blanking period comes at the center of the video period of one field. (3) Reading of memory B Memory B has the same WE signal (waveform 18) and WR as in (1).
Input ST signal (waveform 19) and input data (waveform 1
Writing is performed every 260 lines except the vertical blanking period of 7). (4) Reading of memory B The RE signal (waveform 21) and the RRST signal (waveform 20) input to the memory B are WE at the time of writing of (3), respectively.
30 from the signal (waveform 18) and WRST signal (waveform 19)
Input the signals sent from X lines of 2 to 562 lines. As a result, the output data of the memory B is the waveform 22
As a result, a signal delayed by X lines from the input signal (waveform 13) of the memory A is obtained.

As can be seen from the above description,
The control signals shown in can use the same signal.

WE / RE of memory A (waveform 15), WE of memory B (waveform 18) WRST / RRST of memory A (waveform 16), WRST of memory B (waveform 19) Since it is the RE signal (waveform 21) and the RRST signal (waveform 20), the control signal generation circuit 7 of FIG. 1 generates two types of total enable signals and two types of reset signals, so that the MUSE signal X line (302 ≦ X ≦ 562) A period delay can be obtained. If these control signals are ENBA, ENBB (8, 10 in FIG. 1) and RSTA.RSTB (9, 11 in FIG. 1), the correspondence with each memory is as shown in FIG. Become.

Such a control signal can be easily obtained by detecting the line number with the line counter on the basis of the VD signal shown by the waveform 14 in FIG. 2 and performing the decoding process.

By changing the timings of the RE signal and the RRST signal input to the memory B, the delay amount is set to 302 to 56.
Can be changed to 2 lines. In consideration of performing vertical motion vector correction of 561 to 568 lines in the field memory 5 as in the conventional example, X = 560.
Further, since the maximum delay amount is 562 lines, which is the same as the number of lines in the first field period, it is possible to set the variable delay amount of the field memory 5 to 559 to 566 lines by setting X = 562.

Therefore, according to one embodiment of the memory controller, the delay of one field period of the MUSE signal is set to two NT.
It can be configured to obtain with a memory for SC signals.

[0027]

As described above, according to the present invention, in the MUSE decoder that demodulates and reproduces the original wideband high-definition television signal from the MUSE signal band-compressed by the sub-samples that make a cycle of four fields, Horizontal lines are counted based on the synchronization signal detected by the synchronization processing, the line number in the MUSE signal is detected, and the detected line number is decoded to control the memory operation during the vertical blanking period. Since the control signal is generated by using two image memories for NTSC signals having a capacity less than the data capacity of one field period of the MUSE signal, the MUSE signal is controlled by the control signal.
It is possible to obtain a delayed signal for one field period of the signal, and to share the memory with the video signal processing of the NTSC signal such as the three-dimensional YC separation.
In addition, the use of a general NTSC memory rather than the MUSE memory can greatly contribute to the cost reduction effect, so that the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment.

FIG. 2 is a timing chart showing a memory operation of one embodiment.

FIG. 3 is a block diagram showing an interframe interpolation unit of a conventional MUSE decoder.

FIG. 4 is a schematic diagram showing a signal form of a MUSE signal.

FIG. 5 is a schematic diagram showing a video signal area / vertical blanking period in the MUSE signal format.

FIG. 6 is a schematic diagram showing a signal form after interframe interpolation.

[Explanation of symbols]

1 MUSE signal input terminal 2 Interframe interpolation selector 3 NTSC signal field memory A 4 NTSC signal field memory B 5 MUSE signal field memory with motion vector correction processing 6 Synchronization processing unit 7 Control signal generation unit No. 8 Enable signal ENBA 9 Reset signal RSTB 10 Enable signal ENB 11 Reset signal RSTB 12 Still image signal output terminal 13 Memory A input data waveform 14 VD signal waveform 15 Memory A enable signal waveform 16 Memory A reset signal waveform 17 Memory A output data memory B input data waveform 18 memory B write enable signal waveform 19 memory B write reset signal waveform 20 memory B read reset signal waveform 21 memory B read enable signal waveform 22 memory B output signal waveform 23 USE signal field memory 24 first field period 25 second field period 26 VITS # 1 signal 27 VITS # 2 signal 28 frame pulse # 1 signal 29 frame pulse # 2 signal 30 voice / independent data 31 control signal 32 clamp level 33 vertical Blanking period 34 Video data period 35 Even frame data 36 Odd frame data

Claims (1)

(57) [Claims] 1. A MUSE for demodulating and reproducing an original wideband high-definition television signal from a MUSE signal band-compressed by sub-samples that make a cycle of four fields.
The decoder detects the line number in the MUSE signal by counting the number of horizontal lines based on the synchronization signal detected in the synchronization process, and detects the line number in the vertical blanking period to control the memory operation. The line number is decoded to generate a control signal, and two field memories for the NTSC signal having a capacity less than the data capacity of one field period of the MUSE signal are used,
A memory control device for obtaining a delay signal of one field period of a MESE signal by controlling with the control signal.