JP2685435B2 - Method of relieving defects in semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for repairing defective memory cells by replacing them with spare memory cells. [Prior Art] High integration of semiconductor memory has been rapidly progressing in recent years.
VLSI (Very Large Scale Integrated Circuit) products have also been mass-produced. However, as the integration becomes higher, the chip size tends to increase, and the decrease in yield due to this has become a problem. As a countermeasure against this, there is a so-called defect relief technique in which a defective memory cell is repaired by replacing it with a spare memory cell provided on a chip in advance. This technique is described, for example, in I.E.E.Transaction on Electron Devices, ED-26, pages 853 to 860, June 1979 (I.
EEE, Trans.on Electron Devices, ED−26, pp.853−860, J
1979), it is a very effective method for improving the yield of semiconductor memories. [Problems to be Solved by the Invention] In the above-mentioned conventional technique, defective memory cells are replaced with spare memory cells within one chip, and therefore, defects exceeding the number of spare memory cells provided on the chip are involved. If there is, repair is impossible. Further, although a memory tester is usually used for restoration, there is a problem that the tester is used for a longer time due to the time required for restoration, resulting in an increase in test cost. An object of the present invention is to reduce the manufacturing cost by making it possible to use a chip that has been conventionally unrepairable when a memory device is constructed using a large number of memory chips, and to perform the repair automatically. It is to provide a method of reducing the test cost. [Means for Solving the Problems] In order to achieve the above object, in the present invention, a spare chip is provided in the memory device, and a defective memory cell is repaired by performing replacement between chips. Further, each memory chip is automatically tested by the self-test circuit provided in the memory device to perform necessary repair. [Operation] By replacing defective memory cells between chips,
With the conventional technology (replacement within an individual chip), it becomes possible to repair even defects that cannot be repaired. As a result, the yield of chips can be improved and the manufacturing cost can be reduced. Further, since the self-test circuit automatically performs the above repair, the test cost can be reduced as compared with the conventional technique (repair by the memory tester). Embodiment] An embodiment of the present invention will be described below with reference to FIG. The figure is a block diagram of a semiconductor memory device according to the present invention. In the figure, 1 is a semiconductor memory chip, 2 is a decoder, 3 is a control circuit, 4 is a coincidence detector, and 5 is a self-test circuit. The memory chips 1 include n basic memory chips and m spare memory chips for replacing defective basic memory chips. The coincidence detector 4 is a circuit for storing a defective address and comparing it with the address input from the address input terminal 6. Self test circuit 5
Is a circuit for testing each memory chip 1 when the power is turned on and writing information such as a defective address into the coincidence detector 4, 10 is a CPU, 11 is a ROM, 12 is a test pattern generation circuit, 13 is a selector, 14 Is a majority circuit. This memory device uses the information written in the coincidence detector 4 by the self-test circuit 5 to perform so-called soft defect relief.
The operation of this memory device will be described below. First, the case of reading will be described. Of the address signals input from the address input terminal 6, the portion used for selecting the memory chip (log2 n bits) is the decoder 2
And becomes the chip selection signal CS of the basic memory chip. The remaining address signals are commonly input to the address terminals of all the memory chips. At this time, the CSs of the m spare memory chips are selected.
Therefore, data is simultaneously read from the same address of one basic memory chip, m spare memory chips, and a total of (m + 1) chips. On the other hand, the coincidence detector 4 determines whether or not the input address is a defective address, and which spare chip is used if the input address is a defective address, and outputs the result as a flag. The control circuit 3 receives the flag, selects one of the data read from the memory chip, and outputs it to the data input / output terminal 7. When writing, the control circuit 3 uses the data input / output terminal 7
The data is taken in from and is sent to one memory chip according to the flag. At the same time, the write enable signal WE is input to the memory chip. Other operations are the same as in the case of reading. As is clear from the above description, the defect relief of the present memory device is the replacement in chip units. That is, when the memory cell at the address a of the basic memory chip is defective, the memory cell is always replaced with the memory cell at the address a of the spare memory chip. M which spare chip to use
Although it has a certain degree of freedom, it cannot be replaced with a memory cell having an address other than a. This constraint seems to lower the repairable probability at first glance, but repair is possible as long as there is no defect at the same address in (m + 1) or more memory chips. Therefore, if m is 4 or more, the repairable probability is almost zero. Does not fall. Moreover, this method has the following advantages. First, only chip-by-chip switching needs to be performed (address signals may be common to all chips).
Therefore, control becomes easy. Second, since the memory chip and the coincidence detector can operate simultaneously, the access delay is small. That is, a high-speed memory device having a small amount of hardware can be manufactured. Next, the coincidence detector 4 will be described in detail. FIG. 2 shows an example of the structure of the coincidence detector, in which 20 is an associative memory and 21
Is a priority determination circuit, and 22 is a register. Associative memory 20
Each row stores the address of the defective memory cell, and each row of the register 22 stores information as to whether the defective memory cell is replaced with a spare memory chip. The associative memory can be read and written in the same way as ordinary memory, but also has a data search function. This search function is used here. When the address signal is input from the input terminal 23, it is compared with the data stored in each row of the associative memory 20. As a result, when the data stored in a certain row is matched, a match signal is output to the match detection line 24 of that row, and the data stored in the corresponding row of the register 22 is output to the output terminal.
It is output to 26. Since the comparison in the associative memory is performed in parallel for all the rows, a faster search is possible as compared with the case where the comparison circuit is externally attached to an ordinary memory. Here, the associative memory 20 stores ordinary binary information “0”,
Not only "1" but also don't care value "X" can be stored. The don't care value is a value that is considered as “match” regardless of whether the comparison partner is “0” or “1”. The advantages of doing this are described below. In general, a memory failure is often not only one memory cell failure, but also one word line or one data line, or all or most of the memory cells. Therefore, it is desirable that the spare can be replaced by the word line (row) or the data line (column) as a unit. This can be easily achieved by using the don't care value "X" as follows. A chip address, a row address, and a column address are put in the associative memories 30, 31, and 32, respectively. When replacing word lines, the column address part is set to "X". When replacing data lines, the row address part is set to "X". For example, in the example of the figure, 41 is the replacement in word line units, and if the row address of the chip whose chip address is "1" is "3", it is replaced by the first spare chip regardless of the column address. Shows. 42
Is the replacement for each data line, and the chip address is "2",
If the column address is "5", it indicates that replacement is performed with the second spare chip regardless of the row address. When replacing in units of memory cells, the address of the memory cell to be replaced may be left as it is, as indicated by 40. Further, as shown by 43, if the least significant part of the column address part and the row address part is set to "X", the replacement can be performed in units of two word lines. In this example, it is shown that the word lines of the row address of the chip whose chip address is "3" and whose row addresses are "4" and "5" are replaced with the first spare chip.
This is effective when two adjacent word lines are simultaneously defective due to a short-circuit between the word lines. It is of course possible to replace the two data lines as a unit by the same method. The priority determination circuit 21 is a circuit for transmitting only the match signal having the highest priority to the register 22 when the match signals are output from two or more match detection lines (here, the upper side indicates the priority level is It is expensive). For example, the chip address, row address, and column address are "0", "1", and "2", respectively.
In the case of, a match signal is output from the rows of 40 and 44, but since 40 has a higher priority, the output becomes "3". That is,
The work line whose row address is "1" and whose chip address is "0" is replaced by the first spare chip, except for the memory cell whose column address is "2", which is replaced by the third spare chip. To be done. This is effective when the spare chip is defective. Note that "X" is written to all the unused rows of the associative memory as shown in 45 to 47, and all "0" s are written to the corresponding registers (in this case, when the output is "0", the backup chips are It is not necessary to replace).
Since a match signal is always output to the match detection lines of lines 45 to 47,
If the input address does not match any of 40 to 44, the contents of the register corresponding to 45, that is, "0"
Is read. Therefore, the replacement with the spare chip is not performed. As described above, by using the associative memory that can store the three values of “0”, “1”, and “X” and the priority determination circuit, it is possible to efficiently realize a wide variety of defect relief. This contributes to increase the relief probability. An associative memory that can store three values can be realized, for example, as shown in FIG. In the figure, 100 is one memory cell of the associative memory, and although only one memory cell is shown in the figure, a large number of cells are arranged vertically and horizontally. The associative memory cell 100 includes flip-flops 101 and 102 and a match detection gate 10
With 3. Each flipflop is a pair of nodes (118 and 119).
And 128 and 129), one of the nodes has a high potential (approximately equal to the power supply voltage Vcc; hereinafter abbreviated as “H”), and the other node has a low potential (approximately equal to ground voltage; hereinafter abbreviated as “L”). Information is stored by becoming. When storing the value "0", the nodes 118, 119, 128, 129 are "L",
When storing the value “1” in “H”, “L” and “H” respectively, it becomes “H”, “L”, “H” and “L” and when storing the value “X” respectively Set to L "," H "," H "," L ". When reading and writing as normal memory,
Set the word line 104 to "H" to turn on the MOS transistors 112, 113, 122,
123 is made conductive, and nodes 118, 119, 128, 129 and data lines 105,
Data is transferred between 106, 107, and 108, respectively. At the time of search, the word line 104 is set to "L" and the precharge signal φp is applied in advance to set the coincidence detection line 24 to "H". Next, when searching for the value “0”, the data lines 106, 107
To "H" and "L" respectively, and to search for the value "1", set them to "L" and "H" respectively. As a result, if the coincidence detection line 24 is discharged to “L”, it is determined as “mismatch”, and if not discharged, it is determined as “coincidence”. When the value "0" is stored and the value "1" is retrieved, the MOS transistors 126 and 127 are both conductive, and the match detection line 24 is discharged. When the value "1" is stored and the value "0" is retrieved, the MOS transistor 1
Match detection line 24 is discharged because both 16 and 117 are conducting. In other cases, the coincidence detection line is not discharged. In particular, the fact that the value “X” is stored means that the MOS transistors 116 and 11 are stored.
Since 7 is non-conducting, the match detect line is not discharged no matter what is searched for, and a “match” is determined (for this memory cell). Next, the self-test circuit 5 will be described in detail. FIG. 4 is a flow chart showing the self-test method. When the memory device is powered on, the power-on detection circuit 15 activates the CPU 10 (50). The CPU executes the following self-test according to the program stored in the ROM 11. First, the coincidence detector 4 is initialized (51). The initial setting is a state in which no defect relief is performed (a state in which the basic memory chip is selected regardless of the address). Next, a preliminary test is performed (52 to 54). This is because if there is a defect at the same address in (m + 1) or more memory chips as described above, the defect cannot be repaired.
This is to detect it early. As the preliminary test, for example, all chips (including the preliminary chips) may be simultaneously tested with the same test pattern to check whether or not (m + 1) or more of the outputs from the respective chips are erroneous. Next, defect repair is performed for each chip (55 to 63). That is, the chip is tested (56) until there are no defective bits (57), the defective replacement method (memory cell unit, word line unit, or data line unit) is determined (58) and it is used as a coincidence detector. Write (59). At this time, if there are too many defective locations and the storage capacity of the coincidence detector is exceeded, it is a defective product. (60, (61). When defect repair is completed for all basic chips (62), final test is performed (6
4) Check that there are no bad bits (65 to 67). The CPU may perform the generation of the test pattern by software, but the provision of the dedicated test pattern generation circuit 12 can reduce the test time. In addition, the CPU may need working memory to perform the above tests. In particular, when determining a defective replacement method based on the test result of one chip (58), it is more efficient to have a memory for recording good / defective of each memory cell, that is, a so-called fail bit memory. . A dedicated memory may be provided as the fail bit memory, but its storage capacity is required to be the same as that of the memory to be tested (that is, one chip), which increases the amount of hardware of the self-test circuit. . In the present embodiment, the following method is used without providing a dedicated fail bit memory. When performing a test for each chip, a chip other than the chip to be tested for the time being is used as a fail bit memory. However, it should be noted that the fail bit memory itself should not be defective. For that purpose, at least one chip of a perfectly good product may be used, but error correction as in the present embodiment is advantageous in terms of cost because a completely non-defective product is unnecessary. A majority vote is adopted here as the error correction. That is, the selector
Use 13 to select chips that are not tested for the time being (2m + 1)
When selecting and writing the same, all the same data is written to (2m + 1), and when reading, the result obtained by taking the (2m + 1) majority by the majority circuit 14 is set as read data. It has been confirmed in the preliminary test that there are at most m defects at the same address, so (2m + 1)
If you take the majority vote, you will always get the correct data. The error correction by majority decision has the advantage that the correction procedure is much simpler than the error correction that is commonly used for Hamming codes and the like. A complicated circuit using a large number of exclusive OR gates used for correcting the Hamming code is not necessary, and only a small majority circuit is required. The drawback of error correction by majority is that redundancy is large ((2m + 1) -bit memory is required to store 1-bit information), but in this case, all chips other than the memory chip under test can be used for the time being. Therefore, it does not matter. As described above, by providing the self-test circuit, the defect relief is automatically performed when the power is turned on.
It is not necessary to repair defects by using an expensive memory tester, and the test cost can be reduced. The amount of hardware required for the self-test is relatively small as shown in FIG. CP
U10 only needs to be able to execute the small-scale program shown in FIG. 4. Therefore, for example, a low-priced one-chip microcomputer integrated with ROM11 is sufficient, and test pattern generation circuit 12 and majority circuit 14 are also small circuits. Can be achieved with. In this embodiment, the self-test is activated by the power-on detection circuit 15, but it may be performed at any time by inputting an activation signal from the outside. Also, the information stored in the coincidence detector 4 may be backed up by a battery. It is of course possible to back up the entire memory device, that is, the memory chip 1 with a battery. In the embodiment shown in FIG. 1, the defect relief is a system of switching the memory chip as a unit, but the chip need not necessarily be a unit. For example, when one memory chip is divided into a plurality of memory blocks, one memory block may be switched as a unit. As an example of this, FIG. 5 shows a configuration using a memory chip having a plurality of (here, four) input / output terminals. Each memory
70 is divided into four memory blocks 71, and each block is connected to input / output terminals I / O _{o to} I / O ₃ . By considering each memory block 71 as the memory chip 1 in FIG. 1, a similar memory device can be made. Although the above embodiment is an example in which a RAM (random access memory) is used as a memory chip, the present invention is also applicable to a memory that serially inputs and outputs data. This example is shown in FIG. Each memory chip 80 is controlled by a chip selection signal CS and a clock CLK. By applying CLK k times (k is an integer) after CS is applied, reading or writing is sequentially performed on k memory cells specified by the address A. To make a memory device similar to that shown in FIG. 1 using this chip, the address and CLK are commonly connected, and CS is controlled by the decoder 2. The operation of this memory device is the same as that of the embodiment shown in FIG. 1 except that data is input and output k times (once in FIG. 1). [Effects of the Invention] As described above, according to the present invention, in a semiconductor memory device that uses a large number of memory chips, defects can be repaired on a large scale across chips. Even chips that cannot be repaired can be used, and the manufacturing cost can be reduced. Moreover, since the repair can be automatically performed, the test cost can be reduced as compared with the method using the memory tester or the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block diagram of a coincidence detector in FIG. 1, and FIG. 3 is a block diagram of FIG. FIG. 4 is a flow chart showing a self-test method for the semiconductor memory device of FIG.
5 and 6 are block diagrams of a semiconductor memory device according to another embodiment of the present invention. 1, 70, 80 ... Semiconductor memory chip, 2 ... Decoder, 3 ... Control circuit, 4 ... Match detector, 5 ... Self-test circuit, 10 ... CP
U, 11 ... ROM, 12 ... Test pattern generation circuit, 13 ... Selector, 14 ... Majority decision circuit, 15 ... Power-on detection circuit, 20 ... Associative memory, 21 ... Priority determination circuit, 22 ... Register, 71 ...
Memory block.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Yoshinobu Nakagome               1-280 Higashi Koigabo, Kokubunji-shi               Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shinichi Ikenaga               1-280 Higashi Koigabo, Kokubunji-shi               Central Research Laboratory, Hitachi, Ltd. (72) Inventor Toshiaki Masuhara               1-280 Higashi Koigabo, Kokubunji-shi               Central Research Laboratory, Hitachi, Ltd.                (56) References JP-A-58-171795 (JP, A)                 JP-A-61-253565 (JP, A)                 JP-A-53-78739 (JP, A)

Claims (1)

(57) [Claims] a first step of preparing n first memories and m second memories, and testing whether the n first memories are defective,
A second step of storing good / bad of the memory cells of the n first memories, and replacing the bad of the first memory with the second memory according to the result of the test of the second step. And a fourth step of storing the replacement method, wherein the second step is currently testing during testing each of the n first memories. A method of relieving defects in a semiconductor memory, wherein a first memory different from the first memory is used as a means for storing good / defective of a memory cell of the first memory currently under test. 2. The second step inspects whether or not the n first memories and (m + 1) or more memories of the second memories have the same address defect, and the result of the inspection is ( m
2. The defect repairing method for a semiconductor memory device according to claim 1, wherein if there are +1) or more defectives at the same address, the n first memories are determined to be defective. . 3. The quality of the memory cell of the first memory currently under test
3. The defect remedying method for a semiconductor memory device according to claim 1 or 2, wherein the data from said storage means for storing a defect is corrected by an error correction means. 4. 4. The defect repairing method for a semiconductor memory device according to claim 3, wherein the error correction means is a majority circuit.