JP2682139B2 - Method for manufacturing lead frame for semiconductor integrated circuit - Google Patents

Description

The present invention relates to an improvement in a method for manufacturing a lead frame for a semiconductor integrated circuit. In particular, the present invention relates to an improvement in a manufacturing method capable of reducing the inner lead pitch of a lead frame.

[Conventional technology]

The lead frame for a semiconductor integrated circuit is a metal plate-like body (1) in which a plate-like body such as a nickel alloy is formed as shown in the plan view of FIG. FIG. 6 shows the semiconductor integrated circuit chip (10) mounted on the semiconductor integrated circuit chip (11) and wire bonding connection between each bonding pad (13) of the semiconductor integrated circuit chip (10) and each corresponding inner lead (12). As described above, the lead frame 12 for semiconductor integrated circuit is completed by covering and packaging it with the covering material (15) made of, for example, a plastic material, and thereafter cutting the ends of the leads (12). If desired, as shown in the drawing, the lead (12)
Bending the tip of is free.

As a method of manufacturing a lead frame for a semiconductor integrated circuit according to a conventional technique, there are a manufacturing method using a wet etching method and a manufacturing method using a press punching method. An example of a method of manufacturing a lead frame for a semiconductor integrated circuit using a wet etching method will be described below.
The following description will be made with reference to FIGS. 10 to 10 (each of which is a cross-sectional view of the region (14) shown by a chain line in FIG. 5).

See FIG. 7. On the surface of the metal plate (0) made of nickel alloy,
For example, a resist made of ammonium dichromate containing 10% by weight of casein is applied to form a resist film (2), and a photomask (3) (the hatched region in the drawing is a non-translucent region). Is contacted with this and exposed. The exposure light (4) exposes the resist film (2) only in the areas not hatched in the figure.

See FIG. 8. In the case of this resist, a weak alkaline developing solution is brought into contact with the resist film (2) to remove the photoresist film (2) except the exposed region, and an etching mask (having an opening (22) ( 21) is manufactured.

See FIG. 9. As a result of carrying out the above steps, from the upper and lower surfaces of the above metal plate (0), the etching mask (21) having the opening (22) is formed on the upper and lower surfaces thereof. The metal plate-shaped body (0) in the region corresponding to the opening (22) is removed by etching from the upper and lower surfaces of the metal plate-shaped body (1) by spraying the etching liquid (5).

After the etching process is completed, the used resist film (21) is dissolved and removed by using a solvent to complete the semiconductor integrated circuit lead frame. As mentioned above, the figure shows a cross section of a region having two leads (12) forming a lead frame (a cross section of the region (14) indicated by a chain line in FIG. 5). At
l is the width of the flat regions of the upper and lower surfaces of the inner leads (21), and p is the pitch of the inner leads. When the wet etching method is used, it is unavoidable that the projection 121 is formed at the center of the lead (12) in the thickness direction.

Also, in the method for manufacturing a lead frame for a semiconductor integrated circuit, which is performed by using the press punching method, a metal plate-shaped body is punched using male / female molds that match the pattern of the leads (12). Pull out to manufacture the lead frame. When the press punching method is used, it is unavoidable that there is a difference in the width l·l ′ of the flat area of the inner lead between the upper surface 6 and the lower surface 7 of the lead frame. In the figure, p is the inner lead pitch.

[Problems to be solved by the invention]

As described above, the following drawbacks are unavoidable in the method for manufacturing the lead frame for a semiconductor integrated circuit according to the conventional technique.

Due to wire bonding in a semiconductor integrated circuit, at present, the width of a flat region on the upper and lower surfaces of the inner lead tip (l in FIG. 10 and l·l ′ in FIG. 11) is 100 μm minimum.
m is required.

However, the thickness of the metal plate that constitutes the lead frame is about
In the case of 150 μm, when the wet etching method is used, it is difficult to set the inner lead pitch to 220 μm or less because of the protrusion 121 inevitably formed in the central portion of the thickness of the inner lead as described above. .

In addition, the thickness of the metal plate that constitutes the lead frame is approximately 15
In the case of 0 μm, when the press punching method is used, it is difficult to set the inner lead pitch to a minimum of 250 μm or less because the width of the inner leads is different between the upper surface and the lower surface of the lead frame.

Recently, especially in the versatile semiconductor integrated circuits (ASICs) and the like, the number of pins has increased, and for this reason, it is required to set the inner lead pitch to 180 μm or less. It is difficult with the current technology to set the width of the flat regions on the upper and lower surfaces to 100 μm or more and to set the inner lead pitch to 180 μm or less.

An object of the present invention is to solve this drawback, and for a semiconductor integrated circuit that makes it possible to set the width of the flat regions of the upper and lower surfaces of the lead tip portion to 100 μm or more and the lead pitch to 180 μm or less. It is to provide a method for manufacturing a lead frame.

[Means for solving the problem]

The purpose of the above is to form the metal plate-like body (0) into the shape of the lead frame for a semiconductor integrated circuit by using the etching method, and then leave the etching mask (21) using the above etching method. In addition, a step of performing an electroplating method on the metal plate-like body (1) formed by the above-mentioned step and depositing a metal layer (9) on the side surface of each lead (12) formed in the above-mentioned etching step This is achieved by the method of manufacturing a lead frame for a semiconductor integrated circuit having the same.

[Action]

In the method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention, in the step of molding the lead frame for a semiconductor integrated circuit using a wet etching method using an etching mask (21), this etching step is performed. If the width of the flat regions of the upper and lower surfaces of the leads etc. (12) is made smaller than the width of the etching mask (21) by performing some excess (over-etching), the thickness direction of the leads etc. It is known that the central part is etched to form a recess. Next, the etching mask (21) formed on the upper and lower surfaces of the leads (12) remains, and the etching of the leads (12) of the metal plate-like body (0) formed by the above etching process remains. By electroplating the side surface, a metal layer (9) is formed on this area (the side surface of the lead (12)).
Are being deposited. At this time, the used etching mask (21) functions as a plating prevention film. As a result, as is clear by comparing FIGS. 1a and 1b, the width of the leads (12) is made substantially uniform in the thickness direction (vertical direction), and the tip of the leads (12) is It is possible to reduce the pitch of the leads (12) to a sufficiently small value while ensuring a sufficiently large width for the flat regions on the upper and lower surfaces.

〔Example〕

Hereinafter, a method for manufacturing a lead frame for a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings.

See Fig. 2. On the surface of a metal plate (0) made of a copper material such as MF202 manufactured by Mitsubishi Electric Corporation and having a thickness of about 150 μm,
For example, a negative casein-based resist such as R-16 manufactured by Fuji Yakuhin Co., Ltd. is applied to a thickness of 5 to 10 μm to form a resist film (2).

Next, a photomask (3) (the hatched area in the figure is a non-translucent area) is brought into contact with the upper and lower surfaces of the resist film (2) and exposed. Ultraviolet light (4) generated by an ultra-high pressure mercury lamp or the like is used for exposure, and the resist film (2) is exposed in a region not hatched in the figure. The exposure energy at this time is 50 mJ / cm ²
The degree is appropriate.

See FIG. 3. The selectively exposed resist film (2) is washed with water at room temperature and developed to remove the resist film (2) except the exposed region, and an etching mask ( 21) is manufactured. In this state, the width of the opening (22) of the etching mask (21) is about 40 μm, and the pitch of the leads (12) is 180 μm or less.

See FIG. 4. Spraying an etching solution (5) such as ferric chloride onto the upper and lower surfaces of the metal plate (0) (see FIG. 3) on which the etching mask (21) is formed. Then, the metal plate-like body (0) in the region corresponding to the opening (22) of the etching mask (21) is gradually etched from both upper and lower surfaces thereof to form leads (12). The etching conditions for this step are to use an etching solution consisting of an aqueous ferric chloride solution having a specific gravity of 665 g /, maintain the temperature of the metal plate (0) at 60 ° C, and inject the etching solution at a pressure of 2 kg / It is to be cm ² .

Refer to FIG. 1a The steps described with reference to the figures after this figure are the steps related to the gist of the present invention. Subsequent to the process described with reference to FIG. 4, the above etching process is continued, and is performed excessively beyond the degree of etching in the prior art. As a result, the width (horizontal width) of the flat regions of the upper and lower surfaces of the inner leads (12) becomes smaller than the width of the etching mask (21), for example, about 50 μm, and the metal plate-like body (1 ) Width of the middle part of the lead (12) remaining between the upper and lower surfaces (width in the horizontal direction, length indicated by W in the figure)
Is about 40 μm. It should be noted that the determination of the end point of etching does not require special rigor. This is because the adjustment can be performed at a later stage of the electroplating process.

See FIG. 1b. The metal plate-like body (1) formed by the above process is used as a cathode, and the electrodes respectively provided on the upper and lower surfaces of the metal plate-like body (1) are opposed as an anode (8), for example, copper. Etc. is electroplated to deposit a metal deposition layer (9) on the side surface of the lead (12). The conditions of the electroplating at this time are as follows, for example. First, the electrolytic solution is Cu
SO ₄・ 5H ₂ O 60g /, H ₂ SO ₄ 200g /, brightener Kapparaside ^HL (trade name of Nippon Schering Co., Ltd.) 20g /, and sodium chloride 100mg /
The current density is 0.5 A / dm ² . The electroplating is carried out until the width of the flat regions on the upper and lower surfaces of the inner leads (12) becomes, for example, about 100 μm. When this step is completed, the semiconductor integrated circuit lead frame (1) is substantially completed.

See Fig. 1c. At room temperature, the resist film (21) is dissolved and removed using a 10% aqueous solution of caustic soda, and inner leads, etc. (12) are removed.
The width (length indicated by WW in the figure) of the flat areas of the upper and lower surfaces of the metal deposition layer (9) and the metal deposition layer (9) on its side surface is about 100 μm.
Thus, it is possible to manufacture the lead frame (1) for a semiconductor integrated circuit in which the pitch of the inner leads is 180 μm or less.

The material of the metal plate may be 42 alloy (Ni 42% by weight / remaining Fe), Kovar, nickel, or stainless other than copper. In addition to copper, nickel, iron-nickel alloy, or the like can be used as the material of the metal layer (9) deposited by electroplating.

〔The invention's effect〕

As explained above, in the method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention, (1) an etching mask corresponding to the shape of the lead frame for a semiconductor integrated circuit is formed on the upper and lower surfaces of the metal plate. At this time, an etching mask having a width corresponding to the width of the flat regions on the upper and lower surfaces of the leads and the like forming the lead frame for the semiconductor integrated circuit is formed at intervals corresponding to the pitch of the leads and the like. Excessive etching is performed in a direction perpendicular to the thickness direction of the metal plate using the above, and using the above etching mask as a plating layer deposition preventing material, the side surface of the above-mentioned overetched leads, etc. , Depositing a metal layer in a direction perpendicular to the thickness direction of the metal plate to backfill the over-etched region, d, and then Since the mask used as an etching mask and then used as a plating layer deposition preventing material mask is also removed by solvent, the width of the flat regions on the upper and lower surfaces of e. The width is almost the same as or close to the width of the etching mask of, and as a result, it becomes almost the same and a sufficiently wide flat area can be secured. Since the surface is almost flat, the margin with respect to the pitch of the leads can be reduced, and it is difficult to use the prior art to make a metal plate with a thickness of about 150 μm as a material. The width of the flat regions on the top and bottom surfaces can be reduced to about 100 μm, and the lead pitch can be reduced to 220 μm or less. As a result, the semi-multi-pin semiconductor integrated circuits with 300 or more pins can be used. It is possible to provide a method of manufacturing a lead frame for the body integrated circuit.

[Brief description of the drawings]

FIG. 1a is an explanatory view of an etching step which is a first main step of one embodiment of the method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention. FIG. 1b is an explanatory view of an electroplating step which is a second main step of one embodiment of the method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention. FIG. 1c is a cross-sectional view of a region corresponding to two leads of a lead frame for a semiconductor integrated circuit manufactured by carrying out an embodiment of a method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention. FIG. 2 is an explanatory diagram of an exposure process according to an embodiment of a method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention. FIG. 3 is an explanatory diagram of a developing step according to an embodiment of a method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention. FIG. 4 is a diagram showing an intermediate step of an etching process according to an embodiment of a method for manufacturing a lead frame for a semiconductor integrated circuit according to the present invention. FIG. 5 is a plan view of a lead frame for a semiconductor integrated circuit according to a conventional technique. FIG. 6 is a perspective view of a semiconductor integrated circuit package according to a conventional technique. FIG. 7 is an exposure process diagram of a method for manufacturing a lead frame for a semiconductor integrated circuit according to a conventional technique. FIG. 8 is a development process diagram of a method for manufacturing a lead frame for a semiconductor integrated circuit according to a conventional technique. FIG. 9 is an etching step diagram of a method for manufacturing a lead frame for a semiconductor integrated circuit according to a conventional technique. FIG. 10 is a cross-sectional view of a region corresponding to two leads of a lead frame for a semiconductor integrated circuit manufactured by performing a method for manufacturing a lead frame for a semiconductor integrated circuit using an etching method according to the related art. is there. FIG. 11 shows leads 2 of a lead frame for a semiconductor integrated circuit manufactured by carrying out a method for manufacturing a lead frame for a semiconductor integrated circuit, which is performed by using a press punching method according to the prior art.
It is a cross-sectional view of the area | region corresponding to a book. 0 ... Metal plate, 1 ... Molded metal plate (lead frame for semiconductor integrated circuit), 11 ... Semiconductor integrated circuit chip support, 12 ... Lead, 121 ... Lead thickness Formed in the central portion of the direction, 13 ... Bonding pad of semiconductor integrated circuit, 14 ... Region corresponding to two leads of semiconductor integrated circuit lead frame, 15 ... Coating material made of plastic material, 2 ... ... resist film, 21 ... etching mask, 22 ... etching mask opening, 3 ... photomask, 4 ... exposure light, 5 ... etching liquid jet, 6 ... lead frame top surface, 7 ... Lower surface of lead frame, 8 ... Anode, 9 ... Metal layer deposited on side surfaces of leads, etc., 10 ... Semiconductor integrated circuit chip.

Claims (1)

(57) [Claims] 1. A metal integrated body (0) is formed into a semiconductor integrated circuit by an etching method using an etching mask (21) formed on the upper and lower surfaces of the metal plate (0). After forming into the shape of the lead frame for use in the etching, the etching mask (21) used in the etching method remains, and the formed metal plate-like body (1) is electroplated to perform the etching. A method of manufacturing a lead frame for a semiconductor integrated circuit, comprising the step of depositing a metal layer (9) on the etched surface etched in the step.