JP2682009B2

JP2682009B2 - Selection circuit

Info

Publication number: JP2682009B2
Application number: JP63126580A
Authority: JP
Inventors: 進一平野
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1988-05-23
Filing date: 1988-05-23
Publication date: 1997-11-26
Anticipated expiration: 2012-11-26
Also published as: JPH01295527A

Description

【発明の詳細な説明】〔産業上の利用分野〕本発明は選択回路に関する。The present invention relates to a selection circuit.

[Conventional technology]

従来、この種の選択回路は、２種類の論理ゲートの出
力信号を選択信号でマルチプレクスしていた。第３図
は、従来の選択回路の一例を示す接続図で、入力信号
Ｂ′,C′のNAND論理信号とNOR論理信号を選択信号Ａ′
でマルチプレクスした場合を示す。Conventionally, this type of selection circuit multiplexes the output signals of two types of logic gates with a selection signal. FIG. 3 is a connection diagram showing an example of a conventional selection circuit. The NAND logic signal and NOR logic signal of the input signals B'and C'are selected signal A '.
Shows the case of multiplexing.

第４表は第３図に示す選択回路の真理値表である。 Table 4 is a truth table of the selection circuit shown in FIG.

〔発明が解決しようとする課題〕上述した従来の選択回路は、２種類の論理ゲートの出
力信号を選択信号でマルチプレクスしているので、スピ
ードが低速になるという欠点がある。 [Problems to be Solved by the Invention] The above-described conventional selection circuit has a drawback that the speed becomes low because the output signals of the two types of logic gates are multiplexed by the selection signal.

[Means for solving the problem]

本発明の選択回路は、ソース電極に電源が供給され２
つ以上の異なるゲート入力をもつ第１の縦積みｐ−MOS
トランジスタ群と、ソース電極に電源が供給され前記第
１の縦積みｐ−MOSトランジスタ群と同じゲート入力を
もつ第２の横積みｐ−MOSトランジスタ群と、前記第２
の横積みｐ−MOSトランジスタ群の出力がソース電極に
供給され前記第２の横積みｐ−MOSトランジスタ群と異
なるゲート入力をもつ第３のｐ−MOSトランジスタと、
前記第１の縦積みｐ−MOSトランジスタ群と前記第３の
ｐ−MOSトランジスタが共通の出力をもち、且つ、ソー
ス電極に接地が供給れ前記第１の縦積みｐ−MOSトラン
ジスタ群と同じゲート入力をもつ第４の縦積みｎ−MOS
トランジスタ群と、ソース電極に接地が供給され前記第
４の縦積みｎ−MOSトランジスタ群と同じゲート入力を
もつ第５の横積みｎ−MOSトランジスタ群と、前記第５
の横積みｎ−MOSトランジスタ群の出力がソース電極に
供給され前記第３のｐ−MOSトランジスタと同じゲート
入力をもつ第６のｎ−MOSトランジスタと、前記第４の
縦積みｎ−MOSトランジスタ群と前記第６のｎ−MOSトラ
ンジスタが共通の出力をもち、且つ、前記第１の縦積み
ｐ−MOSトランジスタ群と前記第３のｐ−MOSトランジス
タの出力が前記第４の縦積みｎ−MOSトランジスタ群と
前記第６のｎ−MOSトランジスタの出力と共通な回路と
を含んで構成される。In the selection circuit of the present invention, power is supplied to the source electrode.
First vertically stacked p-MOS with one or more different gate inputs
A group of transistors, a second group of horizontally stacked p-MOS transistors having the same gate input as that of the first vertically stacked p-MOS transistor group, the source electrode being supplied with power, and the second group of
A third p-MOS transistor having a gate input different from that of the second horizontally stacked p-MOS transistor group, the output of the horizontally stacked p-MOS transistor group being supplied to the source electrode.
The first vertically stacked p-MOS transistor group and the third p-MOS transistor have a common output, and the source electrode is supplied with ground, which has the same gate as the first vertically stacked p-MOS transistor group. Fourth vertically stacked n-MOS with input
A transistor group; a fifth laterally stacked n-MOS transistor group having the same gate input as the fourth vertically stacked n-MOS transistor group, the source electrode of which is supplied with ground;
Output of the laterally stacked n-MOS transistor group is supplied to the source electrode and has the same gate input as the third p-MOS transistor, and the fourth vertically stacked n-MOS transistor group. And the sixth n-MOS transistor have a common output, and the outputs of the first vertically stacked p-MOS transistor group and the third p-MOS transistor are the fourth vertically stacked n-MOS. It is configured to include a transistor group and a circuit common to the output of the sixth n-MOS transistor.

〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第１図は、本発明を選択信号Ａで、出力ＯがB,CのNAN
D論理かNOR論理かを選択する回路に実施した場合の第１
の実施例を示す接続回路図であり、第１表は第１図の真
理値表である。FIG. 1 shows that the present invention uses a selection signal A and outputs O are B and C NANs.
The first when implemented in a circuit that selects D logic or NOR logic
2 is a connection circuit diagram showing the embodiment of FIG. 1, and Table 1 is a truth table of FIG.

Ａ＝０の時、ｐ−MOSトランジスタ３は‘ON'、ｎ−MO
Sトランジスタ６は‘OFF'となり、入力信号Ｂ＝０ある
いは入力信号Ｃ＝０ならば、ｐ−MOSトランジスタ１と
3,2と３あるいは４と５を通して、出力Ｏは‘1'とな
り、Ｂ＝Ｃ＝１ならばｎ−MOSトランジスタ10と９を通
して、出力Ｏは‘0'となり、出力Ｏは、NAND論理にな
る。When A = 0, the p-MOS transistor 3 is'ON ', n-MO
The S-transistor 6 is'OFF ', and if the input signal B = 0 or the input signal C = 0, then the p-MOS transistor 1
The output O becomes "1" through 3, 2 and 3 or 4 and 5, and when B = C = 1, the output O becomes "0" through the n-MOS transistors 10 and 9, and the output O becomes NAND logic. Become.

次に、入力信号Ａ＝１の時、ｐ−MOSトランジスタ３
は‘OFF'、ｎ−MOSトランジスタ６は‘ON'となり、Ｂ＝
Ｃ＝０ならばｐ−MOSトランジスタ４と５を通して、出
力信号Ｏは‘1'となり、Ｂ＝１あるいはＣ＝１ならば、
ｎ−MOSトランジスタ７と6,8と６あるいは10と９を通し
て、出力信号Ｏは‘0'となり、出力信号Ｏは、NOR論理
になる。 Next, when the input signal A = 1, the p-MOS transistor 3
Is'OFF ', the n-MOS transistor 6 is'ON', and B =
If C = 0, the output signal O becomes "1" through the p-MOS transistors 4 and 5, and if B = 1 or C = 1,
The output signal O becomes "0" through the n-MOS transistors 7 and 6, 8 and 6 or 10 and 9 and the output signal O becomes NOR logic.

従って、入力信号Ａ＝０の時、出力信号B,CのNAND論
理が選択され、入力信号Ａ＝１の時、入力信号B,CのNOR
論理が選択される。Therefore, when the input signal A = 0, the NAND logic of the output signals B and C is selected, and when the input signal A = 1, the NOR of the input signals B and C is selected.
Logic is selected.

第２図は、本発明を選択信号Ａで、出力Ｏ₂が入力信
号B,CとＤのAND-NOR論理がOR-NAND論理かを選択する回
路に実施した場合の第２の実施例を示す接続回路図であ
り、第２表は第２図の真理値表である。Figure 2 is a the present invention selection signal A, the output O ₂ is the input signal B, and a second embodiment in which AND-NOR logic of C and D were carried out in the circuit for selecting whether OR-NAND logic It is a connection circuit diagram shown, and Table 2 is a truth table of FIG.

また、第３表は、第３図の入力信号Ｄに、第１図の出
力信号Ｏを入力した場合の真理値表である。Further, Table 3 is a truth table when the output signal O of FIG. 1 is input to the input signal D of FIG.

入力信号Ａ＝０の時、ｐ−MOSトランジスタ19は、‘O
N',n−MOSトランジスタ23は‘OFF'となり、入力信号Ｄ
＝０ならばｐ−MOSトランジスタ18と19を通して、さら
に入力信号Ｂ＝０あるいは入力信号Ｃ＝０ならば、ｐ−
MOSトランジスタ20と22,21と22を通して、また、Ｂ＝Ｃ
＝０ならばｐ−MOSトランジスタ16と17と19を通して、
出力信号Ｏ₂は‘1'となり、入力信号Ｄ＝１の時、入力
信号Ｂ＝１あるいは入力信号Ｃ＝１ならばｎ−MOSトラ
ンジスタ29と27あるいは28と27を通して、出力信号Ｏ₂
は‘0'となり、出力信号Ｏ₂は、OR-NAND論理になる。When the input signal A = 0, the p-MOS transistor 19 is ‘O’
The N ', n-MOS transistor 23 becomes'OFF' and the input signal D
= 0, through p-MOS transistors 18 and 19, and if input signal B = 0 or input signal C = 0, p-
Through MOS transistors 20 and 22, 21 and 22, B = C
= 0, through p-MOS transistors 16 and 17 and 19,
The output signal O ₂ becomes '1', and when the input signal D = 1, if the input signal B = 1 or the input signal C = 1, the output signal O _{2 is} output through the n-MOS transistors 29 and 27 or 28 and 27.
Next is "0", the output signal O ₂ will OR-NAND logic.

次に入力信号Ａ＝１の時、ｐ−MOSトランジスタ11は
‘OFF'、ｎ−MOSトランジスタ23は‘ON'となり、入力信
号Ｄ＝１ならばｎ−MOSトランジスタ24と23を通して、
さらに入力信号Ｂ＝１あるいは入力信号Ｃ＝１ならば、
ｎ−MOSトランジスタ28と27、29と27を通して、また、
Ｂ＝Ｃ＝１ならばｎ−MOSトランジスタ26と25と23を通
して、出力信号Ｏ₂は‘O'となり、入力信号Ｄ＝０の
時、入力信号Ｂ＝０あるいは入力信号Ｃ＝０ならばｐ−
MOSトランジスタ20と22あるいは21と22を通して、出力
信号Ｏ₂は‘1'となり、出力信号Ｏ₂は、AND-NOR論理に
なる。Next, when the input signal A = 1, the p-MOS transistor 11 becomes “OFF” and the n-MOS transistor 23 becomes “ON”. If the input signal D = 1, the n-MOS transistors 24 and 23
Further, if the input signal B = 1 or the input signal C = 1,
Through the n-MOS transistors 28 and 27, 29 and 27,
If B = C = 1, the output signal O ₂ becomes “O” through the n-MOS transistors 26, 25 and 23, and when the input signal D = 0, the input signal B = 0 or the input signal C = 0 is p. −
Through MOS transistors 20 and 22 or 21 and 22, the output signal O ₂ is '1' and the output signal O ₂ will AND-NOR logic.

従って入力信号Ａ＝０の時、入力信号B,CとＤのOR-NA
ND論理が選択され、入力信号Ａ＝１の時、入力信号B,C
とＤのAND-NOR論理が選択される。Therefore, when input signal A = 0, OR-NA of input signals B, C and D
When ND logic is selected and input signal A = 1, input signals B and C
AND-NOR logic of and D is selected.

〔発明の効果〕以上説明した本発明は、動作を高速にし、且つ、素子
数を削減できる効果がある。 [Effects of the Invention] The present invention described above has the effects of speeding up the operation and reducing the number of elements.

また、第１図の選択回路は、up-downカウンタ回路の
キャリー部に使用すると効果がある。すなわち、選択信
号Ａが０のときは、upカウンタとして、Ａが１のときは
downカウンタとして動作する。The selection circuit of FIG. 1 is effective when used in the carry section of the up-down counter circuit. That is, when the selection signal A is 0, the up counter is used, and when A is 1,
Operates as a down counter.

さらに、第２図の回路の入力Ｄに第１図の出力Ｏを入
力すると、第３表からも明らかなように、入力信号Ａの
値によって、その出力信号Ｏ₂がEOR論理（Ａ＝１）ある
いはENOR論理（Ａ＝０）になることがわかる。従って、
第１図の回路と第２図の回路を利用することにより、高
速なup-downカウンタ回路を構成できる効果がある。Further, when the output O of FIG. 1 is input to the input D of the circuit of FIG. 2, as is apparent from Table 3, the value of the input signal A causes the output signal O _{2 to} have EOR logic (A = 1. ) Or ENOR logic (A = 0). Therefore,
By using the circuit of FIG. 1 and the circuit of FIG. 2, there is an effect that a high-speed up-down counter circuit can be constructed.

[Brief description of the drawings]

第１図は本発明の第１の実施例を示す接続回路図、第２
図は本発明の第２の実施例を示す接続回路図、第３図は
従来の一例を示す接続回路図である。１〜５……ｐ−MOSトランジスタ、６〜10……ｎ−MOSト
ランジスタ、11……NAND回路、12……NOR回路、13……
インバータ、14,15……抱き合わせトランスファー、Ａ
〜Ｃ……入力信号、Ｏ……出力信号。FIG. 1 is a connection circuit diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 is a connection circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a connection circuit diagram showing a conventional example. 1-5 ... p-MOS transistor, 6-10 ... n-MOS transistor, 11 ... NAND circuit, 12 ... NOR circuit, 13 ...
Inverter, 14,15 ... tying transfer, A
~ C: input signal, O: output signal.

Claims

(57) [Claims]

1. A first vertically stacked p-MOS transistor group having a source electrode supplied with power and having two or more different gate inputs, and a first vertically stacked p-MOS transistor supplied with power to a source electrode. A second laterally stacked p-MOS transistor group having the same gate input as the group, and the second laterally stacked p-MOS transistor group.
A third p-MOS transistor having a gate input different from that of the second laterally stacked p-MOS transistor group, the output of which is supplied to the source electrode of the MOS transistor group; and the first vertically stacked p-MOS transistor group. A fourth vertically stacked n-MOS transistor in which the third p-MOS transistor has a common output, and the source electrode is supplied with ground and has the same gate input as the first vertically stacked p-MOS transistor group. Group, a fifth laterally stacked n-MOS transistor group having the same gate input as the fourth vertically stacked n-MOS transistor group, in which ground is supplied to the source electrode, and the fifth laterally stacked n-MOS transistor group.
A sixth n-MOS transistor having the same gate input as the third p-MOS transistor, the output of which is supplied to the source electrode of the MOS transistor group; and the fourth vertically stacked n-M transistor.
The OS transistor group and the sixth n-MOS transistor have a common output, and the outputs of the first vertically stacked p-MOS transistor group and the third p-MOS transistor are the fourth vertically stacked. n-MOS transistor group and the sixth
Selection circuit which is common with the output of the n-MOS transistor of FIG.