JP2681305B2 - Information display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an information display in which self-luminous display elements such as light bulbs or light emitting diodes are used as display dots, and the display dots are arranged in a matrix in the vertical and horizontal directions to be displayed in a dotted manner. It relates to the device.

[Prior Art] Conventionally, there are traffic information boards, advertising boards, and the like as information display devices in which display dots are arranged vertically and horizontally in a matrix shape and the display dots are displayed in a dotted manner. As a display dot of a display device, a self-luminous display element such as a small light bulb or a neon tube is used because it is easy to see bright. More recently, light emitting diodes have come to be used as display elements because of their features such as multicolor display of red and yellow green and long life.

[Problems to be Solved by the Invention] These self-luminous display elements used outdoors need to be brightly lit, but when a small light bulb is brightly lit, the average life is as short as about 5000 hours, There was a problem with replacement and maintenance of the traffic information boards displayed by, for example. Similarly, the neon tube also has a problem that it has a life depending on the lighting time. Further, in the light emitting diode, there is no disconnection life due to the nature of the semiconductor, but there is a characteristic that the luminous intensity decreases as it is turned on for a long time as shown in the graph of the decrease in luminous intensity per operating time in FIG. Since the luminous intensity of the light emitting diode is almost proportional to the current flowing through the light emitting diode, when a large amount of current is passed to brightly light the outdoors, characteristic A is shown in FIG.
The decrease in luminous intensity is large at 20 mA shown in (4) and 50 mA shown in characteristic B. Further, in the light emitting diode, as can be seen by comparing the characteristic B and the characteristic C shown in FIG. 7, the higher the ambient temperature, the greater the decrease in luminous intensity with respect to the lighting time. There is a problem that self-heating occurs, and when the lamp is lit for a long time, the self-heating raises the ambient temperature and greatly reduces the luminous intensity. In addition, recently, as shown in the display example of the graphic information board in FIG. 8, the road route is dot-displayed by the display dot D, and the point where the traffic congestion occurs is indicated by the area “A” in FIG. As shown, the display dots are finely hatched, and as shown, red or yellow-green is simultaneously lit to produce an orange color for color display to indicate congestion. In such a case, the display dot indicating the route shape does not go out and stays lit, so the luminous intensity is often lower than that of other display dots. This was a problem because a difference in luminous intensity from the dots occurred. Further, in the case where the display dots are made to emit light in a large area at the same time as shown by finely hatching the display dots as shown by the area “A” in FIG.
The self-heating of the light emitting diode will heat other display dots, and the ambient temperature of the light emitting diode will rise further,
There is a problem that the decrease in luminous intensity becomes large, and further, the luminous intensity of the light emitting diode becomes dark when the ambient temperature is high as shown by the ambient temperature vs. luminous intensity characteristic. The allowable current of the diode becomes lower as the ambient temperature becomes higher, as shown in the absolute maximum forward current reduction characteristics in Fig. 10.
There is a problem that a desired luminous intensity cannot be obtained.

[Means for Solving the Problems] In order to solve such problems, the information display device according to the present invention outputs display specification data for specifying lighting or non-lighting for each display dot (D). Display control means (MEM1, SR1-SR8) that controls the display dots to turn on or off based on the designated display data, and a display that outputs the display state data by detecting whether the display dots are on or off. The state detection means (SR9-SR16, MEM2), the data comparison means for comparing the display designation data of the display control means and the display state data of the display state detection means, and the position on the matrix where the display dots light up are shifted, Display change control means (TM, C1, C2) that changes the specified display data at specified time intervals
And a means for temporarily changing all display dots to the non-illuminated state when this display change control means changes the display designation data (M
M) and are provided.

[Operation] In the present invention, lighting of the same display dot does not continue, all display dots are turned on evenly, and in the case of a display element such as a light bulb having a disconnection life, the maintenance and replacement interval is long. And the light intensity decreases like a light emitting diode,
In the display element in which the temperature rise is a problem, the decrease in luminous intensity is reduced, the temperature rise is also reduced, and all the display dots are extinguished when the display is changed or redisplayed, so that the abnormal feeling of appearance is eliminated.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a plan view showing the display surface of the information display device according to the present invention. In the figure, D1 to D64 denote light emitting diodes, and the finely hatched portions indicate that the light emitting diodes are emitting light, and the display is switched in the order of (a) to (d) of FIG. The process is returned to FIG.

FIG. 3 shows a light emitting diode which emitted light in FIGS. 2 (a) to (d). In FIG. 2 (a) to (d), 17 light emitting diodes out of 64 light emitting diodes are Each of them is emitting light, and when viewed in FIG. 3, 40 out of 64 are emitting light, and the display surface emits light on average by switching from FIG. 2 (a) to (d). It indicates that In FIG. 2, when the figures (a) and (b) are displayed for the same time, the light emitting diode D13 at the tip end of the arrow display shows that the figures (a) and (c) are displayed. It emits light, and the lighting rate during the display period is 50%, which is half the time of continuous light emission. Further, looking at the light emitting diode D4, light is emitted during the display of FIG. 7C, and the lighting rate during the display period is 25%. There is no light emitting diode that continuously emits light during the period of (a) to (d) in the figure, which prevents a specific light emitting diode from always emitting light, and the display switching time is appropriately selected. This shows that the temperature rise due to self-heating of the light emitting diode can be prevented to some extent, and the decrease in luminous intensity due to the operating time of the light emitting diode can be relatively reduced. Further, when the display is changed as shown in FIG. 2 (a) → FIG. (B) → FIG. (C) → FIG. (D), all display surfaces should be turned off as shown in FIG. 2 (e). You can also make the arrow display look invisible as if it moved. In addition, in FIG. 2, the display content is an arrow,
The same applies to characters and does not limit the display content.

FIG. 1 is a block circuit diagram showing a configuration according to an embodiment of an information display device according to the present invention, and is a circuit diagram for specifically realizing the switching of the display shown in FIG. In the figure, MEM1 is a light-emitting diode D1 to D6 forming the display surface.
This is a storage circuit that stores display designation data that designates which of 4 is to emit light, and is usually composed of RAM or ROM.

FIG. 4 (a) shows the contents of the display designation data stored in the memory circuit MEM1. "1" and "0" in the display designation data shown in the figure are the data arrays in the memory circuit MEM1 displayed corresponding to the rows 1 to 8 and the columns 1 to 8, and are shown in FIG. When a pulse is received from the terminal CP1 as described above, the terminal OUT is at 8th row to 8th row to 8th row and 1st column, and then at 7th row.
It outputs as serial data from row 8 column to row 7 column 1 in order from row 1 column 8 to row 1 column 1. The terminal OUT is connected to the serial input terminal SI of the parallel out shift register SR1 with serial in latch. There is. The shift register SR1 is commercially available under the model name of TC74HC595. The shift register SR1 has a clock input terminal C
Every time the pulse of P is input, the data of the serial input terminal SI is right-shifted and the serial data is output to the serial output terminal SO. The output terminal SO is connected to the input terminal SI of the shift register SR2 of the next stage, and the shift register SR2 shifts the data of the input terminal SI to the right every time the pulse of the clock input terminal CP is input. Below, the shift register SR8 is connected. When the shift register SR1 receives a latch signal (not shown), the shift register SR1 latches the serial data and outputs the serial data to the parallel output terminals Q1 to Q8. The parallel output terminals Q1 to Q8
The anodes of the light emitting diodes D1 to D8 forming the display surface shown in FIG. 2 are connected, and the cathodes of the light emitting diodes D1 to D8 pass through the current detection circuit CS, respectively, and the zero volt line L
It is connected to the. When serial data is input to the shift register SR1 and the state "1" is output to the parallel output terminals Q1 to Q8, a current flows through the connected light emitting diode, and the light emitting diode emits light. In the current detection circuit CS, specifically, as shown in FIG. 5, the cathode of the light emitting diode is connected to the terminal DI, and the current flowing in the light emitting diode passes from the base B of the transistor TR through the emitter E to become the base current. Flow from the terminal G to the zero volt line L. When the base current flows through the transistor TR, the transistor TR is turned on and the collector C is brought into the state “0”. Since the collector C is connected to the inverter INV2, the state [1] is output from the output of the inverter INV2 to the terminal DO. The terminal DO is the parallel input terminal PI1 of the shift registers SR9 to SR18 in FIG.
~ Connected to PI8 respectively. This shift register S
R9 to SR18 are for parallel input and serial output, and are generally commercially available under the model name of TC74HC59.When the latch signal (not shown) is input to the data input to the parallel input terminals PI1 to PI8, they are latched. Then, each time a clock pulse is input to the clock input terminal CP2, it is shifted left one bit by one bit and output to the serial output terminal SO2. The output terminal SO2 is input to the input terminal IN of the memory circuit MEM2, and the memory circuit MEM2 receives the data of the input terminal IN from 8 rows 8 columns to 8 rows 1 column and then 7 rows 8 by the input of the pulse from the terminal CP3. Serial data is stored from the column to the 7th row and the 1st column in the order of the 1st row and the 1st column. FIG. 4 (b) shows the data. The serial input terminal SI2 of the shift register SR9 is connected to the serial output terminal SO2 of the shift register SR10 at the preceding stage. This allows the light emitting diode D
A so-called monitoring circuit that detects the current flowing in 1 to D64 by the current detection circuit CS, the shift registers SR9 to SR16 transfer the detected data as serial data to the memory circuit MEM2, and stores the state of the light emitting diode in the memory circuit MEM2. Will be configured. Normally, a CPU (not shown) or the like compares the data match between the memory circuit MEM1 and the memory circuit MEM2 to detect an abnormality such as a light emitting diode disconnection. Although a transistor is used to detect the current of the light emitting diode in FIG. 5, a photocoupler or the like may be used. Further, in FIG. 1, C2 is a counter, which counts up by receiving a pulse from its terminal CP4. When it counts 55, it counts to terminal O1, 56 counts to terminal O2, 63 counts to terminal O3, and 64 counts. Then, the signal is output to the terminal O4. The terminals O1 to O4 are connected to one input of the AND circuits AND1 to AND4, the other input of the AND circuit AND1 is the terminal O7 of the counter C1, and the other input of the AND circuit AND2 is the terminal O8 of the counter C1. The terminal O6 of the counter C1 is connected to the other input of the AND circuit AND3, and the terminal O5 of the counter C1 is connected to the other input of the AND circuit AND4.
The counter C2 includes the shift registers SR1 to S from the memory circuit MEM1.
It controls the transfer of data to the memory circuit MEM2 from the shift registers SR9 to SR16 to R8.When a signal is input to the reset terminal R1, it is reset and the outputs of the terminals O1 to O4 are lost and the count number is reset. , The state becomes “0”. The output of the AND circuit AND5 is connected to the terminal CP4 of the counter C2, the clock pulse generator OSC is connected to one input of the AND circuit AND5, and the output of the inverter INV1 is connected to the other. The input of the inverter INV1 is an OR circuit
The output of OR1 is connected, and the inputs of the OR circuit OR1 are connected to the outputs of AND circuits AND1 to AND4. Counter C1 is
It receives a pulse from the terminal CP5 and performs cycle counting, and outputs signals in the order of terminal O5, terminal O6, terminal O7, terminal O8, and terminal O5. The output of the OR circuit OR2 is connected to the terminal CP5 of the counter C1, the output of which passes through the OR circuit OR3 and the counter C5.
2 is connected to the reset terminal R1. The output terminal O9 of the timer TM is connected to one of the inputs of the OR circuit OR2.
When the signal is input to the reset terminal R2, the timer TM
It resets TM to the initial value. When the set time elapses, a signal is output to pin O9 and the timer TM is timed again. The other input of the OR circuit OR2 is connected to the signal from the terminal T, and the signal is connected to the reset terminal R2 of the timer TM. A signal is input to the terminal T when the display is changed, and normally, the signal is input to the terminal T after the data to be displayed is stored in the memory circuit MEM1. AND circuit
The output of AND5 is connected to the common of switch SW
The contact S1 of SW is connected to the terminal CP of the shift registers SR1 to SR8 and the terminal CP1 of the memory circuit MEM1, and the contact S2 is connected to the terminal CP2 of the shift registers SR9 to SR16 and the terminal CP3 of the memory circuit MEM2. The switch SW performs display and monitoring. When contact S1 is selected, the display switching operation is performed, and contact S2
When is selected, the monitoring operation starts. A signal is input to the terminal T, the timer TM and the counter C2 are reset, and the counter C1
If a signal is output from terminal O5 of
Since no signal is output to the terminals O1 to O4 of C2, the output of the OR circuit OR1 is in the state "0" and the output of the inverter INV1 is "1". The output pulse of the clock pulse generator OSC passes through the AND circuit AND5, the contact S1 selected from the common of the switches SW, the memory circuit MEM1 and the shift register SR.
1 to SR8 are operated to sequentially send the data in the memory circuit MEM1 to the shift registers SR1 to SR8 from 8 rows and 8 columns. Since the output of the clock pulse generator OSC is also input to the counter C2, the signal "1" is output to the terminal O4 when the counter C2 counts 64 inputs of the terminal CP4. The signal passes from the AND circuit AND4 and the OR circuit OR1, and the inverter INV
The output of 1 is set to "0". Since the output of the clock pulse generator OSC is no longer output from the AND circuit AND5, the memory circuit MEM1 outputs 64 number of data. Therefore, the data of the shift registers SR1 to SR8 is shown in FIG. 6 (c), FIG. (G), FIG. (K) ... In the state of FIG. (O), the output is output to the terminals Q1 to Q8 of the shift registers SR1 to SR8, and current flows through the light emitting diodes D1 to D64 to emit light. Second
The display shown in FIG. At this time, the shift registers SR8 to SR16 are in the states shown in FIGS. 6 (o), (a), (e) ... (m). Explaining the case of the next monitoring, when the contact S2 of the switch SW is selected and the signal of the monitoring command is input to the terminal W in the state "1", the signal passes through the OR circuit OR3 and resets the counter C2. The output pulse of the clock pulse generator OSC is
Pass through the contact S2 of the switch SW and shift registers SR9 to SR16
And the memory circuit MEM2 are operated, and the counter C2 transfers data up to 64. Therefore, the data in the shift registers SR9 to SR16 are shown in FIGS. 6 (a), 6 (e), 6 (i), ... The diagram (m) is transferred to the memory circuit MEM2 and has the same arrangement and the same data as the memory circuit MEM1. Next, when the timer TM times out and a signal is output to the terminal O9, that signal is output to the OR circuit.
The counter C1 is advanced by 1 through the OR2, the signal is output to the terminal O6, and the counter C2 is reset through the OR circuit OR3. The output of the clock pulse generator OSC passes through the AND circuit AND5, the contact S1 of the switch SW, and the shift register S
The R1 to SR8 and the memory circuit MEM1 are operated. Counter C2
When the number of counts reaches 63, the signal "1" is output from the terminal O3, so the output of the clock pulse generator OSC is stopped by the AND circuit AND5. At this time, since the data transfer from the memory circuit MEM1 to the shift registers SR1 to SR8 is up to 63, the states of the shift registers SR1 to SR8 are shown in FIG. 6 (d), FIG. 6 (h), FIG. As shown in the figure (p), the data is shifted to the left by one dot as compared with the figures (c) to (o), and the driven light emitting diodes D1 to D64
The light-emission state is as shown in FIG. 2 (b), which means that the arrow is shifted to the left by one dot as compared with FIG. 2 (a). Next, for monitoring, when the contact S2 of the switch SW is selected and the monitoring command signal "1" is input to the terminal W, until the data of the shift registers SR1 to SR16 is output to the terminal O3 of the counter C2. , Ie clock pulse generator OS
The C output is transferred to the memory circuit MEM2 until 63 outputs. The data state of the shift registers SR9 to SR16 is 6th.
Since these are the states shown in the figures (b), (f), (j), ... (N), the memory circuit shifts to the left.
When transferred to MEM2, the same data is obtained in the same array as the memory circuit MEM2. Next, when the timer TM times out, the display state similarly becomes the state shown in FIG. 2 (c) from the above description, and when the timer TM times out next, it becomes the state shown in FIG. 2 (d). Then, when the timer TM times out, the state shown in FIG. Even if the display changes in this way, the data array and state of the memory circuit MEM1 and the memory circuit MEM2 match, so if the circuit is operating normally, there will be no mismatch even if both data are compared and compared. Does not occur. However, if the shift register does not transfer or the light emitting diodes D1 to D64 are disconnected due to some abnormality, the mismatch of the portions can be detected and the maintenance and replacement can be performed. In addition, in FIG.
When the MM is connected to the output of the OR circuit OR2 and receives the signal, it outputs the signal to the inverter INV3 in the state "1" for a certain period of time. The output of the inverter INV3 is the shift register SR1 to SR8.
Of the shift register SR
1 to SR8 do not output a signal to the terminals Q1 to Q8 when the output control terminal OE is "0". Therefore, the terminals Q1 to Q8 of the shift registers SR1 to SR8 are output while the signal is output from the mono-multi MM.
Do not output a signal from the light emitting diode D1 ~
I try not to let D8 fire. That is, the display surface is turned off for a certain period of time when the display is switched and the display position is switched when the display time exceeds a certain period.

With such a configuration, the shift register is used as a means for transferring the display command data from the storage circuit to the light emitting diode drive circuit, and the display position can be easily changed by controlling the number of data transfers. Further, when the monitoring data indicating the light emitting state of the light emitting diode is transferred to the storage circuit by using the shift register, the transfer number in the display and the monitoring transfer number are the same by shifting the transfer in the opposite direction to the display. By so doing, the arrangement of the display command data and the arrangement of the monitoring data can be made the same, and there is an advantage that the coincidence comparison between the display command data and the monitoring data becomes easy.

In the above-described embodiment, the data transfer is described using the shift register, but the address may be used and the parallel data may be transferred. Further, the switch between the display and the monitoring has been described by using the switch SW, but it goes without saying that it can be configured by a semiconductor logic circuit. Further, although the switching of the display position has been described in the case of four positions, it goes without saying that the number is not limited. Further, although the display position is switched by hardware using a count and a shift register, it is needless to say that the display can be switched by software using a CPU.

[Effects of the Invention] As described above, according to the present invention, the display position on the display surface is switched at the time of changing the display and at regular time intervals. Therefore, when the display symbol is fixed, a specific display dot is displayed. Since continuous lighting is eliminated, deterioration of the luminous intensity due to temperature rise is significantly reduced, the life of the display element is lengthened, and an extremely excellent effect that an information display device with high quality and reliability can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing the configuration of an embodiment of the information display device according to the present invention, FIGS. 2 and 3 are plan views showing the display surface of the information display device according to the present invention, and FIG. FIG. 5 is a diagram showing a memory state of a memory circuit, FIG. 5 is a circuit diagram showing a configuration of a current detection circuit, FIG. 6 is a diagram showing a memory state of a shift register, and FIG. 7 is a graph showing a decrease in luminous intensity per operating time of a light emitting diode. Fig. 8 is a plan view showing a display example of a graphic display plate, Fig. 9 is a diagram showing ambient temperature vs. luminous intensity characteristics of a light emitting diode, and Fig. 10 is an absolute maximum forward current reduction characteristic of a light emitting diode. It is a figure. D1 to D64 …… Light emitting diodes, MEM1, MEM2 …… Memory circuits,
SR1 to SR18 …… Shift register, PI1 to PI18 …… Parallel input terminal, Q1 to Q8 …… Parallel output terminal, CS …… Current detection circuit, INV1 to INV3 …… Inverter, AND1 to AND5 …… And circuit, C1, C2 ... Counter, OSC ... Clock pulse generator, OR1 to OR3 ... OR circuit, SW ... Switch, TM ...
… Timer, MM …… Monomulti.

Claims (1)

(57) [Claims] 1. An information display device in which display dots composed of self-luminous display elements are arranged vertically and horizontally in a matrix, and the display dots are made to emit light to be displayed by dot-spacing. A display control unit that outputs display designation data designating non-lighting and controls the display dot to light or non-light based on the display designation data, and detects a state in which the display dot is lit or non-lighted. A display state detecting means for outputting the display state data, a data comparing means for comparing the display designation data of the display control means and the display state data of the display state detecting means, and a position on the matrix where the display dot lights up. Display change control means for changing the display designation data at predetermined time intervals so as to shift, and the display change control means changes the display designation data. Information display device comprising temporarily providing the means for the more dots in the non-lighting state to.