JP2680831B2 - Sense circuit - Google Patents

Description

The present invention relates to a sense circuit of a memory device using MOS transistors.

Prior Art FIG. 3 shows this type of sense circuit. In FIG. 3, reference numeral 1 is a memory cell composed of MOS transistors, each connected to a read line 2, and the read line 2 is connected to first and second MOS transistors 3 and 4, respectively. The system clock is applied to the gate,
Both MOS transistors 3 and 4 are turned on / off reciprocally by this system clock. An inverter 5 is connected to the read line 2, and the data of the memory cell 1 is read from the output terminal of the inverter 5. The output of the inverter 5 is the third MOS transistor connected in series with the second MOS transistor 4.
Connected to transistor 6.

In the above configuration, when the memory cell 1 is off, the node A becomes "H" due to the precharge of the first MOS transistor 3. Then, the output of the inverter 5 becomes "L", the third MOS transistor 6 is turned off, and the node A becomes "H".

Problems to be Solved by the Invention In the conventional sense circuit as described above, the first MO
After the end of the precharge period of the S-transistor 3, when the input (node A) is "H", low noise is introduced, and if the output inverts the node (B) to "H" due to the noise, there is a drawback that it cannot be restored.

It is an object of the present invention to provide a sense circuit that can surely perform a sensing operation even if noise enters the node A.

Means for Solving the Problems The sense circuit of the present invention includes an inverter for inputting a signal of a read line connected to a memory cell, and a read line when the first MOS transistor connected to the read line is turned on. A first MOS transistor for precharging a first logic level to a first logic level and a second and a third MOS transistor connected in series with each other, one end of which is connected to the read line
And a series circuit for supplying the read line with a second logic level which is the inverted level of the first logic level when both the third MOS transistor and the third MOS transistor are turned on, A signal path for reciprocally turning on / off the first and second MOS transistors by applying to the gate of the second MOS transistor and applying the output of the inverter to the gate of the third MOS transistor is provided. As a result, in the sense circuit configured to turn on the third MOS transistor when the read line becomes the second logic level, the sense circuit is configured to obtain a signal indicating the content of the memory from the output of the inverter. Insert a low-pass filter consisting of a capacitor and a resistor in the signal path for applying to the gate of the third MOS transistor. It is characterized by doing.

Embodiments In the following embodiments of the present invention, the same parts as those in the circuit of FIG.

As shown in FIG. 1, a capacitor 10 is connected in parallel to the gate of the third MOS transistor 6, and a transmission gate 11 equivalent to a resistor is connected between the output of the inverter 5 and the gate of the third MOS transistor 6. It is connected between. In addition, between the read line 2 and the power supply
The source and the drain of the MOS transistor 12 are connected, and the gate thereof is connected to the common connection point of the capacitor 10 and the resistor 11.

A low-pass filter that absorbs noise is configured by the capacitor 10 and the resistor 11.

In operation, when the memory cell 1 is off, the node becomes "H" due to the precharge of the first MOS transistor 3. When the spiked noise shown in FIG. 2B enters this node, the node which is the output of the inverter 5 becomes “H” momentarily as shown in FIG. 2B, but it is composed of the transmission gate 11 and the capacitor 10. The noise is cut by the filter. Therefore the third
The gate or node of the MOS transistor 6 is stably brought to "L" as shown in FIG. 2C without being affected by noise. As a result, the third MOS transistor 6 never turns on, and the node never goes "L". Further, since the MOS transistor 12 is always on without being affected by noise, the node is stabilized at "H" also by this MOS transistor 12.

As described above in detail, according to the present invention, even if noise is introduced into the sense circuit, the read line can be stabilized at H without being fixed at L, and the data in the memory cell can be reliably read. You can

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the sense circuit of the present invention, FIG. 2 is a waveform diagram of a main part of the circuit of FIG. 1, FIG. 3 is a circuit diagram showing a conventional sense circuit, and FIG. FIG. 4 is a waveform diagram showing a state when noise is introduced into the circuit of FIG. 1 ... Memory cell, 2 ... Read line, 3,4,6 ... MOS transistor, 5 ... Inverter, 10 ... Capacitor, 11 ... Resistor, 12
... MOS transistors.

Claims (1)

(57) [Claims] 1. An inverter for inputting a signal of a read line connected to a memory cell, and a first MOS transistor connected to the read line, which brings the read line to a first logic level when turned on. A first MOS transistor for precharging and a second MOS transistor connected in series with each other.
And a third MOS transistor, one end of which is connected to the read line and the second and third MO transistors are connected.
A series circuit for supplying the read line with a second logic level which is an inverted level of the first logic level when both S-transistors are on, and supplies a system clock to the first and second MOS transistors. By applying to the gate of the transistor, the first and second MOS transistors are turned on and off reciprocally, and the output of the inverter is turned on to the third MO.
By providing a signal path for applying to the gate of the S-transistor, the third MOS transistor is turned on when the read line becomes the second logic level, and a signal indicating the contents of the memory is output from the output of the inverter. In the sense circuit thus obtained, a low-pass filter including a capacitor and a resistor is inserted in the signal path for applying the output of the inverter to the gate of the third MOS transistor.