JP2679314B2 - Music synthesizer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical sound synthesizer in which an algorithm approximating a sounding mechanism of a musical instrument is realized by using a digital electronic circuit.

2. Description of the Related Art In recent years, due to advances in digital technology, many musical tone synthesizers have been developed that apply digital electronic circuits such as electronic pianos and synthesizers. Among them, there is proposed a musical sound synthesizer which analyzes the sounding mechanism of a musical instrument and replaces it with a digital electronic circuit (for example, Japanese Patent Laid-Open No. 63-40199, "Signal Processor"). The signal processor described in the above patent publication can be applied to a signal synthesizer such as an electronic musical instrument or a signal processing circuit for sound field control. In this publication, a rubbed string instrument such as a violin constitutes a musical sound synthesizer with a plurality of delays, an adder and a driving unit, and the bow rubs the strings by relatively controlling the lengths of the plurality of delays. When the contact position (the ratio between the position of the nut supporting the string and the contact position and the position of the bridge also supporting the string and the distance between the contact positions) is changed. Similar tone changes can be realized. This can be applied to a stringed instrument such as a piano or a plucked instrument such as a guitar.

The above-described musical tone synthesizer will be described below with reference to the drawings.

FIG. 10 is a schematic diagram showing the sounding mechanism of a stringed instrument.

In FIG. 10, the strings are supported by bridges (point A) and nuts (point B). The driving input is input to the point B by a playing operation such as striking a string or tapping, and the driving input propagates in the direction indicated by the broken line arrow. At points A and C, the propagated waveform is reflected and returns to the direction of point B again. By repeating this operation, the string vibrates. The influence on the waveform at points A and C is due to the "reflection" caused by the fixed end.
There are two possible causes: “high frequency cutoff” due to vibration leakage.

FIG. 11 is a block diagram of a conventional musical sound synthesizer. The block diagram shown in FIG. 11 approximates the sounding mechanism of the stringed instrument shown in FIG. 10 by various calculations, a table, and a memory.

In FIG. 11, reference numeral 91 starts the reading of drive data stored therein according to a sounding instruction signal (hereinafter referred to as kon) such as a key depression of a keyboard, and sequentially adds the read drive data to the adders 92, 93. It is a table part to be sent to. Adder 92
Is for adding the drive data sent from the table section 91 and the data read from the memory 99, and the adder 93 is for adding the drive data sent from the table section 91 and the memory.
It is to add with the data read from 96.
The addition result of the adder 92 is temporarily stored in the memory 94, and the data read from the memory 94 is processed by the data processing unit 95. Also memory
The numeral 96 is adapted to temporarily store the data sent from the data processing unit 95, and the memory 97 is adapted to temporarily store the addition result of the adder 93. The data sent from the memory 97 is processed by the data processing unit 98, and the data sent from the data processing unit 98 is temporarily stored in the memory 99. The addresses of the memories 97 and 99 are designated by the address generator 201, and the addresses of the memories 94 and 96 are designated by the address generator 202. Word length indicator 2
03 sends the memory word length data m for determining the word lengths of the memories 94 and 96 to the address generation unit 202, and the memory 9
Memory word length data n for determining the word length of 7,99 is sent to the address generator 201. The first
When the musical sound synthesizer of FIG. 1 is associated with the schematic diagram of the sounding mechanism of the stringed instrument of FIG. 10, the drive data sent from the table 91 corresponds to the drive input given to the point B, and the memories 94, 96 and The storage time of the temporary storage by the memories 97 and 99 corresponds to the propagation time of the waveform between BC and AB of the string, respectively. Further, the processing in the data processing unit 95 and the data processing unit 98 corresponds to the influence of the reflection of the nut at the point C and the bridge at the point A and the high-frequency cutoff (low-pass), respectively, and the address generation units 201 and 202 and the word length instruction unit 203 The process of changes the length between AC, which is the total length of the string. That is, it corresponds to an operation of changing the pitch or an operation of changing the position of the drive input point (point B).

 FIG. 12 shows a circuit diagram of the table portion 91.

In FIG. 12, reference numeral 101 is a table for storing drive data in advance. Counter 102 is system clock SCK
The table address is incremented for each table 10
The table address is sent to 1. The comparator 103 compares the table address sent from the counter 102 with the table word length data M corresponding to the total number of word lengths of the table 101, and when a comparison match is found, a comparison match flag is input to the S flip-flop 104 at the S input. Send to. Then, the RS flip-flop 104 releases the reset of the counter 102 when kon is input, and resets the counter 102 when the comparison match flag is input.

 FIG. 13 shows a circuit diagram of the word length instruction unit 203.

In FIG. 13, 110 is a table for converting the position of the depressed key, that is, the pitch data f into the index data e. The multiplier 111 multiplies the driving position parameter k (parameter for determining the position of the driving input point (point B) in FIG. 10) by the exponent data e, and outputs the multiplication result as the memory word length data n. The subtractor 112 subtracts the memory word length data n from the exponent data e and outputs the subtraction result as the memory word length data m. The pitch data f is a linear variable with respect to the unit of cent. The relationship between the index data e and the pitch data f is as shown in equation (1).

e = 2 ^{(fmax−f) / 12} (1) (However, fmax is a value at which the tone frequency becomes fs / 2 when the sampling frequency is fs.) Further, the driving position parameter k is expressed by the formula (2). It is a variable that moves in the range shown in FIG. 10. The driving parameter k becomes smaller as the driving input point (point B) is closer to the point A in FIG. 10, whereas the driving parameter k becomes larger as it is closer to the point C. .

0 <k <1 (2) FIG. 14 is a circuit diagram of the address generators 201 and 202.

In FIG. 14, 121 is a memory 94, 96 or a memory 9
This is a counter that increments and outputs 7,99 addresses for each system clock SCK. Comparator 122 is counter 1
The address sent from 21 is compared with the memory word length data m or n sent from the word length designating section 203, and when a comparison match is found, a comparison match flag is sent to the OR gate 123. The OR gate 123 resets the counter 121 when kon or the comparison match flag is sent.

FIG. 15 shows a circuit diagram of the data processing units 95 and 98.

In FIG. 15, 131 is an inverter that inverts the data sent from the memory 94 or 97.
The data transmitted from the delay unit 132 is delayed by one sampling cycle. The data sent from the delay unit 132 is multiplied by the value 0.5 in the multiplier 133. The data sent from the inverter 131 is multiplied by the value 0.5 in the multiplier 134. The multiplication results of the multipliers 133 and 134 are added by the adder 135.
Is added in. 132,133,134,13
The circuit composed of 5 is generally known as a first-order FIR filter (low-pass filter), and they are collectively referred to as a low-pass filter 136.

The operation of the tone synthesizer configured as described above will be described below.

First, as shown in FIG. 10, it is assumed that a drive input is applied to point B in an actual string instrument model. The given drive input propagates in the directions of points A and C, is reflected at each point (reflected and further cuts off the high frequency range), and returns to point B again. By repeating this operation, vibration of the string occurs. If the drive input point (point B) is moved while being displaced in the A direction or the C direction, a vibration state different from the above-mentioned vibration will occur,
It is clear that the tones of the musical tones generated by the vibration are different.

Next, what realized the above-mentioned actual string sounding mechanism by an electronic circuit is a conventional tone synthesizer shown in FIG. Here, the strings correspond to the memories 94, 96, 97 and 99, the bridge corresponds to the data processing unit 98, the nut corresponds to the data processing unit 95, and the drive input corresponds to the drive data sent from the table unit 91.

In FIG. 11, drive data corresponding to the drive input is first input from the table unit 91 to the adders 92 and 93. More specifically, referring to FIG. 12, kon is input to the R input of the RS flip-flop 104 from the keyboard or the like in order to start sounding. At this time, the reset of the counter 102 is released (it is assumed that the counter 102 was reset before this), and the increment of the table address is started. According to the increment operation of the counter 102, the table 101 sequentially reads the drive data stored in advance. Then, when the table address value matches the table word length data M, the comparator 103 sets the comparison match flag to R.
It is sent to the S flip-flop 104 and the counter 102 is reset. Therefore, the counter 102 remains in the state of holding the table address value at 0 until the next kon is input. Here, the value 0 is set to address 0 of table 101.
By writing, the drive data is read out and then held at the value 0.

Now, returning to FIG. 11, in the adder 92, the drive data sent from the table unit 91 and the data sent from the memory 99 are added, and in the adder 93, the addition is made from the table unit 91. The drive data and the data sent from the memory 96 are added. Then, the addition result is temporarily stored in the memories 94 and 97. The storage time temporarily stored in the memories 94 and 97 corresponds to the time during which the waveform propagates between the strings BC and BA, respectively. Because word length indicator 203
Indicates to the address generators 201 and 202 the memory word length data m (corresponding to the waveform propagation time between the strings BC) and the word length data n (corresponding to the waveform propagation time between the strings BA), respectively. Are memory 97,99 and 94,96 respectively
As a result, the memory 94,95 uses m areas, the memories 97,99 use n areas, and the memories 94,96,97,99 use the areas as ring memories. This is because it will be accessed (detailed later). Therefore, for example, the data written at the time 0 in the memory 94 (data sent from the adder 82) is time (m × Ts) when the sampling cycle is Ts.
After a lapse of time, it is read out and sent to the reflecting section 95. That is, it can be considered that the memory 94 corresponds to a delay of m stages. Similarly, the memory 96 is an m-stage delay, and the memories 97 and 9
9 can be thought of as an n-stage delay. Considering this, the drive data sent from the table unit 91 and input to the adder 92 is processed in the reflecting unit 95 after (m × Ts) time has elapsed, and further processed into the adder 93 after (m × Ts) time has elapsed. To reach. At this time, if the drive data is still being transmitted, addition with the drive data is performed by the adder 93 and the addition result is written in the memory 97. Then, after (n × Ts) time has elapsed, the data is processed in the data processing unit 98 and written in the memory 99, and after (n × Ts) time has elapsed, it is read from the memory 99 and returned to the adder 92 again.
Therefore, each data is processed in the cyclic circuit formed by the adders 92, 93, the memories 94, 96, 98, 99, and the data processing units 95, 98 for (2Ts (m + n)) time. The frequency of the musical sound data is 1 / (2Ts (m + n)).

Next, regarding the processing of the address generation units 201 and 202, the addresses of the memories 94, 96, 97 and 99 are generated here. 14th
The circuit diagram is shown in the figure. In FIG. 14, the counter 121 is reset when kon is input to the OR gate 123, and the address increment is started from the value 0. The address is cyclically incremented from the value 0 to the memory word length data by the comparator 122 and the OR gate 123. Here, in FIG. 11, the address generation unit 201 outputs n as memory word length data from the word length instruction unit 203.
Is received, the address values 0 to (n-1) are cyclically sent to the memories 97 and 99. Similarly, since the address generation unit 202 receives m as the memory word length data from the word length instruction unit 203, the address values from 0 to (m-1) are cyclically sent to the memories 94 and 96.

Next, regarding the processing of the word length designating section 203, the pitch of the desired musical tone data and the position of the driving point (point B) shown in FIG. 10 are determined here. First, the pitch is determined by the table 110 shown in FIG. As described above, the pitch (frequency) of the tone data synthesized by the tone synthesizer shown in FIG. 11 was 1/2 Ts (m + n). That is, m +
When the value of n is determined, the pitch of the musical sound data is determined. By the way, in FIG. 13, the index data e read from the table 110 is nothing but m + n. Therefore, the pitch of the musical sound data is determined by the table 110. Next is the determination of the position of the driving point (point B) shown in FIG.
It is determined by the multiplier 111 and the adder 112 in the figure. It was found from the equation (2) that the driving position parameter k input to the multiplier 111 is a variable that moves in the range of 0 <k <1. When the drive position parameter k takes the minimum value, the memory word length data n takes the minimum value (n _min ), and the memory word length data m becomes (e−n _min ). This corresponds to the case where the drive input point (point B) is closest to the bridge position (point A) in FIG. Similarly, when the driving position parameter k takes the maximum value, the memory word length data n takes the maximum value (n _min ) and the memory word length data m becomes (e−n _max ). This is the drive input point (point B) in Fig. 10 and the nut position (A
It corresponds to the case where it is closest to the point). Further, when the driving position parameter k is 0.5, the memory word length data n becomes e / 2 and the memory word length data m becomes e / 2. This corresponds to the case where the drive input point (point B) is brought to the midpoint of the chord in FIG. By changing the value of the drive position parameter k in this way, the drive input point (point B) shown in FIG.
A tone color change can be realized by changing the position of.

Finally, regarding the processing of the data processing units 95 and 98, this is processing of inversion and high-frequency cutoff (low-pass), as described above. Therefore, a circuit diagram as shown in FIG. 15 can be considered. In FIG. 13, the reversing device 131 literally performs a reversing process. On the other hand, the low-pass filter 136
Is for passing low frequencies. The desired processing described above can be performed by connecting these in a cascade.

SUMMARY OF THE INVENTION However, the above-mentioned configuration requires a large number of circuits, which increases the scale of hardware. Further, there is a problem that the processing speed becomes slow and the quality of the desired musical sound becomes low.

In view of the above problems, it is an object of the present invention to provide a musical tone synthesizer capable of realizing a tone color change by changing the position of a drive input point (point B) shown in FIG. 10 with a simple circuit. Is.

Means for Solving the Problems To achieve this object, a musical tone synthesizer of the present invention provides a table unit for transmitting drive data stored in advance in accordance with a sounding instruction such as a key depression on a keyboard, a data phase inversion and a low pass. Similarly to the first and second data processing units that apply a filter passing action, and the first adder that adds the data sent from the second data processing unit and the drive data sent from the table unit, A second adder for adding data in the first data processing unit and the table unit; first and second storage units for temporarily storing the first and second adders;
A first and a second address unit for designating read and write addresses of the first and second storage units, respectively, and data read from the first and second storage units are respectively stored in the first and second storage units. Input to the second data processing unit, and the sounding instruction is given from the table unit to the first and second adders by pressing a key on the keyboard.
For pitch and timbre, use the word length instructor
The output of the first storage unit is made to be a musical sound by being sent to each of the second address generation units.

Further, the musical sound synthesizer of the present invention comprises a table section for sending drive data stored in advance to an adder in accordance with a sounding instruction such as a key depression on a keyboard, data sent from a low-pass filter section, and driving sent from the table section. An adder that performs addition with data, a storage unit that temporarily stores the addition result by the adder, a low-pass filter unit that processes the data read from the storage unit, and a read / write address of the storage unit are specified. Address generating unit, and sends word length data that determines the word length of the storage unit to the address generating unit based on the pitch data designated by the key depression of the keyboard and the parameters for determining the tone color of the desired musical tone. And a word length instruction section.

Further, the musical tone synthesizer of the present invention sends drive data stored in advance to an adder in accordance with a sounding instruction such as key depression of a keyboard, and further reads out drive data stored in advance based on a parameter for determining a tone color of a desired musical tone. A table unit that controls the aspect, an addition unit that adds the data sent from the low-pass filter unit and the driving data, a storage unit that temporarily stores the addition result by the addition unit, and a data read from the storage unit. A low-pass filter section for processing, an address generation section for specifying the read and write addresses of the storage section, and word length data for determining the word length of the storage section based on the pitch data specified by key depression on the keyboard. It is provided with a word length instruction unit for sending to the address generation unit.

Operation With the above configuration, the drive data sent from the table section is input to the first and second adders, then stored in the first and second storage sections, respectively, and after being delayed by a certain time, the first And is processed in the second data processing unit, and returns to the first and second adders again. By repeating this operation, a desired musical sound can be obtained.
Further, by controlling the number of stages of the first and second storage sections by the first and second address generation sections and the word length designating section, a timbre similar to a timbre change caused by changing a string driving position in a stringed instrument is obtained. Realize change. Since only the two storage units need to be controlled here, the tone color change can be realized with a simple configuration including the address lines.

Further, with the above-described configuration, the drive data sent from the table section is input to the adder, stored in the storage section, processed by the data processing section after being delayed by a certain time, and then returned to the adder again. This operation is divided by 2
By repeating the operation, the same operation as that of the musical tone synthesizing apparatus using the two storage units is performed. By the time division processing, the data processing unit and the adder can be configured by only one, and the circuit scale can be reduced.

Further, according to the above-described configuration, the drive data stored in advance is read out from the table portion twice, that is, the drive data sequence 1 and the drive data sequence 2, and the drive data sequence 2 corresponds to the drive position data for the drive data sequence 1. Read the data after delaying the time. After that, the addition unit adds the data sent from the low-pass filter to the driving data sequence 1 and the driving data sequence 2 and stores the addition result in the storage unit. By repeating this operation, it is possible to realize the same timbre change as the timbre change by changing the driving position of the strings in the stringed instrument.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a musical sound synthesizing apparatus of the present invention.

In FIG. 1, 11 is a first memory which is a so-called storage unit (hereinafter referred to as a memory) for temporarily storing the data sent from the first adder 92. The second memory 12 is for temporarily storing the data sent from the second adder 93, the address of the second memory 12 is designated by the second address generating unit 13, and the first memory 11 Address is first
It is designed to be specified by the address generator 14 of. The word length instruction unit 15 sends the memory word length data 2m for determining the word length of the first memory 11 to the first address generating unit 14 and determines the word length of the second memory 12 as well. The memory word length data 2n is sent to the first address generator 14. Here, the second and first address generators 13,1
4 and the word length designating unit 15 are the address generating units 201 and 202 and the word length designating unit 2 of the conventional tone synthesizer shown in FIG. 11, respectively.
Although it is a circuit equivalent to 03, it differs from the conventional one in that the memory word length data is changed to 2m and 2n in order to match the operating conditions with the conventional tone synthesizer. The operating condition refers to the frequency of the musical sound data, that is, the 11th
The frequency of the tone data synthesized by the tone synthesizer shown in the figure is the sum of the number of memories 94, 96, 97, 98 and the sampling period T
It was the reciprocal of the value obtained by multiplying s, that is, 1 / 2Ts (m + n), but the number of the first memory 11 is 2 m and the number of the second memory 12 is 2 to accommodate the tone synthesizer of this embodiment at this frequency. The number is 2n. The other blocks are the same as those of the conventional tone synthesizer shown in FIG.

FIG. 2 is a block diagram of a musical tone synthesizer having a simpler circuit configuration than the musical tone synthesizer shown in FIG.

Explaining how it is simplified, a series of processes of the first adder 92, the first memory 11, the first data processing unit 95, and the first address generating unit 14 in FIG. The series of processes of the adder 93, the second memory 12, the second data processing unit 98, and the second address generating unit 13 of the second adder 93, the memory 22, the data processing unit 95 shown in FIG. , Address generator
The circuit is simplified by performing time-division processing in 24 circuits.

In FIG. 2, reference numeral 21 is an adder for adding the drive data sent from the table unit 91 and the data sent from the low-pass filter unit 136. The addition result of the adder 21 is temporarily stored in the memory 22.
The address of is designated by the address generator 23. The word length instruction unit 15 is the same as that of the musical tone synthesizer shown in FIG. The other blocks are the same as those of the musical sound synthesizer shown in FIG.

FIG. 3 is a circuit diagram of the address generator 23.

In FIG. 3, reference numeral 31 is an address generation unit for generating an address of the memory 22 based on the memory word length data 2m sent from the word length instruction unit 15. The address generator 32 generates the address of the memory 22 based on the memory word length data 2n sent from the word length instruction unit 15.

The data sent from the address generators 31 and 32 is selected based on the select signal of the selector 33. Here, the address generator 31 is a circuit equivalent to the address generator 201 of the conventional tone synthesizer shown in FIG. 11, and the address generator 32 is the address generator of the conventional tone synthesizer shown in FIG. It is a circuit equivalent to the part 202,
The input memory word length data is changed to 2m and 2n, respectively, in order to match the operating conditions of the above-described conventional tone synthesizer.

 FIG. 4 is a circuit diagram of the memory 22.

In FIG. 4, reference numeral 41 denotes a memory, which is divided into a 2m-stage memory area and a 2n-stage memory area. These two divided areas are selected by the select signal shown in FIG. Further, the select signal is added to the most significant bit of the address, and the 1-bit data selects two areas of the memory 41. Further, among the addresses in FIG. 3, the addresses excluding the select signal bits are commonly connected to the 2m-stage area and the 2n-stage area of the memory 41, and both areas are similarly addressed by the select signal. be able to.

FIG. 5 shows that the number of the memory 11 is increased from 2 m to 2 (m + n) except for the adder 93, the memory 12, the data processing unit 98, and the address generation unit 13 from the tone synthesizer of FIG. 95 is a low-pass filter 136 obtained by removing the inverter 131 in the reflector 95, and the output of the low-pass filter 136 is added to the adder 92.
Further, the table portion 91 is changed to the table portion 51.

In FIG. 5, 51 is a table section for reading out drive data stored in advance based on kon and drive position data K. The drive data read out from this table section 51 and the data sent out from the low-pass filter 136 are The addition section 52 is configured to perform addition. The data sent from the adder 52 is temporarily stored in the memory 53. Here, the drive position data K is a variable that moves in the range shown in the equation (3), unlike the drive position parameter k. However, it is assumed that it is an integer.

0 <K <2 (m + n) (3) The other circuits are the same as those of the conventional tone synthesizer shown in FIG.

 FIG. 6 shows a circuit diagram of the table section 51.

In FIG. 6, reference numeral 61 is a selector for selecting the table address sent from the AND gate 69 and the counter 65. The counter 62 cyclically increments between the value 0 and the value 2 (m + n), and the table address and the table word length data M counted by the counter 62 are counted.
Is compared with the comparator 63. RS
The flip-flop 64 resets the output of the AND gate 69 by the comparison match flag sent from the comparator 63,
The output of the AND gate 69 is released from reset by turning on. The counter 65 cyclically increments from the value 0 to the table word length data M, and the table address counted by the counter 62 and the drive position data K are compared by the comparator 66. The RS flip-flop 67 resets the counter 65 by the comparison match flag sent from the comparator 66, and further the counter 6 by kon.
It is designed to release the reset of 5, and the counter 65
The table address and the table word length data M counted by are compared by the comparator 68. The AND gate 69 masks the data sent from the counter 62 when the RS flip-flop 64 sends the reset flag, sends the value 0 to the selector 61, and the counter 62 when the RS flip-flop 64 does not send the reset flag. The data sent from is sent to the selector 61 through. Here, the counter 65 counts between the value 0 and M, which is the total word length of the table 101, while the counter 62 counts between the values 0 and 2 (m + n). The other circuits are the same as those of the conventional tone synthesizer shown in FIG.

 FIG. 7 shows a circuit diagram of the adder 52.

In FIG. 7, 71 is a selector for selecting the data sent from the low-pass filter 136 and the data sent from the latch 73. The adder 72 adds the drive data sent from the table unit 51 and the data sent from the selector 71, and the addition result of the adder 72 is latched by the latch 73. Then, the data sent from the latch 73 is latched by the latch 74.

FIG. 8 shows a circuit diagram of the table section 51. 6 and 8 both show the circuit diagram of the table unit 51, except that the circuit of FIG. 8 is different from the circuit of FIG. 6 in that the circuit of FIG. The point is that a function for linear interpolation between is added.

In FIG. 8, reference numeral 81 is a linear interpolation unit that performs linear interpolation between a plurality of drive data read from the table 101. The adder 82 outputs the data sent from the counter 65 and the value 0.
Or 1 is added. The other circuits are the same as those of the table section 51 shown in FIG.

FIG. 9 shows a circuit of the linear interpolation section 81. Ninth
In the figure, 83 is a latch for latching the drive data read from the table 101, and an adder 84 is designed to add the data sent from the latch 83 and the data sent from the multiplier 86. There is. The data latched by the latch 83 from the drive data read from the table 101 is subtracted by the subtractor 85, and the data sent from the subtractor 85 and the decimal part Km of the drive position data are multiplied by the multiplier 86. It is like this. Then, the AND gate 87 resets the decimal part Km of the drive position data.

The operation of the tone synthesizer configured as described above will be described below.

First, the operation of the musical sound synthesizer shown in FIG. 1 will be described.

The tone synthesizer shown in FIG. 1 differs from the tone synthesizer shown in FIG. 11 in that the memory 96 inserted between the data processing unit 95 and the adder 93 is connected to the memory 94 and the cascade. By constructing a new first memory 11 and connecting the memory 99 inserted between the data processing unit 98 and the adder 92 to the memory 97 in a similar manner, a new second memory 12 is formed. Configured and the first
The operation is similar to that of the musical sound synthesizer shown in FIG. Since the memory word length data 2m, 2n sent from the word length designating section 15 can be controlled by the driving position parameter k, the driving input point (B shown in FIG.
It is possible to realize a timbre change by changing the position of (dot). The circuit scale is similar to that of the conventional musical tone synthesizer shown in FIG. 11, but the memory 11 and 12 have a simple structure. That is, an effect can be obtained in terms of quality. In FIG. 1, the musical sound output is used as the first storage unit, but if it is in the loop formed by the memory, the adder, and the data processing unit,
Musical sound output is possible anywhere.

Next, the operation of the musical sound synthesizer shown in FIG. 2 will be described.

As described above, the tone synthesizer shown in FIG. 2 is the tone synthesizer shown in FIG. 1 which is time-division processed.

In FIG. 2, the driving data read from the table unit 91 is added to the data sent from the data processing unit 95 and the adder.
Added at 21. The addition result is immediately temporarily stored in the memory 41. Here, the access order of the memory 41 is as follows.

Access sequence R0, m → W0, m → R0, n → W0, n → R1, m → W1, m → R1, n → W1, n → R2, m → W2, m → R2, n → W2, n → R3, m → W3, m → R3, n → W3, n →…
………… → Rn−1, m → Wn−1, m → Rn−1, n → Wn−1, n → Rn, m → Wn, m →
R0, n → W0, n → Rn + 1, m → Wn + 1, m → R1, n → W1, n → …………
… → Rm-1, m → Wm-1, m → Rm-n, n → Wm-n, n → ………… However, R is read, W is written, and the first suffix is the memory address address. , The second suffix represents the area selection, and m is the area of 2m steps in FIG. 4 (area m
, N is a region of 2n stages in FIG. 4 (referred to as region n). That is, R3n represents the reading of the memory at the third address in the 2n-th stage area.

As described above, the memory access to the area m and the area n can be alternately performed because the select signal is switched for each read / write processing of the memory in FIG. By alternately performing the memory access in the area m and the area n in this manner, the processing can be performed in a time-sharing manner, and as a result, processing equivalent to that of the musical tone synthesizer as shown in FIG. 1 can be realized.

Next, the operation of the musical sound synthesizer shown in FIG. 5 will be described.

First, the operation of the table unit 51 will be described with reference to FIG. Kon is input to the R input of the counter 62 by pressing a key on the keyboard. At this time, the counter 62 stops the operation so far, resets the count value, and starts the increment operation from the value 0. The data sent from the counter 62 is
It is input to the AND gate 69, the comparator 63, and the comparator 66. The comparator 66 compares the data sent from the counter 62 with the drive position data K. Then, the comparison match flag is input to the RS flip-flop 67 when the comparison is matched, the reset of the counter 65 is released, and the counter 65 starts the increment operation from the value 0. That is,
Since the counter 65 outputs the value 0 until the increment value of the counter 62 reaches the drive position data K, the value output from the AND gate 69 and the value 0 are alternately selected in the selector 61. Then, when the count value of the counter 62 reaches K, the counter 65 starts the increment operation and sends the count value to the selector 61. The AND gate 69 is reset by the comparator 63, and the counter 65 is reset by the comparator 68 when the count values of the counters 62 and 65 reach the value M, respectively. This reset continues until the next kon is input. Here, assuming that the value 0 is stored in advance at the address 0 of the table 101, the drive data read from the table 101 has the value 0 while the AND gate 69 and the counter 65 are both reset. From the above operation, the drive data stored in the address corresponding to the count value of the counter 62 and the value 0 are alternately read from the table 101 when the kon is input, and the count value of the counter 62 reaches the drive position data K. From the time point, it can be seen that the drive data stored in the address corresponding to the count value of the counter 62 and the drive data stored in the address corresponding to the count value of the counter 65 are alternately read. The order of reading drive data from the table 101 is shown below. Here, D represents drive data and the suffix represents an address.

Read order D0 → D0 → D1 → D0 → D2 → D0 → ... DK → D0 → DK + 1 → D1 →… D
M-1 → DM-K-1 ... D0 → D0 That is, the data string stored in the table 101 is [D0,
D1, D2, D3 ... DM + 1], the drive data string read from the table 101 is the drive data string 1 read by the counter 62 and the drive position data, as shown below. It can be regarded as the sum with the drive data string 2 read by the counter 65 after the delay time corresponding to K.

Drive data string 1: [D0, D1 ... DK, DK + 1, DK + 2 ... DM-1] Drive data string 2: ← delay → [D0, D1, D2 ... DK ... DM-1] Next, the seventh In the figure, the drive data read from the table 101 and the data read from the low pass filter 136 shown in FIG. 5 are added. First, XOR gate 75
The driving data D0 (driving data read by the counter 62) that has passed through and is input to the adder 72 is added to the data transmitted from the low-pass filter 136. At this timing, it is assumed that the inversion signal is not input to the XOR gate 75, and therefore the drive data inversion processing is not performed. In the selector 71, the low pass filter 136
Data from shall be selected. The addition result of the adder 72 is latched by the latch 73 and sent to the selector 71.
Next, the drive data D0 (drive data read by the counter 65) that has passed through the XOR gate 75 and is input to the adder 72 is added to the data transmitted from the latch 73. At this timing, it is assumed that the inversion signal is input to the XOR gate 75, and therefore the drive data inversion process is performed. Further, it is assumed that the selector 71 selects the data from the latch 73. The addition result of the adder 72 passes through the latch 73 and is latched by the latch 74. It can be seen that the following data string is input to the memory 53 by repeating the above operation.

D0 → −D0 → D1 → −D0 → D2 → −D0 →… DK → −D0 → DK + 1 →
−D1 → ... DM-1 → −DM-K-1 ... D0 → −D0 That is, the data string stored in the table 101 is [D0,
D1, D2, D3 ... DM-1], the memory 5
The drive data input to 3 are the drive data read by the counter 62 and input to the memory 53 via the adder 52 (addition processing only), and the delay time corresponding to the drive position data K. It can be regarded as the sum with the drive data which is read by the counter 65 later and is input to the memory 53 via the adder 52 (addition processing after inversion).

Drive data sequence 1: [D0, D1 ... DK, DK + 1, DK + 2 ... DM-1] Drive data sequence 2: ← delay → [-D0, -D1, -D2 ...- DK ...- DM-1] By going back, the musical tone synthesizer shown in FIG. 1 can realize the tone color change by changing the position of the drive input point (point B) shown in FIG. 10 by controlling the drive position parameter k. all right. Therefore, the operation of the musical sound synthesizer shown in FIG. 5 will be explained again while comparing it with the operation of the musical sound synthesizer shown in FIG. 1, so that the musical sound synthesizer shown in FIG. It is clarified that a tone color change can be realized by changing the position of the point (point B).

First, the table section in the musical tone synthesizer shown in FIG.
The circuit for processing the drive data input from 51 becomes a circuit (referred to as circuit 1) in which the memory 53 (2m + 2n stages) and the low-pass filter 136 are cyclically connected, except for the adder 52. On the other hand, in the tone synthesizer shown in FIG. 1, except for the adders 92 and 93, the memories 11 and 12 and the data processing units 95 and 98 are also included.
Becomes Here, the data processing unit 98 is connected to the reflection unit 95 and the memory 12
Then, a change is made to remove both the inverter 131 included in the data processing units 95 and 98, and the changed circuit is referred to as the circuit 2. Then, the circuit becomes substantially equivalent to the circuit 1 and the circuit 2. However, since the circuit 2 includes one extra low-pass filter 136 with respect to the circuit 1, the filter characteristic of the circuit is different. However, for example, by changing the filter characteristic of the circuit 1, the circuit 2 can be changed.
Therefore, the circuit 1 and the circuit 2 are completely equivalent circuits. Now, it is a good idea to make a change to the circuit 2, but since this change does not affect the synthesized tone data, it is appropriate. Therefore, when the musical tone synthesizer shown in FIG. 5 and the musical tone synthesizer shown in FIG. 1 are compared, the difference in the insertion position of the adder is that the drive input point (point B) shown in FIG. 10 is changed. It became clear that there was a functional difference in whether or not the tone could be changed.

Therefore, the operation will be described focusing on the difference between the insertion positions of the adders 92 and 93 of the musical tone synthesizer shown in FIG. 1 and the insertion position of the adding section 52 of the musical tone synthesizer shown in FIG. First,
In the musical tone synthesizing device shown in FIG. 1, the driving data is synthesized from the table portion 91 in order to synthesize musical tone data.
(Circuit type circuit including memories 11 and 12, data processing units 95 and 98, and adders 92 and 93). This drive data sequence is used as drive data sequence 1 [D0, D1 ... DK, DK + 1, DK + 2 ... DM-
1], the drive data sequence 1 [D0, D1 ... DK, DK + 1, DK + 2 ... DM-1] is input to the synthesizing circuit 1 via the adder 92, temporarily stored in the memory 11, and the same addition is performed. Drive data string 1 [D0, D1 ... DK, DK + 1, DK + 2 ... D
M-1] is input and temporarily stored in the memory 12. Here, the drive data string 1 [D0, D1 ... DK, DK + 1, DK + 2 ... DM-1] input to the synthesis circuit 1 via the adder 93 is stored in the memory 12
Is delayed by 2n steps, inverted in the data processing unit 98, cut off in the high frequency range, and temporarily stored in the memory 11. In this operation, the drive data sequence 1 [D0, D1 ... DK, DK + 1, DK + 2 ... DM-1] is first input from the table unit 91 to the adder 92, and then 2n stages of the memory 12 are input. Drive data string 1 [D0, D1 ... DK, DK + 1, DK + 2 ... D
It can be said that the operation is the same as inverting [M-1] and inputting a data string that further cuts off high frequencies. This operation is approximately realized by the table section of the musical tone synthesizer shown in FIG.
51 and an adder 52. That is, from the above description, the driving data sequence 1 [D0, D1 ... DK,
DK + 1, DK + 2 ... DM-1] and the drive data string 2 [-D0, -D1, -D2 ... -D with a delay time corresponding to the drive position data K.
K ...- DM-1] is input to the memory 53.
Here, the drive data string 2 [-D0, -D1, -D2 ...- DK ...- DM
-1] is the drive data string 1 [D0, D1 ... DK, DK + 1, DK + 2 ... DM-
1] is reversed, so that the tone synthesizer shown in FIG. 1 and the tone synthesizer shown in FIG. I understand. However, the drive position parameter K is stored in the memory 12
2n, which is the same as the number. Therefore, the fifth
The musical tone synthesizer shown in the figure also has the drive input point (B
It is possible to realize a timbre change by changing the position of (dot).

Since the drive position data K input to the comparator 66 shown in FIG. 6 is an integer, the drive input point (B
Only timbre changes equivalent to moving (dots) in rough steps can be obtained. The circuit shown in FIG. 8 solves this new problem. This circuit is a circuit of the table unit 51, and by adding a linear interpolation unit 81 and an adder 82 to FIG. 6, a linear interpolation function between a plurality of drive data read from the table 101 is provided. There is. The operation of linear interpolation will be described below. First, the drive position data consists of an integer part Ki and a decimal part Km, and Ki is input to the comparator 66 as in the circuit of FIG. Km is input to the linear interpolation unit 81, where the linear interpolation processing is performed. A drive data string addressed by the counter 65 and read from the table 101 (before the drive data string 2 is inverted) [D0, D1 ... DK, DK +
1, DK + 2 ... DM-1] are drive data strings 1 [D0, D1 ... DK, D which are addressed by the counter 62 and read from the table 101.
It was found from the above description that the drive position data K is delayed with respect to K + 1, DK + 2 ... DM-1] (provided that K is an integer). Here, K is the integer part Ki and the decimal part Km
Since it consists of and, obviously the delay is Ki. Therefore,
The eighth is to try to realize a delay of Km by the linear interpolation unit 81.
This is a feature of the table unit 51 in the figure. In this linear interpolation, the drive data of an arbitrary address N read from the table 101 is set to DN, and an address (N
The drive data of +1) is DN + 1. The addition of the addresses is performed by the adder 82 (FIG. 8). Well, table 10
DN and DN + 1 read from 1 are linear interpolation section 81 (9th
(Fig.) Is sent, and the linear interpolation calculation shown in the fourth equation is executed.

DN ′ = DN + (DN + 1−DN) × Km (4) DN + 1−DN is executed by the subtractor 85, and then by the multiplier 86.
Km is multiplied and DN is added by the adder 84 to obtain the linearly interpolated drive data value DN '. By the way, this linear interpolation calculation is performed only for the drive data string addressed by the counter 65 (before the inversion of the drive data string 2), and for the drive data string 1 addressed by the counter 62. It is necessary to prohibit linear interpolation. For that purpose, Km may be set to a value of 0 in the phase in which the drive data sequence 1 is input to the linear interpolation unit 81. The AND gate 87 performs this processing, and Km is masked to the value 0 by the input of the reset flag.

With the above description of the operation, the drive input point (B
It is possible to realize a timbre change equivalent to moving the point) in fine steps. Although the drive data sequence 2 is linearly interpolated in the present embodiment, the same effect can be obtained by the drive data sequence 1 being linearly interpolated. The same effect can be obtained by interpolation other than linear interpolation.

As described above, according to this embodiment, as shown in FIG. 1, the memories 94 and 96 used in the conventional musical sound synthesizer are combined into the first memory 11, and the memories 97 and 99 are combined into the second memory. 12
It becomes a simple structure by putting together. Also, the second
As shown in the figure, the circuits 11 and 12 are further combined into the memory 22 to access the memory 22 in a time division manner, whereby the circuit scale can be reduced.

In addition, in the tone synthesizer shown in FIG.
The drive data stored in the drive data string 1 [D0, D1 ... D
K, DK + 1, DK + 2 ... DM-1] and drive data string 2 [-D0, -D1,
-D2 ...- DK ...- DM-1] are input to the memory 53, the drive data string 2 is delayed with respect to the drive data string 1, and the delay amount is controlled by the drive position data K. It is possible to realize a tone color change by changing the position of the drive input point (point B) shown in FIG. 10 with a simple circuit configuration.

Further, the linear interpolation section 81 of the table section 51 shown in FIG. 8 can realize a timbre change corresponding to moving the drive input point (point B) shown in FIG. 10 in fine steps.

EFFECTS OF THE INVENTION As described above, according to the present invention, memories scattered in a circuit are integrated into a simple structure, and memory access is performed in a time division manner, or a prestored drive data string is driven with a drive data string 1. By providing a table section for reading the data string 2 in two times and an adding section for inputting the sum of the driving data string 1 and the driving data string 2, the actual string driving position of the stringed instrument of a simple string structure is provided. It is possible to realize a timbre change similar to the timbre change by changing. Furthermore, by linearly interpolating between the samples of the drive data string 2, it is possible to realize a timbre change corresponding to a timbre change by subtly changing the driving position of the strings of the stringed instrument, and the instrument itself is played. Since the subtle tone color change can be surely achieved electrically, the effect is great.

[Brief description of the drawings]

1, 2 and 5 are block diagrams of the musical tone synthesizer of the present invention, FIG. 3 is a circuit diagram of the address generating section 23, FIG. 4 is a circuit diagram of the memory 22 and FIG. 6 is a table section. 51 is a circuit diagram of FIG. 7, FIG. 7 is a circuit diagram of the addition unit 52, FIG. 8 is a circuit diagram of the table unit 51, FIG. 9 is a circuit diagram of the linear interpolation unit 81, and FIG. 10 is a schematic diagram showing a sounding mechanism of a stringed instrument. FIG. 11 is a block diagram of a conventional tone synthesizer, FIG. 12 is a circuit diagram of the table section 91,
FIG. 13 is a circuit diagram of the word length designating unit 203, FIG. 14 is a circuit diagram of the address generating units 201 and 202, and FIG. 15 is a circuit diagram of the data processing units 95 and 98. 21,82,84,135 …… Adder, 64,67,104 …… RS flip-flop, 69,87 …… AND gate, 75 …… XOR gate, 85,112 …… Subtractor, 86,111,133,134 …… Multiplier, 92 …… First Adder, 93 ... second adder, 123 ... OR gate, 131 ... inverter, 132 ... delayer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiko Hatanaka 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Mizuho Seki, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. Within

Claims (3)

(57) [Claims] 1. A data circuit having a table section for transmitting data according to a sounding instruction such as a key depression of a keyboard, a storage section for delaying data and a low-pass filter section connected in a closed loop. A loop unit adapted to take out the data being circulated as desired musical tone data by circulating the data through a data circuit, an address generating unit for designating read and write addresses of the storage unit, and a keyboard of the keyboard. And a word length instruction unit for sending word length data for determining the word length of the storage unit corresponding to the delay time of the data based on the pitch data designated by key depression etc. to the address generation unit, and the table unit. However, a difference value between the drive data and data obtained by delaying the drive data by a time corresponding to a parameter for determining a tone color can be input to the loop unit. A tone synthesizer characterized by. 2. The table unit interpolates at least each data of one drive data series.
A musical sound synthesizer as described. 3. The musical tone synthesizing apparatus according to claim 1, wherein the table section performs linear interpolation.