JP2675302B2 - Phase comparison circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a phase comparison circuit used in a PLL circuit, and particularly in a receiving system using the PLL circuit, when a strong electric field input signal is applied to the PLL circuit. The present invention relates to a phase comparison circuit that reduces the interference given. (B) Conventional technology A PLL circuit divides an accurate oscillation output created by a crystal oscillation circuit, etc. with a reference divider to obtain a reference frequency signal R _E , and also an oscillation output of a voltage controlled oscillation circuit (VCO). Variable frequency signal with a programmable divider
P _E is obtained, the phase difference between these signals R _E and P _E is compared by a phase comparison circuit, and the VCO is controlled with a DC voltage according to the phase difference to obtain a stable VCO oscillation output. In the receiving system, the oscillation output of the VCO is mixed as the local oscillation frequency with the RF input signal to create an intermediate frequency signal (IF). In such a receiving system, it is necessary to improve the C / N ratio (oscillation frequency signal to noise ratio) of the VCO in order to improve the S / N ratio (signal to noise ratio). , It is necessary to reduce the dead zone of the phase comparator. In the conventional phase comparison circuit, as shown in FIG. 3, the reference frequency signal R _E and the variable frequency signal P _E are input to the clock input terminal CK.
D-FF (1) (2) and D-FF (1) applied to the
The output of (2) is composed of a charge pump circuit (3) to which each output is applied, and each output of D-FF (1) (2) is
Both are applied to the other input D, and D-FF (1)
The reset input R of (2) has a reference frequency signal R _E and a variable frequency signal P _E applied to the other clock input CK.
Is applied. The phase difference vs. output voltage V _T characteristic of this phase comparison circuit is
It looks like the figure. Ideally, the straight line indicated by the solid line A is desirable, but the characteristic indicated by the broken line B is obtained due to the delay of the elements forming D-FF (1) and (2). That is, there occurs a region where the output voltage V _T does not change with respect to the change in the phase difference. This is called the dead zone. As described above, this dead zone needs to be made as small as possible in order to secure the C / N ratio of the VCO. The phase comparison circuit shown in FIG. 3 is described in Japanese Utility Model Laid-Open No. 53-100858. (C) Problems to be solved by the invention In the receiving system, the dead zone of the phase comparator circuit as small as possible is used in FIG. 3 in order to improve the S / N ratio. However, when a strong voltage level of 120 to 130 dB is applied to the antenna input, a beat may occur. It is considered that this is because the RF signal causes the oscillation frequency or phase fluctuation of the VCO, although the degree depends on the electrical characteristics or physical arrangement of the front end of the tuner. That is,
When the oscillation frequency or the phase of the VCO fluctuates, the charge pump circuit outputs a pulse corresponding to the phase difference because the dead zone of the phase comparison circuit is small even if the fluctuation is slight. If this pulse cannot be smoothed by LPF,
As shown in FIG. 5, a sideband is generated in the VCO, and a beat between the sideband and the received signal is generated. (D) Means for Solving the Problems The present invention was created in view of the above points,
A first delay circuit for sequentially delaying the reference frequency signal R _E applied to the clock input terminal of the first D-FF, and a second D-FF
A second delay circuit for sequentially delaying the variable frequency signal P _E applied to the clock input terminal of the FF, and a plurality of delay signals of the first and second delay circuits are selected based on the control signal, respectively. And the first applied to the reset input terminal of the second D-FF
And a second selection circuit, and the delay zone is changed by selecting the delay signal by the control signal. (E) Action According to the above-mentioned means, on the other hand, for example, the reference frequency signal
If R _E is faster than the variable frequency signal P _E , the first D-FF is set and its output gradually rises (or falls). When the output of the first D-FF reaches the threshold voltage of the charge pump circuit, the MOS of the charge pump circuit is turned on and an output corresponding to the phase difference is generated. However, before reaching the threshold voltage, the variable frequency signal P _When the first D-FF is reset by the delayed signal delayed by _E , the MOS of the charge pump circuit is not turned on and the output according to the phase difference is not generated. That is, the reference frequency signal R _E and the variable frequency signal P _E
, The phase difference is not recognized as the phase difference if the phase difference is shorter than the delay amount of the selected delay signal. Therefore, the dead zone can be changed by changing the delay amount. (F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. A reference frequency signal R _E obtained by dividing the oscillation output of a crystal oscillator circuit (not shown) or the like is applied to the clock input terminal CK ₁ of the first D-FF (4), and VCO (not shown) The variable frequency signal P _E obtained by dividing the oscillation frequency of is applied to the clock input terminal CK ₂ of the second D-FF (5). The output ₂ of D-FF (5) is applied to the input terminal D ₁ of D-FF (4),
The output of D-FF (4) is applied to the input terminal D ₂ of FF (5), the output Q ₁ is applied to the gate of the N-channel MOS (7) of the charge pump circuit (6), and the output Q ₂ Is applied to the gate of an N-channel MOS (8). The reference frequency signal R _E is applied to the first delay circuit (9), while the variable frequency signal P _E is applied to the second delay circuit (10). The first and second delay circuits (9) and (10) are
Each of the inverters (11) and (12) is cascade-connected in eight stages, and four delay signals are extracted for each two stages and applied to the first selection circuit (13) and the second selection circuit (14). To be done. The first and second selection circuits (13) and (14) each have four ANDs.
It is composed of gates (15) (16) and OR gates (17) (18). The AND gates (15) (16) receive the delay signals of the first and second delay circuits (9) (10), respectively. Applied, which is controlled by the control signals DZA, DXB, DZC, DZD. Control signal DZA, DZB, D
ZC and DZD are created by a decoder (19) that decodes the dead zone selection data DZ0 and DZ1. The output R ₁ of the first selection circuit (13) is the reset input terminal R ₂ of the D-FF (5).
And the output R ₂ of the second selection circuit (14) is applied to the D-FF.
It is applied to the reset input terminal R ₁ in (4). In FIG. 1, when the threshold voltage of the N-channel MOS (7) is Vt _L and the threshold voltage of the N-channel MOS (8) (voltage from the ground level) is Vt _H , D-FF (4) The time until the output Q ₁ rises and reaches the threshold voltage Vt _L , and the output Q of D-FF (5)
The output circuits of D-FF (4) and (5) are designed so that the time until ₂ rises to reach the threshold voltage Vt _H becomes equal. This can be realized, for example, by appropriately setting the transistor size of the output circuit. When the charge pump circuit (6) is composed of a C-MOS, the output of D-FF (5) is applied to the threshold voltage of the P-channel MOS (voltage with power supply V _DD as a reference).
The time it takes for ₂ to fall and reach is D-FF (4)
It is equal to the case of. The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2A shows dead zone selection data DZ0.
And DZ1 are both "0", and the delay signal with the longest delay is selected by the control signal DZA. First, when the phase of the reference frequency signal R _E matches the phase of the variable frequency signal P _E (shown by (a) in FIG. 2A), the variable frequency signal P _E and the reference frequency signal R _E By rising, D-
The FFs (4) and (5) both take their inverted outputs “1” and output them to the outputs Q ₁ and Q ₂ , respectively. This output Q ₁ and Q ₂ , the second
It rises at the slopes shown by solid lines Q ₁ (a) and Q ₂ (a) shown in FIG. When the outputs Q ₁ and Q ₂ reach the threshold voltages Vt _L and Vt _H , respectively (DQT), the outputs R ₁ and R _{2 of} the first and second selection circuits (13) and (14) rise. That is,
The maximum delay amount of the first and second delay circuits (9) and (10) is DQ
It is designed to be equal to T, and outputs R ₁ and R ₂ reset D-FF (4) and (5) together, and outputs Q ₁ and Q ₂ drop. Therefore, in this case, N channels
Both MOS (7) and (8) do not turn on, and output P according to the phase difference
D is not output. Further, as shown in (b) of FIG. 2 (A), when the reference frequency signal R _E is advanced by 10 nsec, the D-FF (4) is
Taking in "1", the output Q ₁ rises as indicated by the broken line indicated by Q ₁ (b). On the other hand, D-FF (5) is delayed by 10 nsec,
At the rising edge of the variable frequency signal P _E , “1” is captured and its output Q ₂ rises. Next, from the first selection circuit (13), R ₁
Is output, the D-FF (5) is reset by its R ₁ and the output Q ₂ is output to Q before reaching the threshold voltage Vt _{H.
2 It} falls like the broken line indicated by (b). On the other hand, DF
The output Q ₁ of F (4) reaches the threshold voltage Vt _{L as shown} by Q ₁ (b), and then the output R of the second selection circuit (14)
_{By 2} , D-FF (4) is reset.
Therefore, the N-channel MOS (7) is turned on and the output PD “0” corresponding to the phase difference is output while the output Q ₁ is equal to or higher than the threshold voltage Vt _L. That is, in the case of FIG. 2A, when the reference frequency signal R _E becomes faster, the threshold voltage Vt _L is always reached before the output R ₂ is output, and the dead zone becomes zero. . Next, FIG. 2B shows dead zone selection data DZ0.
= "1" and DZ1 = "0", the control signal DZB
Inverters (11) and (12), respectively, from the most delayed signal
This is the case where a delayed signal that is two times earlier is selected. First, when the phase of the reference frequency signal R _E matches the variable frequency signal P _E (shown by (a) in FIG. 2B), the output Q of the D-FF (4) and (5) ₁ and Q ₂ are as before, increases in slope, shown by a solid line Q ₁ (i) and Q ₂ (i). Therefore, the output of the first and second selection circuits (13) (14)
R ₁ and R ₂ occur at the point where the maximum delayed signal occurs
Since it becomes faster than DQT, the outputs Q ₁ and Q ₂ naturally do not reach the threshold voltages Vt _L and Vt _H , respectively, and D-FF (4)
(5) is reset. Now, assuming that the outputs R ₁ and R ₂ are delayed signals 10 nsec earlier than DQT, if the reference frequency signal R _E is 10 nsec earlier as shown in (b) of FIG. 2A, D-FF The output Q ₁ of (4) rises as shown by the broken line Q ₁ (b). Then, at immediately before the output Q ₁ is reached the threshold voltage Vt _L, the output R ₂ occurs, D-FF (4) is reset, the output Q ₁ is reduced. Therefore, in the case of FIG. 2B, the phase difference between the reference frequency signal R _E and the variable frequency signal P _E is
Within 10nsec, D-FF (4) will be reset before the output Q ₁ reaches the threshold voltage Vt _L , and the N-channel MOS (7) is turned on to generate the output PD corresponding to the phase difference. There is nothing to do. That is, the dead zone is 10 nsec. When the variable frequency signal P _E becomes earlier than the reference frequency signal R _E , if it is 10 nsec or less, the output Q _{2 of} the D-FF (5) reaches the threshold voltage Vt _H before the D-FF (5 ) Is reset, so
A dead zone of 10nsec occurs. FIG. 2C shows dead zone selection data DZ0 =
This is the case where "0" and DZ1 = "1". Due to the same operation as in the case of FIG. 2B, the dead zone in this case is 20
It becomes nsec. In this way, the first and second selection circuits (13) (14)
Thus, the delay signals of the first and second delay circuits (9) and (10) are selected, and the reset signals R ₁ and R _{2 of} D-FF (4) and (5) are selected.
, The dead zone can be varied. (G) Effect of the Invention As described above, according to the present invention, in a receiving system using a PLL circuit, the occurrence of beats in a strong electric field region can be prevented by changing the dead zone of the phase comparison circuit. Therefore, a high-performance PLL circuit and a reception system can be realized. Further, since the change of the dead zone can be performed by the microcomputer or the like with the dead zone selection data, it is easy to control.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2A to 2C are timing charts showing the operation of the embodiment shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a conventional example, FIG. 4 is a characteristic diagram of a phase comparison circuit, and FIG. 5 is a VCO noise spectrum. (4) ... first D-FF, (5) ... second D-FF,
(6) ... Charge pump circuit, (9) ... First delay circuit, (10) ... Second delay circuit, (13) ... First selection circuit, (14) ... Second Selection circuit, (19) …… Decoder.

Continuation of front page    (72) Inventor Kazuhiro Kimura               2-18 Keihanhondori, Moriguchi City SANYO Electric               Inside the corporation                (56) Reference JP-A-50-156969 (JP, A)                 JP-A-55-64428 (JP, A)

Claims (1)

(57) [Claims] At least first and second memory circuits and the first and second memory circuits
A charge pump circuit connected to the output of the memory circuit, and receiving the state of the second memory circuit by the first input signal to set the state of the first memory circuit,
The second storage circuit is set to a predetermined state, the state of the first storage circuit is set by the second input signal to set the state of the second storage circuit, and the first storage circuit is set to the predetermined state. In a phase comparison circuit that is in a state, a first delay circuit that delays the first input signal and applies it to the second storage circuit, and a first delay circuit that delays the second input signal A second delay circuit applied to the memory circuit; and a delay amount selection circuit for selecting the delay amounts of the first and second delay circuits according to a control signal, and varying the dead zone by the control signal. Phase comparison circuit characterized by.