JP2672504B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a structure of mutual contacts of double-layered word lines. 2. Description of the Related Art In recent years, efforts aiming at higher integration and higher speed of semiconductor devices have become active, and particularly in the field centered on dynamic random access memory (DRAM), remarkable progress has been made. Currently, DRAMs often employ a two-layer structure word line system in order to reduce the delay due to the word line resistance. That is, it has a two-layer structure in which the word line is a lower-layer word line forming a gate electrode and the upper-layer word line is composed of a low-resistance wiring layer for speeding up. The two-layer word lines are electrically connected to each other in the mutual contact region provided between the adjacent memory cell blocks. A conventional example will be described below with reference to FIG. FIG. 2a is a diagram showing the configuration of a memory cell block,
In the figure, 11, 12 and 13 are memory cell blocks and 21 respectively.
Ha and 22 are mutual contact regions. 2b is an enlarged view of the region 8 of FIG. 2a, in which 3 is a polysilicon wiring which is a lower layer word line, 4 is an aluminum wiring which is an upper layer word line, and 5 is an upper layer word line 4. And a contact window for electrically connecting the lower word line 3 to the lower word line 3.
As shown in the figure, in order to secure a mask alignment margin between the contact window 5 and the upper and lower wiring layers 3 and 4, it is necessary to increase the line width of each wiring layer near the contact window. Therefore, in disposing the mutual contacts, the positions of the mutual contacts of the adjacent word lines in the same mutual contact region are shifted in the extension direction of the word lines to ensure the minimum distance between the wiring layers of the same layer. DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, when the positions of the mutual contacts of the adjacent word lines are displaced within the same mutual contact region as in the above-mentioned conventional example, in order to ensure the minimum distance between the wiring layers, the structure shown in FIG. The extra area 6 shown by b is required. This area 6
Is necessary for each mutual contact region, and if the number of mutual contacts is increased in order to increase the operation speed, the area occupied by the region 6 increases and the chip size increases.
Therefore, the DRAM or the like may not be mounted in a desired package, which is a practical problem. In addition, when it is mounted on a desired plastic package for the purpose of cost reduction, it becomes a more serious problem, which becomes a factor that hinders its practical use. According to the semiconductor memory device of the present invention, the positions of mutual contacts of word lines having a two-layer structure are set to two with respect to the same word line.
It is characterized in that each memory cell block is provided for each memory cell, and the mutual contacts of adjacent word lines are provided in different mutual contact regions. Effect According to the present invention, among the mutual contacts of the word lines having the two-layer structure, the mutual contacts of the adjacent word lines do not exist in the same inter-memory cell block region, and the wiring width is increased in the vicinity of the contact window. As a result, the space for ensuring the required minimum distance between the same wiring layers is unnecessary. First Embodiment Next, a first embodiment of a semiconductor memory device according to the present invention will be described.
This will be described with reference to FIGS. FIG. 1A is a diagram showing a layout example of a mutual contact region of a memory cell block and a double-layered word line, and FIGS. 1B and 1C are enlarged views of the mutual contact region. In FIG. 1a, 111, 112, 121, 122 and 131 are memory cell blocks, and 211, 212, 221 and 222 are mutual contact regions. Further, FIGS. 1b and 1c are enlarged views of the regions 7a and 7b in FIG. 1a, and 3, 4 and 5 are the same elements as in the conventional example. As shown in FIGS. 1b and 1c, the mutual contacts of adjacent word lines are not arranged in the same mutual contact region. Here, the word line extending direction of the width of the mutual contact regions in the semiconductor memory device of the present invention and W _1, whereas, if the width of the conventional case shown in FIG. 2 and W _2, in the conventional example in the present invention Since the area 6 is unnecessary, 2W ₁ <W ₂ . That is, by making the width of each memory cell block in the word line extension direction half the width of the conventional example and doubling the number of mutual contact regions as compared with the conventional example, the number of mutual contacts per word line can be increased. It is possible to secure the same number as in the conventional case, and thus to secure the concentric operating speed as in the conventional case, and to eliminate the region 6 required in the conventional example and reduce the chip size. Although aluminum wiring is used as the upper layer word line 4 and polysilicon wiring is used as the lower layer word line 3 in the above embodiment, other wiring materials may be used. EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to reduce the layout area as compared with the conventional configuration while ensuring the same operation speed as the conventional one.
It can be mounted in the desired plastic package,
Very useful in practice.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are views for explaining a semiconductor memory device of the present invention, and FIGS. 2A and 2B are views for explaining a conventional example. 111,112,121,122,131,11,12,13 …… Memory cell block, 211,212,221,222,21,22 …… Mutual contact area,
3 ... Lower layer word line (polysilicon wiring), 4 ... Upper layer word line (aluminum wiring), 5 ... Contact window, 6 ...
Areas that secure a minimum distance between wiring layers on the same layer, 7a, 7b, 8
…… Area expanded for explanation of mutual contact area.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Sumio Terakawa               1006 Kadoma Kadoma Matsushita Electronics               Inside the corporation (72) Inventor Hiroshige Hirano               1006 Kadoma Kadoma Matsushita Electronics               Inside the corporation (72) Inventor Hiroko Kuriyama               1006 Kadoma Kadoma Matsushita Electronics               Inside the corporation (72) Inventor Mikio Kishimoto               1006 Kadoma Kadoma Matsushita Electronics               Inside the corporation (72) Inventor Joji Nakane               1006 Kadoma Kadoma Matsushita Electronics               Inside the corporation                (56) References JP-A-61-274358 (JP, A)

Claims (1)

(57) [Claims] A plurality of memory cell blocks in which memory cells are two-dimensionally arranged are arranged along the extension direction of the word line, and a region for mutual contact of the two-layer structure word line is provided between the adjacent memory cell blocks, Arranging the mutual contacts to the same word line in a region for mutual contacts located every two memory cell blocks or more,
Further, the semiconductor memory device is characterized in that mutual contacts of adjacent word lines are arranged in different mutual contact regions.