JP2669461B2 - Automatic impedance matching method and device - Google Patents

Description

The present invention relates to an automatic impedance matching method for automatically matching the matching impedance of a high frequency power supply and the load circuit impedance to efficiently supply power to a load. And the device. [Prior Art] This type of automatic impedance matching technology is used in power supply equipment for various purposes. For example, FIG. 2 shows an automatic impedance matching device conventionally used in a high-frequency power supply for generating plasma used for etching a surface of a semiconductor wafer. In the figure, reference numeral 1 is a conventional automatic impedance matching device, and this matching device 1 is arranged between a high frequency power source 2 and a load 3, and a load circuit impedance Z is fixed by an internal impedance Z _S of the high frequency power source 2. Automatically with the matching impedance of The load 3 is composed of a discharge part for generating plasma and a workpiece (not shown) processed by the plasma. In the figure, an equivalent resistance R _P and an equivalent capacitor C _{P are used.}
Indicated by The automatic impedance matching device 1 includes a series circuit including an inductance L and a first variable capacitor C1 connected in series to a load 3, and a second circuit connected in parallel to the series circuit and the load 3. The matching circuit 11 including the variable capacitor C2 of FIG. The load circuit impedance Z matched with the above-described matching impedance is an impedance obtained by combining the impedance of the load 3 and the impedance of the matching circuit 11, and the impedance matching is achieved by changing the capacitances of the first and second variable capacitors. Done. Therefore, in the conventional automatic impedance matching device 1, a phase difference that detects a phase difference between the total current and the high frequency voltage and outputs a phase difference detection signal from the vector values of the total current and the high frequency voltage output from the high frequency power supply. From the absolute value of the detector 12 and total current and high frequency voltage,
An impedance difference detector 13 that detects a difference between the matching impedance and the load circuit impedance Z and outputs an impedance difference detection signal is provided. In addition, the phase difference detector 12
A first control circuit 14 for controlling the first driving means 16 to change the capacitance of the first variable capacitor C1 so that the phase difference becomes zero based on the phase difference detection signal outputted from A second variable capacitor C2 for changing the capacitance of the second variable capacitor C2 to zero the impedance difference based on the detection signal;
And a second control circuit 15 for controlling the driving means 17 of. The basic operation of the automatic impedance matching device 1 is as follows.
For example, as described in detail in Japanese Patent Application Laid-Open No. Sho. FIG. 3 shows the current flowing through the load 3, that is, the matching circuit 11;
Current flowing through the variable capacitor C1 and the inductance L (Hereinafter referred to as load current) and the current flowing through the second capacitor C2 FIG. 6 is a diagram showing a locus of a vector of FIG. Load current I1 is E / ｛R _P
+ J [ωL− (1 / ωC1) − (1 / ωC _P )]}, and when the first variable capacitor C1 is varied, the vector becomes Locus of the tip is a circle centered on the E / 2R _P. vector Turns clockwise when the capacitance of the first variable capacitor C1 increases, and turns counterclockwise when the capacitance decreases. X1 in the figure
Is the tip position of the vector when the capacitance of the first variable capacitor C1 is minimum, and X2 is the tip position of the vector when the capacitance is increasing. In FIG. 3, the high-frequency voltage Extends on the X-axis. Further, FIG. 3 only shows the general tendency of the vector locus, and the absolute value of the vector when the capacity of the first variable capacitor C1 is maximum as shown in FIG.
The capacity of the first variable capacitor C1 is not always smaller than the absolute value when the capacity is the minimum. Also current Is expressed as E · jωC2, so the second variable capacitor
Current vector when the capacitance of C2 is varied Draws a trajectory that moves on the Y-axis. In FIG. 3, Y1 is the tip position of the vector when the capacitance of the second variable capacitor C2 is minimum, and Y2 is the tip position of the vector when the capacitance is maximum. When the capacitances of the first and second variable capacitors are varied, the total current vector Moves within the area shown by oblique lines in FIG. When the impedances match, the total current vector And high frequency voltage vector And the same phase, and the internal impedance of the high frequency power supply
Z _S and the load circuit impedance Z are equal. Therefore, the total current vector during matching Is located at the position M in FIG. The semicircle shown by the broken line in FIG. 4 is a semicircle having a radius of E / Z _S , and the intersection of the X axis and this semicircle is the position indicated by the symbol M. In FIG. 4, point A is the first and second variable capacitors C1 and C2.
Vector when the capacity of each is maximum At the position of the tip of the point B, when the capacity of the first variable capacitor C1 is minimum and the capacity of the second variable capacitor C2 is maximum at point B, the capacity of the first variable capacitor C1 is maximum at point C and the second variable capacitor C2 is variable. When the capacitance of the capacitor C2 is the minimum, the point D is the vector when the capacitances of the first and second variable capacitors C1 and C2 are the minimum. Is the position of the tip. Note that the total current vector Is not matched when is at a position other than the point M, the apparatus adjusts the capacitance of the capacitors C1 and C2 to adjust the vector Operates to approach point M. [Problems to be Solved by the Invention] In the high-frequency power supply equipment shown in FIG. 2, a mismatch state occurs due to a change in plasma load or the like.
An operation of reducing the capacitance of the first variable capacitor C1 may be performed to achieve matching. However, often, the first driving means 16 is driven to a position where the capacity of the first variable capacitor C1 is minimized and is constrained at that position, and the capacity of the first variable capacitor C1 cannot be controlled, so that matching is impossible. Is known to occur. Conventionally, there has been proposed a technique for escaping the device from the unmatchable state when the unmatchable state is found. For example, Japanese Laid-Open Patent Publication No. 60-134512 detects that the first variable capacitor has the minimum capacitance, focusing on the fact that the first variable capacitor C1 reaches the minimum capacitance position when the matching is impossible. A technique is provided for increasing the capacitance of the first variable capacitor when the capacitance of the first variable capacitor is minimized. However, according to the technique disclosed in this publication, it is impossible to know whether the matching is possible or impossible until the capacitance of the first variable capacitor is minimized, and the impedance of the high frequency device is quickly matched. There was a problem that it was not possible. SUMMARY OF THE INVENTION It is an object of the present invention to provide an automatic impedance matching method and apparatus capable of preventing in advance of a matching failure in a matching process. [Means for Solving the Problems] In the method of the present invention, in order to solve the above problems, the capacity is changed so that the phase difference between the total current output from the high frequency power supply and the high frequency voltage becomes zero. A matching circuit including a variable capacitor No. 1 and a second variable capacitor whose capacitance is changed so that the impedance difference between the matching impedance and the load circuit impedance is zero is provided between the high frequency power source and the load, and the phase difference is provided. And a method of automatically matching impedances by detecting the impedance difference and adjusting the capacitances of the first and second variable capacitors,
Supplied to the load The phase difference θ1 with respect to is always detected, and when the phase difference θ1 is in the uncontrollable region, the capacitance of the first variable capacitor is forcibly increased. Further, in the device of the present invention, in order to carry out the method of the present invention, the output from the high-frequency power source 2 is used. And a power-supply-side phase difference detector 12 for detecting a phase difference θ between the power supply-side phase difference detection signal and the impedance difference between a matching impedance and a load circuit impedance. An impedance difference detector 13 that outputs an impedance difference detection signal corresponding to the difference, a first variable capacitor C1 whose capacitance is changed so that the phase difference θ is zero, and a capacitance is changed so that the impedance difference is zero. A matching circuit 11 including a second variable capacitor C2 and arranged between the high frequency power supply 2 and the load 3, and a first driven to change the capacitance of the first variable capacitor C1.
Drive means 16 and second drive means 17 driven to change the capacitances of the second variable capacitor C2, and the first drive means 16 for controlling the first drive means 16 based on the power source side phase difference detection signal 12. An automatic impedance matching device including a control circuit 14 and a second control circuit 15 that controls the second driving means 17 based on the impedance difference detection signal is used as a basic configuration. And in the present invention, it is supplied to the load 3. A load-side phase difference detector 18 for detecting a phase difference θ1 between When the load-side phase difference detector detects that the phase difference θ1 between the first and second variable capacitors C1 and C1 is in the uncontrollable region, the first driving means 16 is forcibly driven so as to increase the capacity of the first variable capacitor C1. Means 22 and are provided. [Operation of the Invention] In the present invention, the load current I1 and the high-frequency voltage When the phase difference θ1 is included in the “uncontrollable area” that is determined by constantly monitoring the phase difference θ1 with Causes the operation of increasing the capacitance of the first variable capacitor C1. Therefore, the matching operation can be quickly returned to the matching possible state before the unmatchable state is reached. Example An example of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of an apparatus for carrying out the method of the present invention. In this figure, the same parts as those constituting the conventional apparatus shown in FIG. 2 are denoted by the same reference numerals as those used in FIG. The difference from the conventional device of FIG. 2 is that the load current and the high-frequency voltage are applied between the junction of the impedance difference detector 13 and the second variable capacitor C2 and the first variable capacitor C1. The output signal of the load side phase difference detector 18 exceeds a predetermined level because the load side phase difference detector 18 detects the phase difference θ1 with First level comparison circuit 19 which detects by detecting that
And a second level comparison circuit 20 that detects that the phase difference θ between the total current and the high frequency voltage has become a delayed phase, and a maximum capacity detection that detects that the first variable capacitor C1 has reached the maximum capacity. When the load-side phase difference detector 18 detects that the phase difference θ1 between the load current and the high-frequency voltage is in an uncontrollable region, the first drive is performed so as to increase the capacitance of the first variable capacitor. That is, a forced driving means 22 for forcibly driving the means 16 is provided. The details of the embodiment will be described later in detail, and the case where these means are not used, that is, the reason why an incompatible state occurs in the conventional apparatus will be discussed. It is known that the reason why the unmatchable state occurs is not one but various conditions overlap. Therefore, an exemplary operation in the case where the matching is performed will be described, and then a typical example in which the matching becomes impossible will be described. First, the total current vector The operating conditions when the tip of the above is within the regions I to IV in FIG. 4 are as shown in Table 1 below. As shown in Fig. 5, the total current vector in the matched state is , The load current vector and the current vector flowing through the capacitor C2. To be . Here, the load condition changes and the first variable capacitor C1
The capacity of the total current increases Moved to P1 position And From this state, the matching operation is started under the conditions shown in Table 1, and the vector The variable capacitors C1 and C2 are increased or decreased according to the regions I to IV where the tips of the variable capacitors are located at that time. Figure 6 shows the total current vector when the matching operation is performed. The locus of the tip of is shown. As can be seen from the figure, all current vectors The tip of the arrow approaches the matching point M while rotating clockwise around the matching point M. Due to load fluctuation, the capacity of the first variable capacitor C1 decreases and the total current vector The tip of is in the position of point P2 in Fig. 6. Then, since P2 is in the region III of FIG. 4, both the first and second variable capacitors C1 and C2 decrease. If the rate of decrease of the capacity of the variable capacitor C1 is smaller than the rate of decrease of the capacity of the capacitor C2, the total current vector 6 goes toward Q1 in FIG. 6, and conversely, when the rate of decrease of the capacitance of the variable capacitor C1 is large, it goes toward Q2 and finally reaches point D. Total current vector Even after the tip of the head has reached the point D, the first and second driving means 16 and 17 for driving the variable capacitors C1 and C2 are still in the region III. From the circuits 14 and 15, the signal that tries to keep the capacity of both capacitors at the minimum position, that is, the current from the first control circuit Signal that tries to rotate the counterclockwise, and the second
Current from the control circuit of The signal that tries to decrease is continuously output. As a result, the total current vector Is constrained to point D, and an unmatchable state occurs. In addition, there are cases where either a matching state or a matching failure occurs depending on the conditions. For example, as shown in FIG. When the tip of the target moves out of the matching point M and moves to the position of P3, there are a case where the state can be returned to the matching state and a case where the matching becomes impossible. All current vectors at the position of P3 When the tip of And the current vector flowing through the second variable capacitor C2 There is not a single combination with There are two cases. Since the position of P3 is in the region III shown in FIG. 4 and Table 1, both the first and second variable capacitors C1 and C2 are adjusted so that the capacitance decreases when performing the matching operation. . In the case of, when the decreasing speed of the capacitance of the variable capacitor C1 is slow and the decreasing speed of the capacitance of the capacitor C2 is fast ( If the decrease rate of P is fast), the total current vector from the position of P3 The tip of can enter the area surrounded by T, U and K. Since this area is area IV as shown in FIG. 4,
Total current vector If the tip of is in this area, the total current vector Becomes a delay phase and the vector rotation direction turns clockwise, so that it is possible to return to the matching point M. On the other hand, when the rate of decrease of the capacitance of the first variable capacitor C1 is fast and the rate of decrease of the capacitance of the second variable capacitor C2 is slow ( If the rate of decrease is slow), the current Increases the total current vector May enter the area on the right side of straight line HK. When this happens, the current Even if is minimized, the total current vector Has no lag phase, so the total current vector Continues to rotate in the counterclockwise direction, and is finally constrained to point D. Also , The current vector is reduced when the capacitances of the first and second variable capacitors are reduced. Decreases in the lead phase, so the current vector Even if 2b decreases to the minimum value I2 (C2min), the total current vector Remains in the lead phase. Therefore the total current vector The tip of the can not be removed from the region III, continues to rotate in the counterclockwise direction, and is finally restrained at the point D. The above example is an example of the case where the matching becomes impossible, and the condition that the matching becomes impossible is not limited to the above example. According to various experiments and studies by the inventor, the total current vector Position (P), load current vector And the rate of change of the capacitance of the first and second variable capacitors ( It has been found that an incompatibility state occurs due to the change speed of). The conditions of the propriety determined so far are as schematically shown in Table 2 below by explicitly specifying the area by the code used in FIG. As a result of examining the conditions for falling into the unmatchable state as described above, the inventor found that most of the unmatchable states that actually occur are It was found that most of them can be detected by monitoring the relationship of the phase difference θ1 with. That is, In the advanced phase with respect to However, it has been found that when there is a lag phase relationship within a certain range, a large number of unmatchable states occur. The criterion for determining whether incompatibility occurs is, for example, in order to find out the incompatibility most quickly, the total current vector in the area surrounded by BDEJKGFB in Fig. 7 and near the KJE boundary line. Load current when the tip of the Is defined as an “uncontrollable region”, and the load current When enters into this area, it is determined that the matching is impossible regardless of whether or not the matching becomes impossible. Total current vector If the end of the load is within the range enclosed by EJHE, Since there is a possibility that matching may be achieved if the two have a lag phase relationship, an uncontrollable region other than this region may be used to increase the reliability of the determination. Even if there is a slight time delay, be sure to check the load current when the matching becomes impossible. Since the phase of the load current advances, the region where the load current advances the phase may be an uncontrollable region. The embodiment shown in FIG. 1 for implementing the above technical idea will be described in detail. The power supply side phase difference detector 12 has a configuration similar to a known configuration, and all current vectors And high frequency voltage vector And outputs a power-supply-side phase difference detection signal V corresponding to the phase difference θ between As shown in FIG. 8, the high-frequency voltage vector Forward 90 ° And the absolute value of the vector synthesized And high frequency voltage vector Advance 90 degrees And the absolute value of the vector synthesized Va−Vb is the high frequency voltage vector And the total current vector Corresponding to the phase difference. Therefore, the phase difference detector 12 outputs a phase difference detection signal shown in the following equation (1). When V = 0 in the above equation (1), Are in phase (θ = 0). And the first control circuit 14
Outputs a drive signal Vd for driving the first drive means (for example, a DC motor) based on the detection signal V. The load-side phase detector 18 uses the same principle as the power-side phase difference detector 12 to And outputs a load-side phase difference detection signal V1 of an analog amount corresponding to the phase difference θ1 between Is in phase, V1 = 0, When the phase is delayed with respect to, the signal V1 has a negative polarity, , The signal V1 has a positive polarity. Reference numeral 19 is a first level comparison circuit which outputs a level detection signal V1 'when the signal 1 output from the load side phase difference detector 18 exceeds a predetermined level. This level comparison circuit is a well-known level comparison circuit configured by using, for example, a plurality of operational amplifiers and reference voltage generating means. The level of this comparison circuit is set as described above in BD of FIG.
Total current in the area surrounded by EJKGFB When the range of the phase difference θ1 of the load current when the tip of the vector is included is defined as the “uncontrollable region”, it is determined so that the phase difference θ1 can be detected in this region. Even if there is a slight delay, be sure to load current Since it becomes an advanced phase, when the region where the load current becomes an advanced phase is an uncontrollable region, the level may be set so that it can be detected that the signal V1 has a positive polarity. Reference numeral 20 is a second level comparison circuit similar to the first level comparison circuit 19. In this level comparison circuit 20, the signal V output from the phase difference detector 12 on the power supply side has a negative polarity and the total current is delayed. , A level detection signal V 'is output. The specific configuration is the same as that of the first level comparison circuit. The maximum capacitance detector 21 is composed of, for example, a limit switch, and outputs the detection signal V2 when the first variable capacitor C1 is driven by the first drive means 16 and reaches the maximum capacitance state. The forced drive means 22 drives the first drive means 16 so as to increase the capacity of the first variable capacitor C1.
It comprises a forced drive signal source 22a for generating V3 and a control switch 22b. When the first level comparison circuit 19 outputs the signal V1 'indicating that the phase difference .theta.1 between the load current and the high frequency voltage is in the unmatchable region, the control switch 22b controls the first driving means 16. The control by the output signal Vd of the first control circuit 14 is switched to the control by the drive signal V3 output from the forced drive signal source 22a, and the maximum capacitance detector 21 changes to the first variable capacitor.
When the detection signal V2 indicating that C1 is at the maximum capacity is output or the detection signal V'representing that the total current is in the delay phase is output from the second level comparison circuit 20, The control of the drive means 16 is switched from the control by the drive signal V3 output from the drive signal source 22a to the control by the output signal Vd of the first control circuit 14 (return to automatic matching operation). In the present embodiment, both the second level comparison circuit 20 and the maximum capacity detector 21 are provided, but this is to quickly return to the automatic matching operation. The second level comparison circuit 21 or the maximum capacity detector 21 may be allowed if a slight delay at the time of restoration is allowed.
Only one of these may be used. In each of the above embodiments, the DC motor was used as the first and second driving means, but it goes without saying that other types of motors can be used as these driving means. [Effect of the Invention] According to the method of the present invention, the phase difference between the load current and the high-frequency voltage is constantly monitored, and it is determined that the matching is impossible or the matching is likely to be impossible. When the phase difference enters the determined uncontrollable region, the operation of increasing the capacity of the first variable capacitor C1 is performed.
The matching operation can be quickly returned to the matching possible state. Further, according to the apparatus of the present invention, the method of the present invention can be reliably performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, FIG. 2 is a schematic configuration diagram showing a conventional device, and FIG. 3 shows a load current and a second variable capacitor. A circular diagram of the flowing current, FIG. 4 is an explanatory diagram showing a region where the tip of the vector of the total current moves, and FIG. 5 is a vector of the total current and a vector of the current flowing through the load current and the second variable capacitor Diagram showing the relationship,
FIG. 6 is an explanatory view for explaining a matching operation and a mismatching operation, FIG. 7 is an explanatory view for explaining a mismatching condition, and an eighth.
The figure is an explanatory view for explaining the operation of the phase difference detector. 2 ... High frequency power source, 3 ... Load, 11 ... Matching circuit, 12 ...
... Phase difference detector on power supply side, 13 ... Impedance difference detector, 14 ... First control circuit, 15 ... Second control circuit, 16
...... First driving means, 17 ...... Second driving means, 18 ...... Load side phase difference detector, 19 ...... First level comparison circuit, 20 ...
… Second level comparison circuit, 21… Maximum capacity detector, 22…
... forced drive means, 22a ... forced drive signal source, 22b ... control switch, C1 ... first variable capacitor, C2 ... second variable capacitor.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-60-134512 (JP, A)                 Japanese Patent Publication Sho 37-3951 (JP, B2)                 Actual public Sho 61-30332 (JP, Y2)

Claims (1)

(57) [Claims] To reduce the impedance difference between the matching impedance of the first variable capacitor whose capacitance is varied to zero the phase difference between the total current output from the high frequency power source and the high frequency voltage and the high frequency power source, and the load circuit impedance. A matching circuit including a second variable capacitor having a variable capacitance is provided between the high frequency power supply and the load, and the capacitance of the first and second variable capacitors is detected by detecting the phase difference and the impedance difference. In a method for automatically matching impedance by adjusting the phase difference between the load current supplied to the load and the high-frequency voltage, and the phase difference is in an uncontrollable region. The impedance of the variable capacitor is forcibly increased. 2. 2. The automatic impedance matching method according to claim 1, wherein said first variable capacitor is increased to a maximum capacitance. 3. The automatic impedance matching method according to claim 1, wherein a predetermined delay region and a lead phase region before the load current has the same phase as the high frequency voltage are the uncontrollable regions. 4. The automatic impedance matching method according to claim 1, wherein a region where the load current has a lead phase with respect to the high frequency voltage is the uncontrollable region. 5. A power supply side phase difference detector that detects a phase difference between the total current output from the high frequency power supply and the high frequency voltage and outputs a power supply side phase difference detection signal corresponding to the phase difference, and a matching impedance and load of the high frequency power supply. An impedance difference detector that detects an impedance difference from the circuit impedance and outputs an impedance difference detection signal corresponding to the impedance difference, a first variable capacitor whose capacitance is changed to zero the phase difference, and the impedance. A matching circuit including a second variable capacitor whose capacitance is varied to make the difference zero, and a matching circuit disposed between the high frequency power supply and the load, and a first driving circuit configured to change the capacitance of the first variable capacitor. 1 drive means and a second drive means driven to change the capacitance of the second variable capacitor; An automatic impedance matching device comprising: a first control circuit for controlling the first driving means based on the above; and a second control circuit for controlling the second driving means based on the impedance difference detection signal. In the load side phase difference detector for detecting the phase difference between the load current supplied to the load and the high frequency voltage, the phase difference between the load current and the high frequency voltage is in an uncontrollable region. An automatic impedance matching device comprising: a forced drive means for forcibly driving the first drive means so as to increase the capacity of the first variable capacitor when detected by the load side phase difference detector. . 6. The forced drive means is based on an output of the load side phase difference detector, and a forced drive signal source that generates a drive signal for driving the first drive means so as to increase the capacity of the first variable capacitor. When it is detected that the phase difference between the load current and the high frequency voltage is in the range of the uncontrollable region, the control of the first drive means is controlled from the control by the output signal of the first control circuit. The automatic impedance matching device according to claim 5, further comprising a control switcher that switches to control by a drive signal output from a drive signal source. 7. The control switching device outputs the detection signal from a maximum capacitance detector that detects that the first variable capacitor is at the maximum capacitance, or detects that the total current is in a delay phase. 6. The automatic impedance matching device according to claim 5, wherein the control of the first driving means is switched from the control by the drive signal output from the drive signal source to the control by the output signal of the first control circuit.