JP2668535B2 - Image sensor charge storage time controller - Google Patents

Description

TECHNICAL FIELD The present invention relates to a charge storage time control device for an image sensor, which is used as a focus detection device for a camera for photography. 2. Description of the Related Art A recent camera having an auto-focus function makes subject light incident on an image sensor and performs focus detection from this video signal (image signal). Many image sensors use a CCD type image sensor.In general, a subject image is formed on a reference area and a reference area provided on the light receiving surface of the image sensor, and the reference area is compared with the image of the reference area. The so-called phase difference detection method that detects the focal point by matching the images, and the so-called contrast detection method that utilizes the fact that the contrast of the subject image formed on the image sensor at the time of focusing is maximized are adopted. ing. FIG. 9 is a block diagram of an image sensor shown as a conventional example. The image sensor is a known CCD image sensor, and is composed of a sensor array 11 having a standard area and a reference area, a reset gate 12, a shift gate 13, and a CCD shift register 14, and the image sensor is provided in close proximity. The charge accumulation time is determined by the monitor voltage Vm by the monitor sensor 15. That is, as shown in FIG. 10, the monitor voltage Vm is input to the sensor array 11 together with the reset pulse φr to
The sensor array 11 accumulates charges until the monitor voltage Vm reaches a predetermined set voltage Vt. The charge amount thus accumulated is transferred to the CCD shift register 14 by the input of the shift pulse φs, and then sequentially sent out from this shift register 14 in accordance with the transfer pulses φ ₁ and φ ₂ , and the video signal voltage Vos is outputted from the preamplifier 17. Output. The video signal voltage Vos is compared with a compensation voltage Vcs output from the amplifier 18, and the difference voltage is digitally converted by an A / D converter and sent to a signal processing circuit to perform a distance measurement operation. “Problems to be Solved by the Invention” In the case of the above-described conventional example, the sensor 15 for monitoring monitors the average luminance distribution in the reference region on the sensor array 11, and therefore the sensor array 11 has a high contrast ratio. When an image is projected, or when a part of the pixel is exposed to strong light, as shown by the charge amount curve A shown in FIG. Vos cannot be obtained, and an error appears in the distance measurement calculation result. To avoid this saturation, set the monitor voltage Vm to the set voltage Vt.
Can be set to a low level.However, in this case, the amount of accumulated charge decreases when detecting a subject with a low contrast ratio, the SN ratio of the video signal voltage Vos deteriorates, and there is a sufficient margin from the saturation region. This will limit the amount of charge storage at a level that has a certain level, and it is not preferable because it is used in a state where the SN ratio is low without effectively utilizing the capacity of the image sensor. In addition, in the case of the above-described conventional example, the monitor sensor 15 does not receive the light of the same subject or the subject portion as the image sensor, so that the intended charge accumulation amount may not be controlled depending on the subject. On the other hand, when the contrast ratio of the subject image projected on the sensor array 11 is small, the signal change component − (Vmax−Vmin) of the video signal voltage Vos is the difference voltage − (Vmax−Vmin) between the video signal voltage Vos and the compensation voltage Vcs. Since it is much smaller than the average voltage of Vos−Vcs), a high-resolution A / D converter is required. Further, since the time from when the monitor voltage Vm corresponding to the average output signal reaches the set voltage Vt after the reset pulse φr is input is set as the charge accumulation time of the image sensor, the difference voltage− (Vos−Vcs) described above is used. Becomes constant, and this constant voltage is amplified and input to the A / D converter. In a special case where the brightness of the subject is dark and the monitor voltage Vm does not reach the set voltage Vt within the specified time, the difference voltage − (Vos−Vcs) above is amplified according to the level of the monitor voltage Vm. Was. Even in such a case, since the amplification degree is in accordance with the average voltage of the difference voltage− (Vos−Vcs), A / D conversion cannot be performed effectively for a subject having a small difference in brightness. In addition, the conventional image sensor has a problem that when focus detection is performed on a dark subject on average, a long charge accumulation time is required even when there is a sufficient contrast ratio. "Means for solving the problems" The present invention has been developed in view of the above problems,
Of the light incident on image sensors such as CCD elements,
It includes a circuit that inputs a detection signal of a maximum light detection circuit that electrically detects the most partial light and a minimum light detection circuit that electrically detects the weakest partial light, and that outputs a difference signal between them. A charge storage time control device for an image sensor, comprising: a circuit for regulating the charge storage time of the image sensor by a difference signal. "Working" Depending on the contrast of the image projected on the image sensor, the detection signal of the strongest partial light and the detection signal of the weakest partial light are obtained, and at the time when this difference signal reaches a predetermined level. Accordingly, the charge accumulation time of the image sensor is regulated. Therefore, when the contrast ratio of the image projected on the image sensor is high, the charge storage time is controlled to be short, and when the contrast ratio is not high, the charge storage time is controlled to be relatively long. "Example" Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a control circuit showing an example in which the present invention is applied to an image sensor for focus detection.
Is a sensor array, 22 is a reset gate, 23 is a shift gate, and 24 is a CCD shift register, which are the same as the conventional example constituting the image sensor. It has already been described that this image sensor operates by receiving a reset pulse φr, a shift pulse φs, and transfer pulses φ ₁ and φ ₂ sent from the drive control circuit 25 to output a video signal Vos. The image sensor includes a maximum light detection circuit 26 for electrically detecting the strongest partial light among the light incident on the reference area of the sensor array 21 and a minimum light detection circuit 27 for electrically detecting the weakest partial light. Is provided. FIG. 2 is a circuit diagram showing a specific example of these detection circuits 26 and 27. In this specific example, N-channel MOS-type FETs 28a, 28b, 28 having a gate connected to each photoelectric element of the sensor array 21
c,,,, by extracting the amount of charge accumulated in the photoelectric element as a source follower, Vm corresponding to the minimum light
An in signal is output, and a Vmax signal corresponding to the maximum light is output from P-channel MOS type FETs 29a, 29b, 29c,. The Vmax signal detected by the maximum light detection circuit 26 is sent to a sample / hold circuit 31 via an amplifier 30. The sampled Vmax signal is selected by a selector circuit 32 and input to a differential amplifier circuit 33. The Vmin signal detected by the minimum light detection circuit 27 is sent to another sample / hold circuit 35 via the amplifier 34, and the sampled Vmin signal and the held Vmin signal are input to the differential amplifier circuit 33. . The sample / hold circuits 31, 35 receive the sample / hold signal φsh sent from the drive control circuit 25 and switch from the sample state to the hold state. Further, the selector circuit 32 described above receives the selector signal Sel
Is configured by an analog switch that operates by inputting
When the selector signal Sel becomes a high voltage, the Vmax signal becomes a low voltage.
The video signal Vos from the shift register 24 is selected and input to the differential amplifier circuit 33. On the other hand, the Vmax signal of the maximum light detection circuit 26 is sent to the comparison circuit 37, where it is compared with a predetermined comparison voltage Vt. The comparison voltage Vt is determined so that the Vmax signal when the charge accumulation of the sensor array 21 approaches saturation is input and the comparison circuit 37 is inverted. That is, the sensor array 21
When the charge of the subject approaches the saturation due to the partial light, the comparator circuit 37 inputs and inverts the Vmax signal corresponding to the partial light. For example, if the Vmax signal is the saturation level of the sensor array 21
When it becomes about 80%, the comparison circuit 37 is inverted. The inverted output of the comparison circuit 37 is input to the shift pulse control circuit 38. The shift pulse control circuit 38 receives the shift selection signal Ss and the inverted output of the comparison circuit 37, and also receives the shift signal Es from the outside and sends the shift control signal Sc to the drive control circuit 25. The shift signal Es is sent from the microcomputer to be described later after the amplification degree of the differential amplifier circuit 33 is set according to the brightness difference of the subject by the monitor operation.
While the shift control signal Sc is being output while being input to Es, the input of the inverted output from the comparison circuit 37 is blocked. In this state, the shift control signal Sc sent to the drive control circuit 25 is shaped into an appropriate pulse, and the shift gate
Sent to 23. Further, before the amplification degree of the differential amplifier circuit 33 is set by the difference in brightness of the subject, that is, when the inverted output from the comparison circuit 37 is input to the shift pulse control circuit 38 during the monitor operation, the drive is performed in the same manner as above. The control circuit 25 sends the shift pulse φs to the shift gate 23 in the same manner as above by the input of the shift control signal Sc, and the shift monitor circuit 39 monitors that the shift control signal Sc has been sent. The shift monitor circuit 39 operates so as to monitor the shift control signal Sc and not monitor the brightness difference of the subject until the sensor array 21 starts the next charge accumulation. The control circuit of the above image sensor is the third
Various signals are exchanged with the micro-computer 60 as shown in a block 50 in the figure. Microcomputer
Shift input signal already explained as input signal from 60
In addition to Ss and shift signal Es, there are a start signal St, an amplification degree selection signal Asel, and a transfer control signal φcnt. The start signal St is a signal for instructing the start of charge accumulation in the sensor array 21. The amplification degree selection signal Asel is a signal for setting the amplification degree of the differential amplifier circuit 33. The transfer control signal φcnt is a control signal for driving the CCD shift register 24 at high speed. Normally, the output of the shift register 24 is extracted at a speed at which the output signal Vo of the differential amplifier circuit 33 can be A / D converted.When the video signal Vos is unnecessary, the shift register 24 is driven at a high speed.
Unnecessary charges are discharged. The signals output to the microcomputer 60 include the output signal Vo of the differential amplifier circuit 33 and the A / D timing signal Sad. The output signal Vo includes an output signal −Am (Vmax−Vmin) corresponding to the difference in brightness of the subject output during the monitor operation, and an output signal −A when the video signal Vos is input from the image sensor.
s (Vos−Vmin). The A / D timing signal Sad is a signal for measuring the timing of the A / D converter included in the CCD shift register 24 and the microcomputer 60, and the output signal Vo of the differential amplifier circuit 33 is stabilized so that the A / D
This signal conveys that conversion is possible. Next, the operation of the control circuit of the image sensor will be described with reference to the time chart shown in FIG. (1) Setting of the amplification degree by the monitor When the start signal St is input as a high voltage, the drive control circuit 25 outputs a reset signal φ as a low voltage.
The sensor array 21 that has output r starts charge storage. The drive control circuit 25 outputs the sample / hold signal φsh and the select signal Sel as a high voltage by inputting the shift selection signal Ss as a low voltage together with the start signal St. The sample / hold signal φsh holds both the sample / hold circuits 31 and 35 in the sample mode, and the select signal Sel selects the Vmax signal.
Switch. Further, the shift pulse control circuit 38 shifts to a state in which the shift selection signal Ss is input and the inverted output from the comparison circuit 37 is input. The differential amplification circuit 33 sets the amplification degree selection signal Asel so that the amplification degree is set to a predetermined amplification degree Am in consideration of each circuit configuration.
Supply. In the above state, the charge accumulation in the sensor array 21 progresses, and the Vmax signal detected by the maximum light detection circuit 26 and the Vmin signal detected by the minimum light detection circuit 27 are sampled by the sample / hold circuits 31, 35, respectively. Differential amplifier circuit
Enter 33. Therefore, the output signal Vo of Vm = −Am (Vmax−Vmin) (1) is sent from the differential amplifier circuit 33. The output signal Vo = Vm is subjected to A / D conversion and subjected to data processing by the microcomputer 60, and the output signal Vo = Vm
When the computer 60 reaches a predetermined level within a prescribed time predetermined by the computer 60, an amplification selection signal Asel calculated by the microcomputer 60 is sent, and the amplification Am of the differential amplifier circuit 33 is sent to the sensor array 21. Amplification As is newly set as a constant amplification according to the difference in brightness of the projected subject image. The amplification degree As is set so that As = (Vf / Vm) · Am K (2). Vf is the full scale of the A / D converter. K is a constant of 1 or less, which is a safety factor determined in consideration of the difference in the characteristics of the sensor array 21 between the above-described monitor operation and the time of outputting the video signal Vos described below. It is preferable to determine the degree. When the output signal Vo = Vm does not reach the predetermined level within the specified time, the amplification degree selection signal Asel is sent after the lapse of the specified time, and the amplification degree as the amplification degree according to the value of the output signal Vo = Vm. As is set. In this case, the output signal Vo = Vm level is determined, and when the level is insufficient for A / D conversion, the amplification degree As is switched so that the output signal Vo of the differential amplifier circuit 33 is suitable for A / D conversion. Assuming that the amplification degree selection signal Asel is supplied as a 3-bit signal, the amplification degree As can be set as shown in Table 1 below. (2) Output Operation of Video Signal Vos As described above, when the output signal Vo = Vm of the differential amplifier circuit 33 reaches a predetermined level, the amplifier circuit 33 is set to the amplification degree As and simultaneously the shift selection signal Ss is Hig from Low voltage
h voltage, and the shift pulse control circuit 38
The operation shifts to a state of inputting s, and thereafter, the input of the inverted output of the comparison circuit 37 is prohibited until the monitor operation is performed again. The shift signal Es is a positive pulse signal sent from the microcomputer 60 at the same time when the shift selection signal Ss becomes the high voltage, and the shift control signal Sc outputted from the shift pulse control circuit 38 by the input of this signal Es becomes the drive control circuit.
25, the shift pulse φs is supplied as described above, and the accumulated charges in the sensor array 21 are transferred to the CCD shift register 24. When the shift pulse φs is sent to the shift gate 23, the reset pulse φr changes from the Low voltage to the H level.
igh voltage, and the charge accumulation in the sensor array 21 stops. Thus, when the shift signal Es is supplied to the control circuit, that is, when the output signal Vo = Vm reaches a predetermined level, the charge accumulation of the sensor array 21 is stopped.
The charge accumulation time is determined according to-(Vmax-Vmin),
The higher the contrast ratio, the shorter the time, and the higher the contrast ratio, the longer the time. On the other hand, when the shift selection signal Ss changes from the Low voltage to the High voltage, the select signal Sel changes from the High voltage to the Low voltage, and the selector circuit switches from passing the Vmax signal to passing the video signal Vos. The sample / hold signal φsh also changes from the high voltage to the low voltage, and the sample / hold circuits 31, 35 are held in the hold state. The start signal St changes from High voltage to Lo
w voltage, and at the same time the transfer pulses φ ₁ and φ ₂
The data is input to the shift register 24, and the data of the shift register 24 is sequentially sent out serially, and the video signal Vos is output. As a result, the video signal Vos and the held Vmin signal are input to the differential amplifier circuit 33, and the output signal Vo is output as Vs = -As (Vos-Vmin) (3). The output signal Vo = Vs is sequentially output one pixel at a time in synchronization with the transfer pulses φ ₁ and φ ₂ , sent to the A / D converter, and the A / D converted pixel data is sequentially stored in the storage operation unit. . When all the pixel data necessary for the distance measurement calculation is stored in the storage calculation unit, the monitor amplification Am is set again, and the process proceeds to the above-described monitor operation. In FIG. 4, Ti is the charge storage time, and Ts is the CCD.
The charge signal extraction time from the shift register 24, To indicates the operation processing time, and Ti ₂ is the second charge accumulation time. As can be seen from the above equations (2) and (3), since the difference between the video signal Vos and the Vmin signal is amplified by the amplification As according to the maximum contrast of the subject, the amplification As is set when the contrast is small. When the contrast is large, the amplification factor As decreases when the contrast is large.
Vs is A / D converted with extremely high precision. For example, if a full-scale 4V A / D converter is used, when (Vmax−Vmin) is 100 mV, the amplification factor As = 40,
When (Vmax-Vmin) is 500 mV, the amplification factor As = 8-
(Vos-Vmin) signal is amplified. Further, the video signal Vos appears as shown in FIG. 6, but since the video signal Vos is not amplified as it is, but only the true signal change component is amplified as a − (Vos−Vmin) signal, the signal change Can be captured with high accuracy. For example, even if A / D conversion is performed on a 100: 90 subject at a resolution of 100, only a signal of 90 to 100 is obtained, but − (Vos−Vmin)
If the signal is amplified 10 times and A / D converted, a signal of 0 to 100 can be obtained, which is equivalent to using an A / D converter with 10 times resolution, which is effective. . FIG. 6 shows a case where the contrast is large.
The focus difference of the camera results in a smaller difference in brightness. (3) Monitoring Operation of Sensor Array Saturation The comparison circuit 37 detects whether or not the sensor array 21 has approached the saturation level of charge accumulation while monitoring the brightness difference of the subject. (See FIG. 5.) As described above, when the subject light is bright and the sensor array 21 approaches the saturation level, the comparison circuit 37 inputs the Vmax signal and inverts the signal, and outputs the inverted output to the shift pulse control circuit 38.
At this time, the shift selection signal Ss is Low, and the shift pulse control circuit 38 inputs the inverted output and sends the shift control signal Sc to the drive control circuit 25. Therefore, the above state is monitored by the shift monitor circuit 39, and the accumulated charge is transferred to the CCD shift register 24. However, at this point, the output signal Vo of the differential amplifier circuit 33 is
= Vm = −Am (Vmax−Vmin) has not reached the predetermined level, and the shift selection signal Ss is at a low voltage, so that the sample / hold circuits 31 and 35 are in the sample state, It is in the selected state. Therefore, in this case, set the amplification degree selection signal Asel again,
The output signal Vm in the equation (1) is set to reach a predetermined level. From this, the shift selection factor Ss changes from Low voltage to Hig.
The voltage changes to h, the sample / hold circuits 31 and 35 are in the hold mode, the selector circuit 32 is in the selection mode of the video signal Vos, and the differential amplifier circuit 33 outputs the output signal Vo = Vs according to the above equation (3). . In the case of the above operation, the charge storage time of the sensor array 21 becomes the time corresponding to the inversion of the comparison circuit 37. (4) Forcible execution operation In a dark state, the output signal Vo = Vm of the brightness difference monitor does not reach the predetermined level within the specified time, and the comparison circuit 37 does not invert. At this time, when the first specified time measured by the microcomputer 60 has elapsed, Vo
Based on the level determination result of = Vm, at this time, the shift selection signal Ss is set to a high voltage and the shift signal Es is validated and input, whereby the accumulated charge is transferred to the CCD shift register 24. For example, when Vo = Vm is 1/4 or more of a predetermined level and distance measurement calculation and contrast determination can be performed based on a subject pattern, or Vo = Vm based on the current monitor based on the result of contrast determination based on previously acquired data. When it is determined that the distance measurement can be performed even at the level of, and when the moving speed of the subject image on the sensor array 21 is large (during driving the lens, etc.), it is determined that extending the charge accumulation time any longer does not make sense. The shift signal Es (High) is forcibly applied. In the case where the stored charge is not transferred to the CCD shift register 24 within the first specified time, the charge storage time is extended to the second specified time, and when the second specified time is reached, the shift signal Es is unconditionally set. (High) to generate a shift pulse, and transfer the electric charge accumulated in the sensor array 21 to the CCD shift register 24. Therefore, when the above operation is performed, the charge storage time of the sensor array 21 is determined by the first or second regulation time. FIG. 7 is a flowchart of the output circuit shown in FIG. As shown, the amplification degree Am set in step ST _2, to start charge accumulation of the sensor array 21, then, whether or not it is determined output signal Vm in step ST ₃ reaches a predetermined level, a predetermined when it reaches the Reberube set amplification degree As the process proceeds to step ST _6, the next step ST ₇
The − (Vos−Vmin) signal is amplified and A / D converted. Although the determination whether to distance measurement again after the ranging operation has been performed is performed in step ST _10, Vm in the case of distance measurement again
Step whether ax signal reaches the comparison voltage Vt ST ₁₁
If the comparison voltage Vt has been reached, the initial step ST
Returning to ₁ , high-speed extraction of unnecessary charges is performed.
An operational according to the above loop, and the flow proceeds from the level determination step of the output signal Vm returns to the step ST ₃ when it does not reach the comparison voltage Vt. The output signal Vm has not reached the predetermined level in step ST _3, the Vmax signal reaches the comparison voltage Vt, the amplification degree Am passes to step ST ₆ is again set according to the monitoring of the saturation charge accumulation, further , The output signal V
m is shifted from step ST ₅ is amplified degree Am reconfiguration similarly when not reached the predetermined level in step ST _6, then,
Amplification of the − (Vos−Vmin) signal and A / D conversion of the output signal Vs are performed. Next, FIG. 8 shows a time chart showing an example in which the charge accumulation start time of the sensor array 21 is variously changed and executed. In this figure, in phase Ph _1, the Vmax signal is the comparison voltage V
Here, an example is shown in which execution is performed as a result of reaching t, where Ti ₁ is the charge accumulation time, Ts ₁ is the signal extraction time of the CCD shift register 24,
Numeral ₁ indicates the data processing time. In this case amplification degree Am is reset to Am _1. Phase Ph ₂ shows an example in which charge accumulation is started immediately after the signal extraction time Ts ₁ ends, and Ti ₂ , Ts ₂ , and To ₂ similarly show charge accumulation time, signal extraction time, and arithmetic processing time . Phase Ph ₃ is an example in which charge accumulation is started immediately after the end of the signal extraction time Ts ₂ .In this case, since the Vmax signal reaches the comparison voltage Vt during the arithmetic processing time To ₂ , the time T
Fast charges between e sweep is performed, then, the charge storage time Ti ₄ phases Ph ₄ is started. In phase Ph _4, the output signal Vo = Vm value when shifting, is selected the amplification degree -As ₂ of Vos-Vmin. In phase Ph _5, after completion of the charge accumulation time Ti _4, an example in which to start the charge storage time Ti _5, arithmetic processing time To storage time Ti ₅ is completed in _4, immediately signal extraction entered the time Ts ₅ I have. The phase Ph ₆ is an example in which the charge accumulation time Ti ₆ becomes longer than the regulation time, and the shift signal Es is forcibly applied to execute the phase Ph ₆ . [Effects of the Invention] As described above, according to the present invention, the charge accumulation time is regulated according to the contrast of light incident on the image sensor, and the charge accumulation time of the image sensor is shortened if the contrast ratio is high. Control is performed so that the charge accumulation time becomes longer as the contrast ratio increases. Therefore, the average luminance distribution on the sensor array is monitored, and the S / N ratio is higher than that of a conventional sensor that regulates the charge accumulation time by detecting that the monitor voltage has reached a predetermined set voltage. Only a signal component necessary for distance measurement can be taken out, and the charge accumulation time control device of the image sensor which is very advantageous to use for focus detection of a camera or the like can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a control circuit of an image sensor showing an embodiment of the present invention implemented as a focus detection device for a camera, and FIG. 2 is a maximum photodetection circuit provided in the control circuit. And a circuit diagram showing a specific example of a minimum light detection circuit,
FIG. 3 is a block diagram showing a signal transfer state between the control circuit and the microcomputer, FIG. 4 is a time chart showing an operation of the control circuit, and FIG. 5 is a charge storage state of a sensor array included in the image sensor. FIG. 6 shows the image sensor.
FIG. 7 shows a video signal taken out of the CCD shift register, FIG. 7 is a flowchart of the control circuit,
FIG. 8 is a time chart showing an example in which the charge accumulation starting point of the sensor array is variously changed, and FIGS.
11 shows a conventional example, FIG. 9 is a block diagram of an image sensor, FIG. 10 is an operation waveform diagram of the image sensor, and FIG.
The figure shows the amount of charge stored in the sensor array. 21 Sensor array 24 CCD shift register 25 Drive control circuit 26 Maximum light detection circuit 27 Minimum light detection circuit 31, 35 Sample / hold circuit 32 Selector circuit 33 Differential Amplifier circuit 37 Comparison circuit 38 Shift pulse control circuit 39 Shift monitor circuit

Claims (1)

(57) [Claims] Of the light incident on the image sensor such as a CCD element, the detection signals of the maximum light detection circuit that electrically detects the strongest partial light and the minimum light detection circuit that electrically detects the weakest partial light are input. Then, a charge storage time control device for the image sensor, comprising a circuit for outputting these difference signals, and circuit means for regulating the charge storage time of the image sensor by the difference signal.