JP2664221B2 - Information playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information reproducing apparatus for reproducing information from an information recording medium such as an optical disk, and in particular, to information having different optical characteristics such as reflectance and modulation factor. The present invention relates to an information storage device suitable for reproducing information from a storage medium.

[Related Art] In an information reproducing apparatus for optically reading information written on an information storage carrier and reproducing the information, a reproduced signal detected by an optical head is amplified by an analog processing circuit.
After performing processing such as equalization, it is converted into a digital signal by a digitizing circuit such as a data slicer or an analog-to-digital converter. In these analog processing circuits and digitizing circuits, in order to reproduce information stably, the aging of optical components, the reflectance of the recording film,
The light amount of the light emitting unit is controlled according to the change of the modulation degree and the like.

For example, the technique described in Japanese Patent Application Laid-Open No. 62-217433 discloses that even when the modulation degree of the record carrier changes, the change in the amplitude of the RF signal or the like does not become larger than the change in the modulation degree. Also, even if the amount of light received by the detector changes due to a change in the optical system, the amount of light received by the detector on the mirror surface should be constant so that the tracking error signal, focus error signal, RF signal, etc. can be kept constant. In addition, the amount of light emitted from the laser diode is controlled.

[Problems to be Solved by the Invention] The above-mentioned conventional technique is used for reproducing information from an information storage carrier using a recording film on which a user can write information, such as a phase change film and a perpendicular magnetization film. No consideration was given.

That is, in the related art, the amount of emitted light is controlled in order to cope with fluctuations in the modulation degree and the like. In this case, when the amount of emitted light increases, the energy absorbed by the recording film increases, so that the temperature of the recording film increases. on the other hand,
When a signal is stored in the recordable information storage carrier having the above-described phase change film or perpendicular magnetization film as a recording film, the amount of emitted light is changed according to a signal to be written, and the temperature of the recording film is raised. Therefore, when reproducing information from the recordable information storage carrier using an apparatus using the conventional technique described above, if the light emission amount is increased to a certain level or more, the temperature of the recording film increases. This induces a phase transition or a reversal of magnetization, which causes a problem of writing an unintended signal or erroneously erasing a signal already recorded. Also,
The amount of light that can reproduce information without causing the above problems is
It depends on the substance used for the recording film. Therefore, it seems difficult to reproduce information from a recordable carrier with the information reproducing apparatus using the conventional technique described here.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, when the reflectance and modulation degree of an information storage carrier, the light quantity of a light source, and the like change, the amplitude of a signal input to a signal processing circuit and the DC power By controlling the position to be an optimal value, it is possible to provide an information reproducing apparatus that does not need to change the amount of emitted light even when the reflectance of the information storage carrier, the degree of modulation, the characteristics of the optical system, and the like change. is there.

[Means for Solving the Problems] The present invention provides the following means for solving the above problems.

The first means irradiates an optical disk on which a signal is recorded with a light beam, receives a signal light modulated according to the recorded information,
An information reproducing apparatus comprising: an optical head that converts a change in the signal light into a current signal; and a current-voltage conversion circuit that converts an output current signal of the optical head into a voltage signal. An offset control circuit that detects an output of itself and sets the offset detection signal as an offset detection signal, and performs offset control of a controlled signal based on an offset amount set from the offset detection signal and a reference value. A DC offset level of an output signal of the current-voltage conversion circuit is controlled.

The second means irradiates an optical disk on which a signal is recorded with a light beam, receives a signal light modulated according to the recorded information, and receives the signal light.
An information reproducing apparatus comprising: an optical head that converts a change in the signal light into a current signal; and a current-voltage conversion circuit that converts an output current signal of the optical head into a voltage signal. A gain control circuit for detecting the output of the signal itself to generate an amplitude detection signal, and performing gain control of a controlled signal by a gain control amount set from the amplitude detection signal and a reference value. The signal amplitude of the output signal of the current-voltage conversion circuit is controlled.

The third means irradiates a light beam on an optical disk on which a signal is recorded, receives a signal light modulated according to the recorded information,
An information reproducing apparatus comprising: an optical head that converts a change in the signal light into a current signal; and a current-voltage conversion circuit that converts an output current signal of the optical head into a voltage signal. A control circuit for detecting an output of the control signal to generate an amplitude detection signal, and performing gain control of a controlled signal based on a gain control amount set from the amplitude detection signal and a reference value; An offset control circuit that detects an output of the gain control circuit to generate an offset detection signal, and performs offset control of a controlled signal based on an offset amount set from the offset detection signal and a reference value. The offset control circuit uses the output signal of the current-voltage conversion circuit as a controlled signal of the offset control circuit, While controlling the DC offset level of the output signal, the output signal of the offset control circuit is used as a controlled signal of the gain control circuit, and the gain control circuit controls the amplitude of the output signal of the offset control circuit. It is characterized by the following.

The fourth means irradiates an optical disk on which a signal is recorded with a light beam, receives a signal light modulated in accordance with the recorded information,
An information reproducing apparatus comprising: an optical head that converts a change in the signal light into a current signal; and a current-voltage conversion circuit that converts an output current signal of the optical head into a voltage signal. An offset control circuit for detecting the output of itself and using the offset detection signal as an offset detection signal, and performing offset control of a controlled signal based on an offset amount set from the offset detection signal and a reference value; With the configuration, the output of the offset control circuit is detected as an amplitude detection signal,
A gain control circuit that performs gain control of a controlled signal by a gain control amount set from the amplitude detection signal and a reference value, wherein an output signal of the current-voltage conversion circuit is a controlled signal of the gain control circuit. The gain control circuit controls the signal amplitude of the output signal of the current-voltage conversion circuit, and the output signal of the gain control circuit is used as a controlled signal of the offset control circuit. The offset level of the output signal is controlled.

Fifth means is to irradiate an optical disk on which a signal is recorded with a light beam, receive a signal light modulated according to the recorded information,
An information reproducing apparatus comprising: an optical head that converts a change in the signal light into a current signal; and a current-voltage conversion circuit that converts an output current signal of the optical head into a voltage signal. An offset control circuit for detecting the output of itself and using the offset detection signal as an offset detection signal, and performing offset control of a controlled signal based on an offset amount set from the offset detection signal and a reference value; A gain control circuit that detects the output of itself and sets it as an amplitude detection signal, and performs gain control of a controlled signal by a gain control amount set from the amplitude detection signal and a reference value. Using the output signal of the current-voltage conversion circuit as a controlled signal of the offset control circuit, the offset control circuit While controlling the DC offset level of the force signal, the output signal of the offset control circuit is used as a controlled signal of the gain control circuit, and the gain control circuit controls the amplitude of the output signal of the offset control circuit. It is characterized by the following.

The sixth means irradiates an optical disk on which a signal is recorded with a light beam, receives a signal light modulated in accordance with the recorded information,
An information reproducing apparatus comprising: an optical head that converts a change in the signal light into a current signal; and a current-voltage conversion circuit that converts an output current signal of the optical head into a voltage signal. A gain control circuit for detecting the output of itself, forming an amplitude detection signal, and performing gain control of a controlled signal by a gain control amount set based on the amplitude detection signal and a reference value; And an offset control circuit that detects the output of itself as an offset detection signal and performs offset control of a controlled signal with an offset amount set from the offset detection signal and a reference value, An output signal of the current-voltage conversion circuit is output by the gain control circuit, using an output signal of the current-voltage conversion circuit as a controlled signal of the gain control circuit. The signal amplitude is controlled, and the offset level of the output signal of the gain control circuit is controlled by the offset control circuit using the output signal of the gain control circuit as a controlled signal of the offset control circuit. And

It is preferable that the offset control circuit, which is a component in each of the above means, receives a controlled signal, a timing signal, and an offset detection signal, and outputs a signal subjected to offset control. The offset control circuit preferably compares the level of the offset detection signal at a specific timing determined by the timing signal with a reference value, and generates an offset control signal that determines an offset amount corresponding to the comparison result. And an offset adding circuit that adds the offset amount determined by the offset control signal to the controlled signal and outputs an offset-controlled signal.

For example, the offset control signal generation circuit sequentially performs offsets from a maximum or minimum offset to an optimum offset in order so that the level of the offset detection signal at a specific timing determined by the timing signal matches the level of the reference value. May be configured to generate an offset control signal for adjusting

Further, the offset control signal generation circuit can be constituted by a digital circuit. In other words, this digital offset control signal generation circuit uses the plurality of bits of the offset control signal so that the level of the offset detection signal at a specific timing determined by the timing signal matches the level of the reference value. An offset control signal for adjusting the offset by sequentially setting / resetting each bit up to the least significant bit can be configured.

The offset addition circuit may include a high-pass filter that blocks a DC component of the controlled signal, and the offset level of the output may not depend on the offset level of the controlled signal.

It is preferable that the gain control circuit, which is a component in each of the above means, receives a controlled signal, a timing signal, and an amplitude detection signal, and outputs a signal whose amplitude is controlled. The gain control circuit preferably compares the amplitude level, which is a level difference between the amplitude detection signals at two or more specific timings determined by the two timing signals, with a reference value, and calculates a gain control amount corresponding to the comparison result. A gain control signal generating circuit for generating a predetermined gain control signal; and a gain switching circuit for outputting an amplitude-controlled signal by amplifying the controlled signal in accordance with a gain control amount determined by the gain control signal. Be composed.

For example, the gain control signal generation circuit may be configured so that the amplitude level, which is the difference between the levels of the amplitude detection signals at two or more specific timings determined by the two timing signals, matches the amplitude level of the reference value. The configuration may be such that a gain control signal for sequentially adjusting the gain from the minimum gain to the optimum gain is generated.

As the timing signal, it is preferable to use a signal indicating that a signal is being reproduced from a specific area other than the area for recording information in the information storage format set on the information storage medium. This timing signal is used as a timing signal input to an offset control signal generation circuit, and as two timing signals input to a gain control signal generation circuit, for example, in an information storage format set on an information storage medium. The signal indicating that a signal is generated from a specific area where the level of the output signal of the current-voltage conversion circuit is maximum or minimum in an area other than the area in which is recorded.

The format of the information storage medium defines an area for storing information corresponding to a specific position on the information storage medium. For example, there is a format such as an optical disk.

[Operation] According to the present invention, the amplitude and the DC potential level of a signal input to an information processing circuit for reproducing recorded information are determined by determining the reflectance and modulation degree of an information storage carrier, the light amount of a light source, and the like. The above object is achieved by controlling the signal amplitude and the DC potential level so as to fall within a predetermined range even when the voltage changes. That is, the offset control circuit and / or the gain control circuit detects the amplitude and / or the DC potential level of the signal input to the information processing circuit, compares each detected value with a reference value, and, according to the comparison result,
Control the signal amplitude and / or DC potential level.

When the amplitude of the reproduction signal input to the signal processing circuit is larger than the reference value, the gain control circuit lowers the gain so that the amplitude of the output signal of the signal processing circuit always has a constant magnitude. If the amplitude of the reproduced signal is smaller than the reference value, the gain is increased. Similarly,
The offset control circuit lowers the DC potential level of the output when the DC potential level is higher than the DC potential level reference value of the reproduction signal,
If the DC potential level of the reproduction signal is lower than the reference value, the DC potential level of the output is increased. Therefore, even if the characteristics of the information recording carrier, the optical system, and the like change, the optimum signal is always given to the information processing circuit to which the signal controlled by the signal control circuit is input, so that the error rate increases. Can be prevented from deteriorating.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

In the figure, 1 is an optical disk, 2 is an optical head, 3 is a current-voltage conversion circuit (hereinafter abbreviated as an IV conversion circuit), 4 is a gain control circuit, 5 is an offset control circuit, and 6 is a signal processing circuit. , 7 is a pit detection signal, 8 is an error portion detection signal, and 9 is a reproduction signal.

A light beam emitted from a light emitting section (not shown) of the optical head 2 converges on a recording film of a target track of the optical disc 1 by an operation of a focus servo system and a tracking servo system (both are not shown). Then, the recording signal is modulated and reflected on the recording film, and then enters the optical head 2 again. The light incident on the optical head 2 is converted into a current proportional to a signal by a photoelectric conversion element of a light receiving unit (not shown) inside the optical head 2 and output from the optical head 2 as an electric signal. The current signal from the optical head 2 is I-
The signal is converted into a voltage signal by the V conversion circuit 3 and applied to the gain control circuit 4 as a reproduction signal. Gain control circuit 4
Detects the amplitude of the reproduced signal and controls the gain so that the amplitude is sufficiently close to the amplitude value of the reference value, so that the amplitude of the output of the gain control circuit 4 is always substantially constant. Here, the gain control circuit 4 will be described.

FIG. 2 shows a more detailed block diagram of the gain control circuit 4 of the present invention.

In the figure, a gain switching circuit 21 is a circuit that can change its gain by a gain control signal 24 output from a gain control signal generation circuit 22,
The reproduction signal 9 from the IV conversion circuit 3 is input.
The gain control signal generation circuit 22 detects a level difference between the two signals at a specific timing of the level difference detection signal 23 (hereinafter, simply referred to as a level difference), and calculates a difference between the detected level difference and a reference level difference. When the comparison is performed and the detected level difference is larger than the reference level difference, a gain control signal 24 for lowering the gain of the gain switching circuit 21 is generated. Conversely, the detected level difference is larger than the reference level difference. When the value is also smaller, the circuit generates a gain control signal 24 for increasing the gain of the gain switching circuit 21.
The gain control circuit 4 includes, as input signals, a level difference detection signal 23 output from the offset control circuit 5 for obtaining a level difference, a pit detection signal 7 (described later) as the two timing signals, and a mirror. Part detection signal 8
(Described later) are added.

 Here, the gain switching circuit 21 will be described.

 FIG. 3 shows an embodiment of the gain switching circuit 21.

In the figure, switches S1 to Sn-1 are analog switches, and 31 is an operational amplifier.

Each of the switches S1 to Sn-1 can be controlled by the gain control signal 24 so that only one switch S is closed and the other switches S are open. At this time, when only the switch S2 is closed as shown in FIG. 3, for example, the gain G of the gain switching circuit 21 is equal to the resistance R between the closed switch 2 and the output terminal of the operational amplifier 31. (= R1 + R2) and the resistance R ″ (= R3 + R4 +... Rn) between the switch S2 and the ground, G = (R ′ +
R ") / R". Therefore, the gain control signal 24
The gain G of this circuit can be changed by changing the switches R 'and R "by switching the close switch.

 Next, the gain control signal generation circuit 22 will be described.

FIG. 4 shows an embodiment of the gain switching signal generation circuit 22.

In the figure, the Vm detection circuit 41 and the Vp detection circuit 42
These are circuits for detecting and holding the signal voltage Vm of the mirror section and the signal voltage Vp of the pit, respectively, and both are composed of sample and hold circuits. Mirror detection signal 8 and pit detection signal 7 are input as signals for controlling the sample and hold operations, respectively. For example, when the detection signal is at a "high (H)" level, the sampled voltage level is held. To detect.

The differential amplifier 45 amplifies the difference between the output signal Vm of the Vm detection circuit 41 and the output Vp of the Vp detection circuit 42. Gain
If kg, the output voltage Vs of the differential amplifier 45 is expressed as Vs = kg (Vm-Vp). Comparators 46a and 46b are connected to reference voltages Vr1 and Vr2, respectively.
Is compared with the output voltage Vs of the differential amplifier 45, and a digital signal corresponding to the result is output. In the case of the present embodiment, the logical level of the output of the comparator 46a becomes “H” level when Vs is higher than Vr1, and
The logic level of the output of b becomes Vs smaller than Vr2,
It becomes the “low (L)” level. AND circuit 47a, 47b
Performs an AND operation between the output signals of the comparators 46a and 46b and the count pulse 48, respectively.
The output goes high only when both inputs a and 47b go high. The count pulse generation circuit 49
A delay circuit for delaying the pit detection signal 7 for a predetermined time to generate a count pulse 48. The sample and hold circuits of the Vm detection circuit 41 and the Vp detection circuit 42 sample the mirror section detection signal 8 and the pit detection signal 7. After that, the time required for the operation by the differential amplifier 45 and the comparison by the comparator 46 and the pit detection signal 7 are delayed, and the logical operation by the AND circuit 47 is performed after the comparator output 46 becomes sufficiently stable. .

The up / down counter 410 is a digital counter that can increase or decrease the count value by the output pulse of the AND circuit 47. In this embodiment, the up-down counter 410 is configured such that the signal level from the AND circuit 47a becomes “H” level, the count value decreases when a signal is input to the D terminal, and the level of the signal from the AND circuit 47b. Is “H”
When the level is reached and a signal is input to the U terminal, the count value increases.

The decoder 411 decodes the output of the up / down counter 410 and generates a gain control signal 24 for controlling the opening and closing of the switch of the gain switching circuit 21. The decoder 411 increases the gain of the gain switching circuit 21 when the value counted by the up / down counter 410 is larger than the reference value, and decreases the gain when the count value is smaller than the reference value. Gain control signal
24 is output to control the amplitude of the output signal of the gain switching circuit 21.

Since the gain switching circuit 21 and the gain control signal generating circuit 22 performing the above-described operations are connected to form a feedback control system, the amplitude of the output signal of the gain control circuit 4 is set to a predetermined reference level. Is controlled so as to be substantially equal to the amplitude. Thus, the gain control circuit 4 controls the amplitude of the output signal of the IV conversion circuit 3.

Next, the offset control circuit 5 will be described. The offset control circuit 5 detects the DC offset level of the signal at a specific timing of the input signal, controls the offset level so that this level is sufficiently close to the reference offset level, and adjusts the offset level of the output of the offset control circuit 5. Always be almost constant.

FIG. 5 shows a more detailed block diagram of the offset control circuit 5 of the present invention.

The offset control circuit 5 detects the offset level of the offset level detection signal 54 and controls the offset level so that the offset level is sufficiently close to the reference offset level value. Make it a fixed size. The offset addition circuit 51 is a circuit that can change the offset level of the output by the offset control signal 53 output from the offset control signal generation circuit 52, and receives the signal from the gain control circuit 4. The offset control signal generation circuit 52 outputs an offset level detection signal.
Detects the offset level (hereinafter simply referred to as offset level) of the signal at a specific timing of 54, compares the detected offset level with the reference offset level, and detects that the detected offset level is higher than the reference offset level. When the offset level is larger, an offset control signal 53 for lowering the offset level of the output of the offset adding circuit 51 is generated. Conversely, when the detected offset level is smaller than the reference offset level, the offset level of the output of the offset adding circuit 51 is raised. It is a circuit that generates such an offset control signal 53. In the offset control signal generation circuit 52, an output of the offset addition circuit 51 is added as an offset level detection signal 54 as an input signal, and a mirror section detection signal 8 (described later) is added as a timing signal.

Here, the offset adding circuit 51 will be described. FIG. 6 shows an embodiment of the offset addition circuit 51.

An operational amplifier (hereinafter abbreviated as an operational amplifier) 61 has a non-inverting input terminal to which the output signal of the gain control circuit 4 is applied,
Further, an offset control signal 53 from an offset control signal generation circuit 52 is applied to the inverting input terminal. In this offset adding circuit 51, the offset level of the output signal
Vo is given by Vo = ko (Vi−Voff) (1) where Vi is the output of the gain control circuit 4, Voff is the voltage of the offset control signal 53, and ko is the gain of the operational amplifier 61. Therefore, the offset level Vo can be controlled by changing the voltage Voff of the offset control circuit 53.

Next, the offset control signal generation circuit 52 will be described. FIG. 7 shows an embodiment of the offset control signal generation circuit 52.

The Vm 'detection circuit 71 is a circuit for detecting and holding the signal voltage Vm' of the mirror unit, and is composed of a sample and hold circuit. The mirror section detection signal 8 is input as a signal for controlling the sample and hold operation. For example, when the detection signal is at the “H” level, the offset addition circuit of the offset addition circuit added as the offset level detection signal is used. The output voltage is sampled. When the output voltage is at "L" level, the sampled voltage level is held and output.

The low-pass filter 73 smoothes the output of the sample-and-hold circuit, and removes high-frequency components higher than the frequency of the sample so that the component of the sample frequency appears in the output of the offset addition circuit and does not become noise. belongs to.

The operational amplifier 74 amplifies the difference between the output signal Vm 'of the Vm' detection circuit 71 and the reference offset level voltage Vref. Here, assuming that the gain of the differential amplifier 74 is K, the output voltage Vs' of the operational amplifier 74 (that is, the offset control signal Voff) is as follows: Vs = K (Vm'-Vref) (2)

Offset addition circuit 51 and offset control signal generation circuit
Numeral 52 forms a feedback control system, and when the system is operating stably, the output voltage Vo of the offset addition circuit 51 is calculated from the equations (1) and (2) as Vo = ｛ko / (1 + koK). ｝ × Vi + {koK / (1 + koK)} × Vref (3) Therefore, when K >> 1 and ko ≒ 1, Vo ≒ (1 / K) Vi + Vref (4), and the variation ΔVi of the offset level of the input signal Vi is
Is suppressed to (1 / K) ΔVi at the output. Therefore,
The offset level of the output signal Vo of the offset control circuit 5 becomes substantially equal to the reference voltage Vref.

Thus, the offset control circuit 5 controls the offset level of the output signal of the gain control circuit 4. As a result, the output of the offset level control circuit 5 becomes
The amplitude and the offset level are controlled so as to be almost constant.

Next, a method of detecting a mirror portion and a pit portion in the signal processing circuit 6 will be described.

Generally, there are many optical disks on which a unique pattern is formed in advance in order to synchronize with data to be recorded / reproduced. The peculiar pattern is a pattern that appears only at a specific position on the disc and does not exist in the area where information is recorded. If the mirror portion and the pit are at a fixed position from this pattern, a signal indicating the position of the mirror portion and the pit by a device that generates a pulse after a certain period of time after the detection of the peculiar pattern, that is, a detection signal of the mirror portion and A pit detection signal is obtained. As an example, a detection method for an optical disk having a format called a sampled format will be described with reference to FIG.

In FIG. 14, a sampled format optical disk has a servo area 10 composed of servo pits 12 formed periodically, and a portion sandwiched between the servo areas 10 is a data area 11 used for recording and reproducing information. ). In this format, the arrangement of the servo pits 12 in the servo area 10 forms a peculiar pattern, and the interval between the peaks of the reproduced signal obtained during reproduction of the optical disk is T0 in the servo area 10. There is no other Servo area 10
Since it appears at a fixed cycle, after detecting the above T0, T1
When the time elapses, the gap between the servo pits 12 in the next servo area 10, that is, the mirror section 14 always appears.

The pit detection uses a unique pattern formed in advance similarly to the detection of the mirror unit 14. If the pit is located at a fixed position from the peculiar pattern, a pit detection signal is obtained by a device that generates a pulse after a certain period of time after the detection of the pattern. That is, the pits of the next servo area 10 always appear after T2 after detecting T0. Therefore, the mirror section detection signal 8 and the pit detection signal 7 are obtained by the circuit having the configuration as shown in FIG.

The circuit having the configuration shown in FIG. 15 includes a peak detection circuit 71, T0
It comprises a detection circuit 72, a T1 delay pulse generation circuit 73, and a T2 delay pulse generation circuit 74. The peak detection circuit 71 generates a pulse for each peak of the reproduction signal. By measuring the interval between the pulses, the T0 detection circuit 72 allows the peak-to-peak
A trigger pulse is generated at T0. The T1 delay pulse generation circuit 73 generates a pit detection signal T1 after the trigger pulse output from the T0 detection circuit 72. This is a signal indicating the timing of the mirror section (mirror section detection signal 8). The T2 delay pulse generation circuit 74 generates a pit detection signal T2 after the trigger pulse output from the T0 detection circuit 72. This is a signal indicating the pit timing (pit detection signal 7).

The pulse width of the pit detection signal is equal to or smaller than the pit width. Further, the width of the pulse of the mirror unit 14 detection signal is equal to or smaller than the width of the mirror unit 14, and is equal to or less than T0 in the present example.

The mirror section 14 and the T0 detection circuit 72 of the pit detection circuit and the T1 delay pulse generation circuit 73 shown in FIG. 15 can be constituted by a logic circuit, so that they can be easily integrated or integrated into a part of the integrated circuit. is there.

By the operation described above, the signal input to the signal processing circuit 6 does not change significantly even if the optical characteristics of the optical disk 1 and the characteristics of the optical head 2 change, and the error rate increases due to the signal fluctuation. Can be prevented from deteriorating.

Next, a second embodiment of the present invention will be described. This embodiment is the same as the first embodiment except for the gain control circuit. Therefore, only different points from the first embodiment will be described, and the description of the same parts as the first embodiment will be omitted.

8 and 9 show an embodiment of the gain switching circuit 21 and the gain control signal generation circuit 22 of the gain control circuit 4 in the present embodiment, respectively.

First, the gain switching circuit 21b will be described. The gain switching circuit 21b shown in FIG. 8 includes a voltage control amplifier 81 that can change the gain kg by the voltage Vc applied to the control terminal 82. In the case of the present embodiment, the control terminal voltage Vc is high. If the gain kg is large,
Further, the amplifier is such that the gain kg becomes small when the control terminal voltage Vc is low.

Next, the gain control signal generation circuit 22b will be described. The gain control signal generation circuit 22b shown in FIG. 9 is the same as the gain control signal generation circuit 22 except that a digital-to-analog converter (hereinafter abbreviated as DAC) 911 is different from the decoder 411 in the first embodiment. Therefore, only the differences from the first embodiment will be described,
A description of the same parts as in the first embodiment will be omitted.

The DAC 911 converts information relating to gain control, which is output as digitized numerical data from the up / down counter 410, into a voltage, and outputs the gain control signal 24 as voltage level information. In the case of this embodiment, the output voltage of the DAC 911 increases as the value counted by the up / down counter 410 increases, and conversely, the DAC 91 decreases as the value counted by the up / down counter 410 decreases.
The voltage of the gain control signal 24, which is the output of 1, becomes low. Therefore, the gain of the voltage control amplifier 81 increases as the count value of the up / down counter 410 increases, and decreases when the count value is low, and thus operates in the same manner as in the first embodiment.

Next, a third embodiment of the present invention will be described. This embodiment is the same as the first embodiment except for the offset addition circuit, and therefore, only the points different from the first embodiment will be described, and the description of the same parts as the first embodiment will be omitted.

FIG. 10 shows an embodiment of the offset adding circuit 51b in the present embodiment. The difference between the present embodiment and the first embodiment is that a DC blocking capacitor C1 is newly added in order to block the DC component of the signal from the gain control circuit 4.

In this embodiment, since the DC component of the signal applied to the inverting input terminal of the operational amplifier 101 is blocked by the DC blocking capacitor C1, even if the offset voltage of the output of the gain control circuit 4 changes, the operational amplifier 101 The DC component of the signal applied to the inverting input terminal is always zero. Therefore, the offset voltage Vo at the output of the offset adding circuit 51b is determined only by the offset control signal. Therefore,
The offset control signal does not need to be changed according to the offset fluctuation of the input signal, so that the offset control signal has a constant voltage. Therefore, in this embodiment, the offset control signal generation circuit 52 has a feature that a constant voltage power supply can be used, and the circuit configuration can be simplified.

Next, a fourth embodiment of the present invention will be described. This embodiment is the same as the first embodiment except for the gain control signal generation circuit. Therefore, only the differences from the first embodiment will be described, and the description of the same parts as the first embodiment will be omitted. .

FIG. 11 shows a gain control signal generating circuit 22 according to this embodiment.
It is an example of c. Here, the gain control signal generation circuit 2
2c will be described. The gain control signal generation circuit 22c is the same as the gain control signal generation circuit 22 except that it is different from the Vm detection circuit 41 and the Vp detection circuit 42 and that a reset pulse generation circuit 114 is added. First
Only the differences from the first embodiment will be described, and the description of the same parts as the first embodiment will be omitted.

The maximum value hold circuit of the Vm detection circuit 111 and the minimum value hold circuit of the Vp detection circuit 112 output the maximum value and the minimum value of the input signal after the reset pulse 113 is released. Also, the reset pulse generation circuit 114
Generates a reset pulse a predetermined time after the count is performed by the count pulse. Therefore,
Even if the maximum value hold circuit and the minimum value hold circuit are used as the Vm detection circuit 111 and the Vp detection circuit 112, the maximum value and the minimum value of the level difference detection signal are detected, and the level difference is detected from the difference between the detected values. be able to. Therefore, also in this embodiment, a level difference is detected as in the first embodiment, and the gain is controlled accordingly.

Next, a fifth embodiment of the present invention will be described. In the present embodiment, since the configuration other than the level difference detection signal input to the gain control signal generation circuit and the gain of the offset addition circuit is the same as that of the first embodiment, only the differences from the first embodiment will be described. And the description of the same parts as in the first embodiment is omitted.

 FIG. 12 is a block diagram showing the configuration of this embodiment.

In this embodiment, the level difference detection signal 23 input to the gain control signal generation circuit (not shown) included in the gain control circuit 4b is a gain switching circuit included in the gain control circuit 4b. (Not shown). The difference from the first embodiment is that the gain ko of the offset addition circuit 51 must be a stable and constant value. That is, in the first embodiment, the gain control signal generation circuit 22 is
Since the level difference was detected from the signal having passed through the offset control circuit 5 and the offset control circuit 5, the gain ko of the offset control circuit may be an arbitrary value, and even if the gain ko fluctuates,
Since the variation is suppressed by the operation of the gain control circuit 4, the amplitude of the signal input to the signal processing circuit 6 becomes substantially constant. On the other hand, in the present embodiment, since the fluctuation of the gain ko of the offset control circuit 5b cannot be suppressed,
The gain ko of the offset control circuit 5b must be stable. However, in the present embodiment, since the gain control circuit 4b and the offset control circuit 5b can be separated, there is a feature that control can be performed more stably without interference between both feedback control systems. .

In the present embodiment, it is apparent that even if the order of the gain control circuit and the offset control circuit is changed, there is no problem in controlling the gain and the offset which is the original purpose.

Next, a sixth embodiment of the present invention will be described. The actual embodiment is the same as the first embodiment except for the order of the gain control circuit and the offset control circuit. Therefore, only different points from the first embodiment will be described, and the same parts as the first embodiment will be described. Is omitted.

 FIG. 13 is a block diagram showing the configuration of the present invention.

The gain control circuit 4c needs to change the gain kg over a relatively wide range in order to suppress the fluctuation of the amplitude of the input signal. As shown in FIGS. 1 and 2, in the first embodiment, since the reproduction signal 9 is directly input to the gain control circuit 4, the gain switching is performed depending on the offset level of the reproduction signal 9 and the value of the gain kg. The output range of the operational amplifier of the circuit 21 may be exceeded, and the amplitude control may become unstable. On the other hand, in the present embodiment, the reproduction signal 9
Is input to the offset control circuit 5c before being input to the gain control circuit 4c, so that the offset level of the signal input to the gain control circuit 4c is controlled to be substantially constant. Therefore, the present embodiment has a feature that the above problem can be prevented from occurring.

In each of the embodiments described above, the gain control circuit and the offset control circuit are all provided. If any one of the gain control circuit and the offset control circuit is unnecessary, the unnecessary part is deleted. It is clear that the gain control circuit or the offset control circuit may be used alone.

Next, a case where the present invention is implemented using a microprocessor will be described.

Hereinafter, the seventh embodiment will be described with reference to FIG. FIG. 16 is a block diagram of an embodiment of the offset control circuit 5 using a microprocessor (MPU) 60.

The D / A (digital / analog) converter 61 supplies a voltage corresponding to the data set by the MPU 60 to the offset adding circuit 51 as an offset voltage. The offset addition circuit 51
The offset control circuit 5 outputs a voltage obtained by adding an offset voltage to a reproduction signal, which is one of the inputs. The output is the output of the offset control circuit 5. The output of the offset addition circuit 51 is also input to an A / D (analog-digital) converter 62. The A / D converter 62 receives a mirror part detection signal 8 which is another input of the offset control circuit 5.
Is used as a timing signal to convert the voltage level of the mirror portion of the reproduction signal to which the offset has been added into digital data,
Send to MPU60.

The MPU 60 sets the data in the D / A converter 61 so that the output data of the A / D converter 62 matches the reference value or has a sufficiently close value. Note that the reference value is a value obtained by converting the voltage level of the mirror portion of the reproduction signal into digital data when an appropriate offset voltage is applied. The reference value is within the conversion value range of the A / D converter 62 and does not include the maximum value and the minimum value of the value range.

The components of this embodiment will be further supplementarily described.

The D / A converter 61 generates a voltage corresponding to a digital data signal, such as a PWM (pulse width modulation) circuit, and can be replaced. The A / D converter 62 converts a voltage level of an input signal of a comparator circuit or the like into a digital data signal, and can be replaced. The MPU 60 does not need to be dedicated to the offset control circuit 5 and can be shared with the control microprocessor of the optical disk device. This MPU60
ROM (read only memory), RAM, I / O (input / output)
Even if it is composed of a multi-chip processor with an external port, or ROM, RAM (random access memory),
Built-in I / O port, A / D converter 62, D / A converter 61
There is no essential difference from the configuration shown in this embodiment even if a device incorporating either or both of them is used.

An example of the offset voltage setting procedure in the present embodiment
This will be described with reference to FIG.

In this procedure, the resolution of the D / A converter 61 and the A / D converter 62 is set to 8-bit precision, and the optimum value is obtained by using the bisection method.

That is, “1” is sequentially assigned from the most significant bit of the D / A converter 61.
In each case, the voltage level of the mirror portion of the reproduced signal after the addition of the offset voltage is compared with the reference value, and it is determined whether the offset voltage is too large or too small.
If the value is too small, the value is kept at "1" and fine adjustment is gradually performed while trying the least significant bit. The data set in the D / A converter 61 and the offset voltage of the output are directly proportional, and when data = 0, the minimum, data = ＄
When FF (hexadecimal), the maximum offset voltage is output. Similarly, in the A / D converter 62, when the voltage level of the mirror portion of the reproduction signal to which the offset voltage is added is high, the data is large, and when the voltage level is small, the data is small. A / D converter 62
Has a finite input range, but outputs 最大 FF (hexadecimal), which is the maximum value when the input exceeds the range, and outputs 0, which is the minimum value when the input falls below the range. Therefore, the reference value takes a value greater than 0 and less than $ FF (hexadecimal). If the reference value is set to 0, the output of the A / D converter 62 becomes 0 even when the offset voltage is too small, so that it cannot be determined. For the same reason, reference value = $ FF (hexadecimal) cannot be used.

In FIG. 19, first, in step S1, the register inside the MPU 60 is set to $ 80 (hexadecimal number) and 0 is set to the D / A converter 61.

In step S2, a value obtained by adding the value of the register and the data set in the D / A converter 61 is set in the D / A converter 61. In step S3, the process waits until the A / D converter 62 converts the voltage of the mirror portion of the reproduction signal to which the new offset voltage has been added into data.

In step S4, the data output from the A / D converter 62 is compared with the reference value. If the data is larger than the reference value, the process proceeds to step S5, and if it is smaller than the reference value, the process proceeds to step S9.

When the data output from the A / D converter 62 is larger than the reference value, in step S5, the value of the register added in S2 is subtracted from the data set in the D / A converter 61, and the D / A
Reset the converter 61. Next, the value of the register is checked in step S6. If the value is not 0, the process proceeds to step S7, shifts the value of the register by one bit to the right, and returns to step S2. Each time through step S7, the value of the register is divided into two, And change.

On the other hand, if the register is 0 in S6, the process proceeds to step S8
To check the value set in the D / A converter 61,
In this case, the process ends abnormally as “error 2”. in this case,
Since the output of the A / D converter 62 exceeds the reference value even though the minimum offset voltage is applied from the D / A converter 61, the message “Offset control is disabled (because the input signal is too large)” Possible ".

If the set value of the D / A converter 61 is other than 0 in step S8, the process ends normally. The process proceeds from step S6 to step S8 when the register = 0, that is, when the offset voltage adjustment with the minimum resolution is completed, and the offset voltage of at least the minimum value or more is added from the D / A converter 61. Since the set value is not 0 (set value is not 0), it is determined that the value is within the offset control range, and therefore exceeds the reference value due to an error at a resolution lower than the resolution of the D / A converter 61.

If the output of the A / D converter 62 is equal to or smaller than the reference value in step S4, the process proceeds to step S9. In step S9, the value is compared again with the reference value, and if the values match, the process ends normally. When they do not match, that is, when the value of the A / D converter 62 is smaller than the reference value, the process proceeds to step S10. When the value of the register is 0 in step S10, the process proceeds to step S11, and the set value of the D / A converter 61 is checked. Here, if it is $ FF (hexadecimal number), the process ends abnormally as error 1. In this case, although the maximum offset voltage is applied, the data of the A / D converter 62 becomes equal to or less than the reference value, so that it is determined that the offset control is impossible (because the input signal is too small). Step S1
If the set value of the D / A converter 61 is other than $ FF (hexadecimal number) at 1, the process ends normally for the same reason as described above in step S8.

Here, if the reference value in step S4 is changed to the reference value + α and the reference value in step S9 is changed to the reference value -α, an allowable range of ± α can be provided.

According to this procedure, the offset control with the minimum resolution that can be set is performed as quickly as possible.

According to the present embodiment, since it is possible to determine whether the offset control is possible or not, it is possible to detect an abnormality of the optical disc 1 or the reproducing system, and to improve the safety and maintainability.

Next, an eighth embodiment of the present invention will be described with reference to FIG.
In this embodiment, the A / D converter 62 in the seventh embodiment is replaced by a high-speed A / D converter 63 shared with other circuits.

The high-speed A / D converter 63 converts the voltage level of the reproduced signal to which the offset voltage output from the offset control circuit 5 has been added into data at a sufficiently fast cycle of the clock φ. The output of the high-speed A / D converter 63 is input to the signal processing circuit 6,
The data is distributed to each processing circuit in the signal processing circuit 6 via the data bus. The data bus also connects to a latch circuit 64. The latch circuit 64 receives the data on the data bus with the mirror section detection signal 8, that is, the data of the voltage level of the mirror section of the reproduction signal to which the offset voltage has been added. The latch circuit 64 sends the captured data to the MPU 60.

In this embodiment, data obtained by the MPU 60 from the latch circuit 64 is equivalent to data obtained from the A / D converter 62 in the seventh embodiment. Therefore, in the procedure shown in FIG. 19, the data obtained from the A / D
, The offset voltage can be controlled.

According to the present embodiment, since it can be shared with other circuits of the A / D converter 62, there is an effect of cost reduction. Further, if the signal processing circuit 6 is formed of a logic circuit, the effect of miniaturization can be obtained by forming the latch circuit 64 as a part of the signal processing circuit 6 and forming an integrated circuit.

A ninth embodiment of the present invention will be described with reference to FIG. In this embodiment, the optimum offset voltage is determined by using the data of the maximum voltage level of the reproduced signal instead of the data of the voltage level of the mirror portion of the reproduced signal in the eighth embodiment.

20, components other than the maximum data detection circuit 65 are the same as those shown in FIG. 17 described in the eighth embodiment. The maximum data detection circuit 65 sequentially compares the data output from the high-speed A / D converter 63 with the value held therein, and if the new data is larger than the previous one, the value held inside Has a function of updating to new data.
The value held inside the maximum data detection circuit 65 is
Is read to a sufficiently small value (for example, 0).

The purpose of the offset control is to supply a signal controlled to an appropriate level to a circuit connected to the subsequent stage of the offset control circuit 5, so that the maximum value of the signal is set higher than the upper limit of the input range of the subsequent circuit. The goal can be achieved by controlling it low. Therefore, in this configuration, MPU6
By treating the data obtained from the maximum data detection circuit 65 of 0 as equivalent to the data obtained from the A / D converter 62 in the seventh embodiment, the offset voltage can be controlled by the procedure shown in FIG.

Note that the maximum data detection circuit 65 can be realized by software. In that case, as shown in FIG. 21,
The circuit configuration is such that the output of the high-speed A / D converter 63 can be read directly from the MPU 60. An example of a process for obtaining the maximum value of the voltage level of the reproduced signal to which the offset voltage has been added will be described with reference to FIG. In this example, the data of the high-speed A / D converter 63 is inspected N times, and the largest one is stored in the variable D.

First, in step S19, the number of inspections N is substituted for a variable I which is a counter for counting the number of inspections, and in step S20, a variable D holding the maximum data is initialized to 0, which is the minimum value of the data.

In step S21, a variable I which is a counter is checked,
If it is 0, the process is terminated; if it is other than 0, step S22
Proceed to.

In step S22, the data of the high-speed A / D converter 63 and the variable D
If the data of the high-speed A / D converter 63 is larger than the variable D, the process proceeds to step S23, and the value of the variable D is changed to the high-speed A / D
The value is updated to the value of converter 63, and the process proceeds to step S24. Step S
At 22, if the data of the high-speed A / D converter 63 is smaller than the variable D, the process directly proceeds to step S 24.

In step S24, the variable I which is a counter is decremented by 1, and the process returns to step S21.

This processing is replaced with step S3 in FIG.
The value of the variable D may be used instead of the voltage level of the mirror portion of the reproduction signal.

According to the present embodiment, since the maximum level of the signal can be controlled, it can be used also for a signal whose mirror cannot be detected or a signal having a signal larger than that of the mirror, and has an effect of improving operation stability.

A tenth embodiment will be described with reference to FIGS. 18, 23, and 24. In the present embodiment, the offset voltage is adjusted while performing the pull-in operation for focusing.

FIG. 18 is a block diagram of the offset control circuit 5 in the present embodiment.

D / A converter 61, A / D converter 62, offset addition circuit 51,
The relationship between them and the MPU 60 is the same as in the seventh embodiment. That is, the setting value of the D / A converter 61 is changed by the MPU 60 so that the data obtained by converting the voltage level of the mirror portion of the reproduction signal to which the offset voltage has been added by the A / D converter 62 matches the reference value. Configuration. Therefore, in addition to the configuration shown in FIG. 18, the present invention can be realized with the configurations of the seventh, eighth, and ninth embodiments described above, and other similar configurations.
In this embodiment, the configuration in the seventh embodiment is used as a representative. The MPU 60 further outputs a sweep operation control signal SWEEP for moving the focus position of the light beam to focus on the optical disk 1 and inputs a FOCUS signal for detecting that the optical disk 1 is in focus.

The outline of the operation of this embodiment will be described with reference to FIG.

By gradually bringing the focus position closer to the recording film surface of the optical disc 1, the level of the reproduction signal obtained from the reflected light increases. The level of the reproduction signal becomes maximum when the focus position coincides with the recording film surface of the optical disc 1. Therefore, it is possible to control the offset voltage by repeating the steps of giving the maximum offset in advance, checking the level of the reproduction signal which gradually increases in this way, and lowering the offset voltage when the level exceeds the reference value.

 An example of the control procedure will be described with reference to FIG.

First, in step S12, the initial value ＄ FF (16
Base number), that is, the maximum offset voltage, and the movement of the focus position is started in step S13. It is assumed that the in-focus position is at a position away from the recording film surface of the optical disc 1 before the movement starts in step S13, and gradually approaches and coincides with the movement.

In step S14, the process waits until the A / D converter 62 converts the voltage level of the mirror portion of the reproduction signal to which the offset voltage has been added into data.

In step S15, the output data of the A / D converter 62 is compared with a reference value. If the output data is larger than the reference value, the process proceeds to step S16. In step S16, the value set in the D / A converter 61 is checked. That is, despite the application of the minimum offset voltage, the level of the mirror portion of the reproduction signal exceeds an appropriate value, and the offset control is impossible (because the input signal is excessive).
Abnormally ends. If the set value of the D / A converter 61 is other than 0 in step S16, the set value of the D / converter 61 is reduced by 1 in step S17, and the process returns to step S14.

On the other hand, in step S15, if the output data of the A / D converter 62 is equal to or less than the reference value, the process proceeds to step S18, where the FOCUS signal is inspected, and if the focus is on the recording film surface of the optical disc 1, the processing is performed. If it ends normally and is not focused, step
Return to S14.

After the process shown in FIG. 23, if the output data of the A / D converter 62 is less than the reference value and the set value of the D / A converter 61 is ＄ FF (hexadecimal), the maximum Even though the offset voltage is applied, the level of the mirror portion of the reproduction signal is less than an appropriate value.
Abnormally ends as "offset control impossible".

By the above processing, as shown in FIG. 24, the offset voltage is sequentially adjusted so that the voltage level of the mirror portion of the reproduction signal to which the offset voltage is added does not exceed the reference value,
Ultimately, it can be the optimal value.

According to the present embodiment, since the offset control can be performed in parallel with the initial focus pull-in operation, there is an effect of reducing the processing time. Further, according to the present embodiment, the offset voltage can be reduced as the voltage level of the mirror portion of the reproduction signal increases, so that the output signal is always controlled to a level lower than the reference value, which is effective for the protection of the subsequent stage. is there.

Hereinafter, an eleventh embodiment will be described. This embodiment is an embodiment of the gain control circuit 4 using a microprocessor.

The gain control circuit 4 controls the difference between the reproduction signal level of the pits formed in advance on the optical disc 1 and the reproduction signal level of the mirror unit to have an appropriate value. An example of the gain control circuit 4 using the mirror part detection signal 8 and the pit part detection signal 7 is shown in FIGS. 25 and 26.

The gain control circuit 21 is an amplifier circuit whose amplification rate changes under the control of the MPU 60. The gain switching circuit 21
Amplify and output at the amplification rate set by U60. The A / D converter 62 is used for the MPU 60 to obtain the level of the mirror portion and the pit of the amplified reproduced signal as digital data.

In the case of Fig. 25, A / D is applied to each of the mirror section and the pit.
A converter 62 is provided. That is, the mirror section detection signal 8
A mirror A / D converter 62-1 for converting the voltage level of the reproduced signal amplified with the timing to the data, and the pit for converting the voltage level of the reproduced signal amplified with the pit detection signal 7 into the data. A / D converter 62-2
And

The configuration shown in FIG. 26 shares the A / D converter 62 with other circuits. The high-speed A / D converter 63 converts the voltage level of the reproduced signal amplified at a sufficiently high cycle of the clock φ into data. The output of the high-speed A / D converter 63 is input to the signal processing circuit 6 and distributed to each processing circuit in the signal processing circuit 6 via a data bus. The data bus includes a mirror section level latch circuit 64-1 and a pit level latch circuit 64.
-2. Mirror section level latch circuit 64-1
Is a mirror part detection signal 8, and the pit level latch circuit 64-2 takes in the data on the data bus, that is, the level of the mirror part and the pit of the amplified reproduced signal, with the pit part detection signal 7. In either configuration, the level of the mirror portion and the pit of the amplified reproduction signal can be sent to the MPU 60.

An example of a gain setting procedure of the gain control circuit 4 having this configuration will be described with reference to FIG.

In this procedure, the gain is first maximized, and while the difference between the level of the mirror portion and the pit of the amplified reproduced signal (the signal amplitude) is checked, the gain is gradually reduced until the gain matches the reference value. .

Here, the reference value is a signal amplitude value obtained when the gain is controlled to be appropriate. This value is the A / D converter 6
It is smaller than the difference between the maximum value and the minimum value in the range of 2. The A / D converter 62 has a finite input range, outputs a maximum value when the input exceeds the range, and outputs a minimum value when the input falls below the range. Therefore, when the reference value of the signal amplitude includes the minimum value and the maximum value, it cannot be determined that the signal amplitude is excessive. In this example, since the 8-bit A / D converter 62 is used, the value range is from 0 to $ FF (hexadecimal), and the reference value must be less than or equal to $ FD (hexadecimal).

In FIG. 28, first, in step S25, the gain is set to the maximum.

In step S26, the process waits until the level of the mirror portion and the pit of the amplified reproduced signal is converted into data.

In step S27, the amplitude value of the signal is substituted for the variable A.
Details of this processing will be described with reference to FIG.

In FIG. 30, in step S50, data of the pit level of the amplified reproduced signal is substituted for a variable B.
In step S51, the value of the variable B is checked. If the value is 0, $ FF (hexadecimal) is substituted into the variable A for storing the amplitude data, and the process is terminated. That is, even if the voltage level is lower than the input range of the A / D converter 62, since it is converted to 0, it is not regarded as an accurate pit level, and the maximum amplitude data is substituted.

In step S53, data of the level of the amplified reproduction signal in the mirror section is substituted for the variable A. Step S54
Then, the value of the variable A is checked, and if it is $ FF (hexadecimal number), the process ends. As in step S51, this is not regarded as an accurate mirror section level, considering the possibility of exceeding the input range of the A / D converter 62, and the process ends with the data having the maximum amplitude.

If the data has passed the inspections of steps S51 and S53, the process proceeds to step S55, in which the difference between variable A (mirror level) and variable B (pit level) is obtained, substituted for variable A, and the process is terminated. I do.

Returning to FIG. 28, the content of the variable A is compared with the reference value in step S28, and if it is larger than the reference value, the process proceeds to step S29. In step S29, the set gain is checked, and if the minimum value is set, the processing is abnormally terminated as error 2. That is, even though the minimum gain is set, the amplitude of the reproduced signal exceeds the appropriate value, and the processing ends abnormally as "gain control is impossible (because the input signal is too large)". In step S29, if the gain is not the minimum value, in step S30, the gain is reduced and step S26
Return to

On the other hand, if the variable A is equal to or smaller than the reference value in step S28,
Proceeding to step S31, the value is compared with the reference value again. If the value is not smaller than the reference value, it is already known that the value is not large in step S28. If the variable A is smaller than the reference value in step S31, the process proceeds to step S32 to check whether the gain is set to the maximum. If it is set to the maximum, even though the maximum gain is set, the amplitude of the reproduced signal is less than an appropriate value, and the gain cannot be controlled (because the input signal is too small). And terminate abnormally (error 1). If the gain is not maximum at step S32, the process ends normally. Since a value larger than the currently set gain is determined to be excessive, it is assumed that the optimum gain is set at a value lower than the reference value.

The gain control can be realized by the above processing procedure.

According to the present embodiment, since it is possible to determine whether the gain control is possible or not, it is possible to detect an abnormality of the optical disc 1 or the reproducing system,
This has the effect of improving safety and maintainability.

 Next, a twelfth embodiment will be described with reference to FIG.

This embodiment is a modification of the gain control circuit 4, and has a configuration similar to that of the eleventh embodiment and controls the gain by a different procedure.

In this procedure, first, the gain is minimized, and while the difference between the level of the mirror portion and the pit of the amplified reproduced signal (signal amplitude) is checked, the gain is gradually increased until the gain matches the reference value. is there.

 First, in step S33, the gain is set to a minimum.

In step S34, the process waits until the levels of the mirror section and the pits of the amplified reproduced signal are converted into data.

 In step S35, the amplitude value of the signal is substituted for the variable A.

The content of the variable A is compared with the reference value in step S36, and if it is smaller than the reference value, the process proceeds to step S37. In step S37, the set gain is checked, and if the maximum value is set, the processing is abnormally terminated as error 1.
That is, although the maximum gain is set, the amplitude of the reproduction signal is less than an appropriate value, and the processing ends abnormally as "gain control is impossible (because the input signal is too small)". If the gain is not the maximum value in step S37, the gain is increased in step S38 and the process returns to step S34.

On the other hand, if the variable A is equal to or larger than the reference value in step S36,
Proceeding to step S39, the value is compared with the reference value again. If the value is not larger than the reference value, it is already known in step S36 that the value is not smaller. If the variable A is larger than the reference value in step S39, the process proceeds to step S40 to check whether the gain is set to the minimum. If it is set to the minimum, it means that the amplitude of the reproduced signal exceeds the appropriate value, even though the minimum gain is set, and the gain control is not performed (because the input signal is too large). Abnormally ends as "possible" (error 2). If the gain is not minimum in step S40, the process ends normally. Since a value smaller than the currently set gain is determined to be the minimum, it is assumed that the optimum gain is set at a value higher than the reference value.

The gain control can be realized by the above processing procedure.

According to the present embodiment, since the gain adjustment is started from a low gain, the output changes from small to large, and the gain can be controlled without sending an excessive signal to a subsequent circuit, thereby improving the stability of operation. Has the effect.

 Next, the embodiment of FIG. 13 will be described with reference to FIG.

This embodiment is another modification of the gain control circuit 4,
The optimum gain is determined by using the data of the maximum voltage level and the minimum voltage level of the reproduction signal instead of the data of the voltage level of the mirror portion and the pit of the reproduction signal in the twelfth embodiment.

In FIG. 27, the other components except the maximum data detection circuit 65 and the minimum data detection circuit 66 are equivalent to those shown in FIGS. 25 and 26 described in the eleventh embodiment.

The maximum data detection circuit 65 sequentially compares the data output from the high-speed A / D converter 63 with the value held therein, and if the new data is larger than the previous one, determines the value held inside. Update to new data. Maximum data detection circuit 65
When the value held inside is read from MPU60,
It is cleared to a sufficiently small value (for example, 0).

The minimum data detection circuit 66 sequentially compares the data output from the high-speed A / D converter 63 with the value held therein, and if the new data is smaller than the previous data, the value held inside is Update to new data. Minimum data detection circuit 66
When the value held inside is read from MPU60,
Cleared to a sufficiently large value (for example, $ FF (hexadecimal)).

The purpose of the gain control is to supply a signal controlled to an appropriate signal amplitude to a circuit connected to the subsequent stage of the gain control circuit 4. Therefore, the object can be achieved by controlling the gain so that the difference between the maximum value and the minimum value of the signal falls within the input range of the subsequent circuit. Therefore, in the present configuration, the data obtained from the maximum data detection circuit 65 and the minimum data detection circuit 66 of the MPU 60 is converted into the A / V of the voltage level of the mirror portion and the pit of the reproduced signal in the eleventh embodiment.
By treating the data equivalent to the data obtained from the D converter, the gain can be controlled by the procedure shown in FIGS. 28 and 29.

Note that the maximum data detection circuit 65 and the minimum data detection circuit 66 can be realized by software. In that case, as shown in FIG. 31, the circuit configuration is such that the output of the high-speed A / D converter 63 can be read directly from the MPU 60.

An example of processing for obtaining the maximum value and the minimum value of the voltage level of the reproduction signal by software will be described with reference to FIG. In this example, the data of the high-speed A / D converter 63 is inspected N times, and the largest one is checked for the variable DX and the smallest one is checked for the variable
Stored in DN.

First, in step S41, the number of inspections N is substituted for a variable I which is a counter for counting the number of inspections, and in step S42, a variable DX holding the maximum data is set to 0, which is the minimum value of the data.
In step S43, the variable DN holding the minimum data is initialized to $ FF (hexadecimal), which is the maximum value of the data.

In step S44, the variable I, which is a counter, is checked. If it is 0, the process is terminated.
Proceed to S45.

In step S45, the data of the high-speed A / D converter 63 and the variable DX
If the data of the high-speed A / D converter 63 is larger than the variable DX, the process proceeds to step S46, and the value of the variable DX is changed to the high-speed A / D
The value is updated to the value of converter 63, and the process proceeds to step S49. Step S
At 45, if the data of the high-speed A / D converter 63 is smaller than the variable DX, the process directly proceeds to step S47.

In step S47, the data of the high-speed A / D converter 63 and the variable DN
If the data of the high-speed A / D converter 63 is smaller than the variable N, the process proceeds to step S48, and the value of the variable DN is changed to the high-speed A / D
The value is updated to the value of converter 63, and the process proceeds to step S49. Step S
At 47, if the data of the high-speed A / D converter 63 is larger than the variable DN, the process directly proceeds to step S49. In step S49, the variable I which is a counter is decremented by 1, and the process returns to step S44.

This processing is performed in step S26 in FIG.
Step S34 in FIG. 9 may be replaced by using the value of the variable DX instead of the voltage level of the mirror portion of the reproduction signal and the value of the variable DN instead of the voltage level of the pit of the reproduction signal.

According to the present embodiment, control can be performed based on the maximum level and the minimum level of the signal. Therefore, the mirror section and / or the pit can not be detected, or the signal can be used even when there is a signal larger than the mirror section. This has the effect of improving the performance.

The embodiment of FIG. 14 will be described with reference to FIGS. 33 and 34. This embodiment is an embodiment of a gain / offset control circuit.

33 and 34, the gain control circuit 4
This is the same as that described in the tenth to thirteenth embodiments. The mirror section level data detection circuit 80
Embodiments 9 to 9 have been described. Means for evaluating the amount of offset voltage applied, that is, A / D converter 62 for converting the reproduction signal level of the mirror section into data in the seventh embodiment, high-speed A / D converter in the eighth embodiment
Latch circuit that captures the level of 63 and the playback signal of the mirror section
64, or a microprocessor 60 and a D / A converter 6 constituted by the maximum data detecting means in the ninth embodiment.
The 1 and the offset addition circuit 51 are the same as those of the seventh embodiment.

33 and 34 are composed of the same components, but the order of the gain control circuit 4 and the offset control circuit 5 is different. That is, in FIG. 33, gain control is performed in advance, and then offset control is performed by the microprocessor 60. On the other hand, in FIG. 34, the gain control circuit 4 is placed after the offset voltage is applied, and the gain control is performed. Circuit 4
The microprocessor 60 performs offset control on the microprocessor 60 based on the output of the microprocessor 60.

First, in the gain / offset control circuit 5a having the configuration shown in FIG. 33, the reproduced signal is controlled to an appropriate gain by the gain control circuit 4 and input to the offset addition circuit 51. The configuration after the offset adding circuit 51 is the same as that shown in the seventh, eighth, and ninth embodiments, and performs offset control according to the procedure shown in FIG. This makes it possible to obtain a reproduced signal in which the gain and the offset are optimized. Further, since the A / D converter 62 is used in the mirror section level data detection circuit 80, the reproduction signal can be output as digital data.

In the gain / offset control circuit 5a having the configuration shown in FIG. 34, the reproduction signal is first added with an offset and then input to the gain control circuit 4. Even if the offset voltage is kept constant, when the gain control circuit 4 changes the gain,
Although the offset amount of the output reproduction signal changes, the mirror section level data detection circuit 80 for evaluating the amount of applied offset voltage outputs the changed reproduction signal, that is, the level of the output signal of the gain / offset control circuit 5a. Therefore, if an offset voltage is added so as to optimize this level, the final offset of the output signal becomes an optimal value. Therefore, the offset control procedure in the configuration of FIG. 34 may be the procedure as shown in FIG. This makes it possible to obtain a reproduced signal in which the gain and the offset are optimized. Further, since the A / D converter 62 is used in the mirror section level data detection circuit 80, the reproduction signal can be output as digital data.

According to the present embodiment, the offset and gain of the signal can be controlled to optimal values, so that there is an effect of improving operation stability. In addition, the digital data output of the reproduction signal level according to the present embodiment always converts the signal within the input range of the A / D converter 62 into digital data, so that accurate data can be obtained and the processing in the subsequent circuit is performed. Can be simplified, and the reliability can be improved.

A fifteenth embodiment will be described with reference to FIG. In this embodiment,
This is an example of the gain / offset control circuit 5a, in which offset control and gain control are used in combination using the offset control circuits 5 according to the seventh to ninth embodiments described above.

First, the reproduced signal is amplified by the gain switching circuit 21 with the gain set by the MPU 60 and input to the offset control circuit 5. The reproduction signal having the optimum offset by the offset control circuit 5 is sent to the pit level data detection circuit 70, and the pit level data detection circuit 70 sends the voltage level data of the pit reproduction signal to the MPU 60. The pit level data detection circuit 70 is a part of the means for evaluating the gain described in the eleventh embodiment and the thirteenth embodiment, that is, the pit reproduction signal level in the eleventh embodiment is Pit A / D converter 6
2, or a high-speed A / D converter 63 and a pit latch circuit 64 for capturing the level of a pit reproduction signal, or a minimum data detecting means in the thirteenth embodiment. Since the input signal of the pit level data detection circuit 70 has already been subjected to the offset control, the level of the reproduction signal of the mirror section or the data of the maximum value of the reproduction signal is known, so the level of the pit reproduction signal or The signal amplitude can be determined based on the data of the minimum value of the reproduction signal. MPU6
“0” switches the gain so that the signal amplitude becomes an optimum value.

The processing of the MPU 60 in the present embodiment is performed according to the procedure shown in FIGS. 28 and 29. When the gain of the gain switching circuit 21 is changed, the optimum offset voltage to be applied also changes. However, since the offset control is performed in a stage subsequent to the gain switching circuit 21, the optimum value is always obtained.

According to the present embodiment, by taking in data for signal amplitude determination after offset control is performed, the data of the level of the reproduction signal of the mirror section or the maximum value of the reproduction signal can be known, and the reproduction signal of the pit can be known. Since the signal amplitude can be determined by obtaining only the data of the level or the minimum value of the reproduced signal, the number of circuits can be reduced, and the determination can be facilitated.

The sixteenth embodiment will be described with reference to FIGS. 36 and 38. The present embodiment is an example of the gain and offset control circuit 69, in which the gain and the offset are controlled by the microprocessor 60.

The gain / offset control circuit 69 according to the present embodiment
A gain switching circuit 21 that is an amplification circuit whose amplification factor changes under the control of U60, and an A / A circuit that provides a voltage corresponding to data set by the MPU 60 to the offset addition circuit 51 as an offset voltage.
A D converter 61, an offset addition circuit 51 that outputs a voltage obtained by adding an offset voltage to the reproduction signal gain-controlled by the gain switching circuit 21, and a level of the reproduction signal of the mirror unit or the reproduction signal from the output of the offset addition circuit 51 An A / D converter 67 for taking in the maximum value data of the pits and the data of the pit reproduction signal level or the minimum value of the reproduction signal;
It is composed of PU60.

The A / D converter 67 has been described in the eleventh embodiment and the thirteenth embodiment, but means for evaluating the gain, that is,
In the eleventh embodiment (see FIG. 25), a mirror A / D converter 62 for converting the voltage level of the reproduced signal amplified to data with the mirror detection signal as a timing in the eleventh embodiment, and amplified with the pit detection signal as a timing. Pit A / D converter 62 or high-speed A that converts the voltage level of the reproduced signal
/ D converter 63, a mirror section latch circuit 64-1 for capturing data of a reproduction signal level of the mirror section, a pit section latch circuit 64-2 for capturing the level of the pit reproduction signal, or a thirteenth embodiment ( (See FIG. 27) and the minimum data detecting means 65 and the maximum data detecting means 65.

An example of a gain and offset control procedure in this embodiment will be described with reference to FIG. In the procedure in FIG. 38, the gain is changed from the maximum to the minimum, and the offset is controlled again each time the gain is changed.

 First, in step S56, the gain setting is maximized.

In step S57, offset control is performed. Details of this processing are as described in the seventh, eighth, and ninth embodiments.

In step S58, it is checked whether an error has occurred in the offset control. If an error has occurred, the process proceeds to step S59. In step S59, it is checked whether the generated error is error 2, and if it is error 2, the process proceeds to step S60. When the error is other than the error 2, the error is the error 1, that is, "the offset control is impossible (because the input signal is too small)", and the process ends abnormally as the error 3. The gain is changed from the maximum value to the minimum value.After the immediately preceding gain is determined to be excessive, the gain is reduced, offset control is performed, and since it is determined that the input signal is excessive, there is no appropriate gain. And

In the case of error 2 in step S59, that is, it is "offset control is impossible due to an excessive input signal", the set gain is checked in step S60. I do. In other words, offset control is impossible due to an excessive input signal despite the minimum gain, so it is determined that "control is impossible due to excessive input signal". If the gain has not been set to the minimum in step S60, the process proceeds to step S61, the gain is reduced, the process returns to step S57, and the offset control is performed again.

On the other hand, if no error has occurred in the offset control in step S57, the process proceeds to step S62, and the signal amplitude value is substituted for the variable A.

In step S63, the variable A is checked, and if it is larger than the reference value, the process proceeds to step S60. In step S60, the set gain is checked. That is, since the signal amplitude has become larger than the reference value despite the minimum gain, it is determined that "control is impossible due to an excessive input signal". On the other hand, if the gain is not set to the minimum in step S60, the process proceeds to step S61, the gain is reduced, and the process returns to step S57, where offset control is performed again.

If the variable A is equal to or smaller than the reference value in step S63, the process proceeds to step S64. In step S64, it is checked whether or not the variable A is smaller than the reference value.
Proceed to 5. In step S65, the set gain is checked. That is, since the signal amplitude has become smaller than the reference value despite the maximum gain, it is determined that “the input signal is too small to control”. If the gain is not set to the minimum, the process ends normally because the gain setting is closest to the reference value but less than the reference value for the resolution of the gain setting. When the variable A is not smaller than the reference value in step S64, the case where the variable A is already larger than the reference value is branched in step S63, so that the variable A matches the reference value, and the process ends normally.

According to the present embodiment, since the gain / offset control circuit 69 can be realized by one MPU 60, there is an effect of reducing the circuit scale and reducing the cost.

A seventeenth embodiment will be described with reference to FIGS. 37 and 39. This embodiment is an example of the gain / offset control circuit 69,
The circuit components are the same as those of the sixteenth embodiment, but the gain is switched after adding an offset voltage to the reproduced signal.

The gain / offset control processing in this embodiment
As in the case of the sixteenth embodiment, it can be performed by the procedure shown in FIG. Further, in the gain / offset control circuit 69 of this embodiment, the gain / offset control processing can be performed also in the procedure shown in FIG.

In the circuit configuration of the present embodiment, first, the offset voltage is added to the reproduced signal, and then the gain is switched. Therefore, once the offset voltage is once set to the optimum value, the gain is set to 1 / M. The offset as the output of the offset control circuit 69 is 1 / M of the optimum value. The processing means shown in FIG.
When the amplification factor is changed by 1 / M by the setting of U60, by multiplying the offset by M, the optimum offset voltage is maintained without performing the offset control every time.

In this procedure, first, in step S66, the gain setting is maximized.

In step S67, offset control is performed. Details of this processing are as described in the seventh, eighth, and ninth embodiments.

In step S68, it is checked whether an error has occurred in the offset control. If an error has occurred, the process proceeds to step S69. In step S69, it is checked whether or not the error that has occurred is error 2. If it is error 2, step S7 is performed.
Go to 0. When the error is other than the error 2, the error is the error 1, that is, "the offset control is impossible (because the input signal is too small)", and the process ends abnormally as the error 3. The gain is changed from the maximum value to the minimum value.After the immediately preceding gain is determined to be excessive, the gain is reduced to perform offset control,
Since it is determined that the input signal is too small, it is determined that there is no appropriate gain.

In the case of error 2 in step S69,
Since "(offset control is impossible) due to excessive input signal", the set gain is checked in step S70. In other words, offset control is impossible due to an excessive input signal despite the minimum gain, so it is determined that "control is impossible due to excessive input signal". Step S7
If 0 and the gain is not set to the minimum, step S
Proceeding to 71, set the gain to 1 / M, return to step S67, and perform offset control again.

On the other hand, if no error has occurred in the offset control in step S67, the process proceeds to step S72. At this stage, the offset control has been completed. In step S72, the signal amplitude value is substituted for the variable A.

In step S73, the variable A is checked, and if it is larger than the reference value, the process proceeds to step S74. In step 74, the set gain is checked. That is, since the signal amplitude has become larger than the reference value despite the minimum gain, it is determined that "control is impossible due to an excessive input signal". On the other hand, if the gain has not been set to the minimum in step S74, the process proceeds to step S75, where the gain is set to 1 / M, and in step S76, the offset is set to M times.

By the processing in step S76, the offset voltage is corrected by the change in gain in step S75. After the process in step S76, the process returns to step S72, and the loop of S72 → S73 → S74 → S75 → S76 is repeated until the signal amplitude becomes equal to or smaller than the reference value.

If the variable A is equal to or smaller than the reference value in step S73, the process proceeds to step S77. In this step S77, this time,
It is checked whether the variable A is smaller than the reference value, and if it is smaller, the process proceeds to step S78. In step S78, the set gain is checked. That is, since the signal amplitude has become smaller than the reference value despite the maximum gain, it is determined that “the input signal is too small to control”. If the gain is not set to the minimum, the gain setting is closest to the reference value, but the gain setting is less than the reference value by the resolution of the gain setting. On the other hand, if the variable A is not smaller than the reference value in step S78, the case where the variable A is already larger than the reference value is branched in step S73, so that the variable A matches the reference value, and the process ends normally.

According to the present embodiment, once the offset control is performed,
Since the gain and the offset can be controlled without performing thereafter, there is an effect of improving the processing speed.

In the above-described embodiments, the optical disk has been described as an example of a signal recording medium.
It is apparent that the present invention is not limited to an optical disc as a signal recording medium, but can be applied to an information reproducing apparatus for reproducing information from an information storage medium capable of reproducing information optically, such as an optical memory card. .

Also, when an electronic circuit and software having the configuration described in the above embodiment are integrated into an IC, it is possible to reduce the number of circuit components, reduce the circuit board area, and improve the reliability of the circuit. It is.

Further, by making the electronic circuit and software having the configuration described in the above embodiments into, for example, a signal processing IC or an analog / digital converter (A / D converter), Further, the number of circuit components can be reduced, the area of the circuit board can be reduced, and the reliability of the circuit can be improved. In addition, the analog / digital converter having such a function detects the range of the input signal,
By changing the offset level and the amplification (gain) of the input signal in accordance with that, it is possible to perform analog / digital conversion on a wide range of input signals.

In addition, the control of the offset level in the present invention is as follows:
The present invention is not limited to the embodiments described above, but may be applied to other embodiments using a pedestal clamp, for example, and the present invention is widely applied to them.

According to the present invention, the amplitude and offset level of a signal input to the signal processing circuit can be optimized without changing the light amount of the laser light. It is possible to solve problems that may occur when the amount of laser light for recording or the like is increased, and to reduce the error rate when reproducing a signal, thereby improving the reliability of information. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram of an offset control circuit and a gain control circuit constituting a first embodiment of the present invention, FIG. 2 is a block diagram of a gain control circuit constituting a first embodiment, and FIG. FIG. 4 is a block diagram of a gain control signal generating circuit of the gain control circuit, and FIG. 5 is a block diagram of an offset control circuit of the first embodiment. FIG. 6 is a block diagram of an offset adder circuit constituting the offset control circuit, FIG. 7 is a block diagram of an offset control signal generation circuit constituting the offset control circuit, and FIG. 8 is a second embodiment. FIG. 9 is a block diagram of a gain control signal generation circuit constituting the second embodiment, and FIG. 10 is an offset circuit constituting the third embodiment. FIG. 11 is a block diagram of a gain control signal generating circuit constituting the fourth embodiment, FIG. 12 is a block diagram of an offset control circuit and a gain control circuit constituting the fifth embodiment, FIG. 13 is a block diagram of an offset control circuit and a gain control circuit constituting the sixth embodiment. FIG. 14 is a waveform diagram schematically showing pits and additional recording portions of a sampled format disc, a reproduced signal, and the like. FIG. 15 is a block diagram of a mirror section and a pit detection circuit, FIG. 16 is a block diagram of an offset control circuit constituting a seventh embodiment, and FIG. 17 is a block diagram of an offset control circuit constituting an eighth embodiment. FIG. 18 is a block diagram of the offset control circuit constituting the tenth embodiment, FIG. 19 is a flowchart showing the flow of the offset control circuit according to the seventh embodiment, and FIGS. Block diagram of the offset control circuit constituting an example, Figure 22 is a flowchart showing a flow of maximum value processing of the offset control circuit according to an embodiment of the ninth, FIG. 23 No. 10
FIG. 24 is a flowchart showing the flow of processing of the offset control circuit according to the embodiment of the present invention, FIG. 24 is a waveform diagram showing the operation of the offset control circuit according to the tenth embodiment, and FIGS. 25 and 26 are gains constituting the eleventh embodiment. Block diagram of control circuit, Nos. 27 and 31
FIG. 28 is a block diagram of a gain control circuit constituting the thirteenth embodiment, FIG. 28 is a flowchart showing the flow of the gain control circuit according to the eleventh embodiment, and FIG. 29 is a diagram of the gain control circuit according to the twelfth embodiment. Flow chart showing the flow, FIG.
FIG. 32 is a flowchart showing the details of the amplitude value processing of the gain control circuit according to the eleventh embodiment, FIG. 32 is a flowchart showing the flow of the maximum value and minimum value processing of the gain control circuit according to the thirteenth embodiment, and FIGS. FIG. 35 is a block diagram of an offset control circuit and a gain control circuit constituting a fourteenth embodiment, FIG. 35 is a block diagram of an offset control circuit and a gain control circuit constituting a fifteenth embodiment, and FIG. FIG. 37 is a block diagram of an offset control circuit and a gain control circuit constituting an example, FIG. 37 is a block diagram of an offset control circuit and a gain control circuit constituting a seventeenth embodiment, and FIG.
FIG. 39 is a flowchart showing a control flow of the offset control circuit and the gain control circuit according to the sixteenth embodiment.
6 is a flowchart showing a control flow of an offset control circuit and a gain control circuit according to the embodiment of FIG. DESCRIPTION OF SYMBOLS 1 ... Optical disk, 2 ... Optical head, 3 ... IV conversion circuit, 4 ... Gain control circuit, 5 ... Offset control circuit, 6 ... Signal processing circuit, 7 ... Pit detection signal, 8 ...
Mirror detection signal, 9 Reproduction signal, 21 Gain switching circuit, 22 Gain control signal generation circuit, 23 Level difference detection signal, 24 Gain control signal, 41 Vm detection circuit , 42… Vp detection circuit, 45… differential amplifier, 46…
Comparator, 410 ... Up / down counter, 51 ...
Offset addition circuit, 52: Offset control signal generation circuit, 53: Offset control signal, 54: Offset level detection signal, 71: Vm 'detection circuit, 73: Low-pass filter, 74: Differential amplifier, 81 …… Voltage controlled amplifier, 91
1 ... Digital / analog converter, 100 ... Capacitor, 111 ... Vm detection circuit, 112 ... Vp detection circuit, 114 ...
Reset pulse generation circuit, 60: MPU, 61: Digital / analog converter, 62: Analog / digital converter.

Claims (10)

(57) [Claims] An optical head for irradiating an optical disk on which a signal is recorded with a light beam, receiving a signal light modulated in accordance with recorded information, and converting a change in the signal light into a current signal; An information reproducing apparatus having a current-voltage conversion circuit for converting an output current signal of the optical head into a voltage signal, wherein the information reproduction apparatus has a configuration separated from the current-voltage conversion circuit, and detects its own output as an offset detection signal. An offset control circuit that performs offset control of a controlled signal based on an offset amount set from the offset detection signal and a reference value, and the offset control circuit controls a DC offset level of an output signal of the current-voltage conversion circuit. An information reproducing apparatus having a configuration. 2. An optical head for irradiating an optical disk on which a signal is recorded with a light beam, receiving a signal light modulated in accordance with recorded information, and converting a change in the signal light into a current signal; An information reproducing apparatus having a current-voltage conversion circuit for converting an output current signal of the optical head into a voltage signal, wherein the information reproduction apparatus has a configuration separated from the current-voltage conversion circuit, and detects an output of itself to generate an amplitude detection signal. A gain control circuit for controlling the gain of the controlled signal based on a gain control amount set from the amplitude detection signal and the reference value, wherein the gain control circuit controls the signal amplitude of the output signal of the current-voltage conversion circuit. An information reproducing apparatus having a configuration. 3. An optical head for irradiating an optical disk on which a signal is recorded with a light beam, receiving a signal light modulated according to recorded information, and converting a change in the signal light into a current signal; An information reproducing apparatus having a current-voltage conversion circuit for converting an output current signal of the optical head into a voltage signal, wherein the information reproduction apparatus has a configuration separated from the current-voltage conversion circuit, and detects an output of itself to generate an amplitude detection signal. A gain control circuit for controlling the gain of the controlled signal based on a gain control amount set from the amplitude detection signal and the reference value; and a configuration separate from the current-voltage conversion circuit, and detecting an output of the gain control circuit. To obtain the offset detection signal,
An offset control circuit that performs offset control of a controlled signal based on an offset amount set from the offset detection signal and a reference value, wherein an output signal of the current / voltage conversion circuit is used as a controlled signal of the offset control circuit, The control circuit controls the DC offset level of the output signal of the current-voltage conversion circuit, and the gain control circuit uses the output signal of the offset control circuit as a controlled signal of the gain control circuit. An information reproducing apparatus characterized in that the amplitude of an output signal is controlled. 4. An optical head for irradiating an optical disk on which a signal is recorded with a light beam, receiving a signal light modulated according to recorded information, and converting a change in the signal light into a current signal; An information reproducing apparatus having a current-voltage conversion circuit for converting an output current signal of the optical head into a voltage signal, wherein the information reproduction apparatus has a configuration separated from the current-voltage conversion circuit, and detects its own output as an offset detection signal. An offset control circuit that performs offset control of the controlled signal based on an offset amount set from the offset detection signal and the reference value, and a configuration separated from the current-voltage conversion circuit, and detects an output of the offset control circuit. A gain control circuit that performs gain control of the controlled signal with a gain control amount set from the amplitude detection signal and a reference value, Using the output signal of the current-voltage conversion circuit as a controlled signal of the gain control circuit, the gain control circuit controls the signal amplitude of the output signal of the current-voltage conversion circuit, and sets the output signal of the gain control circuit to the offset. An information reproducing apparatus, wherein an offset level of an output signal of the gain control circuit is controlled by the offset control circuit as a signal to be controlled by a control circuit. 5. An optical head for irradiating an optical disk on which a signal is recorded with a light beam, receiving a signal light modulated according to recorded information, and converting a change in the signal light into a current signal; An information reproducing apparatus having a current-voltage conversion circuit for converting an output current signal of the optical head into a voltage signal, wherein the information reproduction apparatus has a configuration separated from the current-voltage conversion circuit, and detects its own output as an offset detection signal. An offset control circuit that performs offset control of a controlled signal based on an offset amount set from the offset detection signal and a reference value, and a configuration separated from the current-voltage conversion circuit, and detects an output of itself to detect an amplitude. A gain control circuit for controlling the gain of the controlled signal based on a gain control amount set from the amplitude detection signal and the reference value. The output signal of the offset control circuit as a controlled signal of the offset control circuit, the offset control circuit controls the DC offset level of the output signal of the current-voltage conversion circuit, and outputs the output signal of the offset control circuit to the gain control circuit An information reproducing apparatus, wherein an amplitude of an output signal of the offset control circuit is controlled by the gain control circuit as a controlled signal. 6. An optical head for irradiating an optical disk on which a signal is recorded with a light beam, receiving a signal light modulated according to the recorded information, and converting a change in the signal light into a current signal; An information reproducing apparatus having a current-voltage conversion circuit for converting an output current signal of the optical head into a voltage signal, wherein the information reproduction apparatus has a configuration separated from the current-voltage conversion circuit, and detects an output of itself to generate an amplitude detection signal. A gain control circuit for controlling the gain of the controlled signal by a gain control amount set based on the amplitude detection signal and the reference value, and a configuration separated from the current-voltage conversion circuit, and detecting its own output. An offset control circuit for performing offset control of the controlled signal based on an offset amount set from the offset detection signal and a reference value. The output signal of the path is controlled by the gain control circuit, and the gain control circuit controls the signal amplitude of the output signal of the current-voltage conversion circuit, and outputs the output signal of the gain control circuit to the offset control circuit. An information reproducing apparatus, wherein an offset level of an output signal of the gain control circuit is controlled by the offset control circuit as a controlled signal. 7. The offset control circuit compares a level of an offset detection signal at a specific timing determined by a timing signal with a reference value,
An offset control signal generation circuit that generates an offset control signal that determines an offset amount corresponding to the comparison result; and an offset addition circuit that adds the offset amount determined by the offset control signal to the controlled signal and outputs an offset-controlled signal. The information reproducing apparatus according to claim 1, 3, 4, 5, or 6, wherein the information reproducing apparatus is configured to include: 8. The gain control circuit compares an amplitude level, which is a level difference between amplitude detection signals at two or more specific timings determined by two timing signals, with a reference value, and performs gain control in accordance with the comparison result. A gain control signal generating circuit for generating a gain control signal for determining the amount, and a gain switching circuit for outputting a signal whose amplitude is controlled by amplifying the controlled signal in accordance with the gain control amount determined by the gain control signal. 7. The information reproducing apparatus according to claim 2, wherein the information reproducing apparatus is provided. 9. The signal according to claim 7, wherein the timing signal is a signal indicating that a signal is reproduced from a specific area other than an area for recording information in the storage format set on the information storage medium. 8. The information reproducing apparatus according to 8. 10. The offset adding circuit has a high-pass filter for blocking a DC component of a controlled signal, and an offset level of an output thereof does not depend on an offset level of the controlled signal. 7. The information reproducing apparatus according to 7.