JP2662401B2 - Image processing device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an image processing apparatus such as a digital printer and a digital facsimile. [Prior art] Conventionally, as a binarization method for reproducing a halftone in a digital printer, a digital facsimile, and the like,
There is a dither method using a dither matrix in which a threshold value is periodically changed. In this method, the number of gradations that can be expressed is limited by the dither matrix. For example, when the number of gradations is about 16 gradations, there is a drawback that a pseudo contour is generated in an output image. Further, as a binarization method that has recently attracted attention, there is a method called an error diffusion method in which an error generated in the binarization processing is distributed to peripheral pixels. This method was described in 1975 by Floid and Steinberg as “An Adaptive Al
gorithm for Spatial Gray Scale "SID DIGEST" is proposed in a paper called "SID DIGEST", and is a method superior in resolution and gradation to the dither method. [Problems to be Solved by the Invention] When the density of the original is low, there occurs a portion where no dot is formed as shown in Fig. 9, which has the disadvantage that the image quality is remarkably reduced. The following can be considered as causes: When the low-density image is binarized by the error diffusion method, the positive error diffused to the surroundings during the binarization is small.
Positive errors collected at the pixel of interest are also reduced. Therefore, the density of the pixel of interest does not easily exceed the threshold value for binarization (normally 127), and a dot-free portion as shown in FIG. 9 occurs. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional technique, and binarizes input image data while correcting error data between input and output densities generated by binarization processing, thereby achieving gradation and resolution. An excellent image can be obtained, and the threshold value for binarization is set according to the image density level of the input image data. An object of the present invention is to provide an image processing apparatus capable of obtaining a reproduced image faithful to an input image density by setting a low-level threshold value with a corresponding probability. [Means for Solving the Problems] To achieve the above object, according to the image processing apparatus of the present invention, an input unit for inputting image data representing an image density, and an image of the image data input by the input unit Setting means for setting a threshold value for binarizing the input image data in accordance with the density level; and binarizing the input image data into binary data using the threshold value set by the setting means.
Value conversion means, correction means for correcting error data between input and output densities generated by the binarization processing of the binarization means,
Output means for outputting a binarization result of the binarization means, wherein the setting means sets a low level threshold with a probability corresponding to the image density level when the image density level of the input image data is low. It is characterized by the following. Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of the image processing apparatus of the present embodiment. Image data read by an input device 1 having a photoelectric conversion element such as a CCD and a drive system for scanning the same is sequentially sent to an A / D converter 2. Here, for example, the data of each pixel is converted into 8-bit digital data. This gives 256
This means that the data is quantized into data having the number of levels. Next, in the correction circuit 3, correction such as shading correction for correcting unevenness in sensitivity of the sensor and unevenness in illuminance caused by the illumination light source is performed by digital arithmetic processing. Next, the corrected 100 is input to the threshold value setting circuit 4, the binarization processing circuit 5, and the determination circuit 6. In the threshold value setting circuit 4, the judgment circuit 6
The threshold value for binarization is set based on the determination signal 400 output from the correction circuit 100 and the corrected signal 100 output from the correction circuit 3, and a threshold signal 200 is output. In the binarization circuit 5, the threshold signal output from the threshold setting circuit 4 is binarized by the corrected signal 100 output from the correction circuit 3 by 200,
The binary signal 300 is output. The determination circuit 6 refers to the already binarized area around the target pixel to be binarized by the binary signal 300 output from the binarization circuit 5 and the corrected signal 100 output from the correction circuit 3. Then, it is determined whether or not there is a dot that is on, and a determination signal
Outputs 400. The output device 7 is constituted by a laser beam printer, an ink jet printer, or the like, and turns on and off the binary signal 300 output from the binarization circuit 5.
When OFF, image formation is performed. FIG. 2 is a block diagram showing details of the threshold setting circuit 4. The judgment signal 400 output from the judgment circuit 6 and the correction circuit 3
The corrected signal 100 output from is input to the ROM 8. ROM
In 8, when the judgment signal 400 is “0” and the signal 100 is 1 or more and less than 5, “0” is set, and when the judgment signal 400 is “0” and the signal 100 is 5 or more and 15
If it is less than “1”, the judgment signal 400 is “0” and if the signal 100 is 15 or more and less than 30, “2”. If the judgment signal 400 is “0” and the signal 100
"3" is output as the signal 110 when the determination signal 400 is "1", and "4" is output regardless of the value of the signal 100 when the determination signal 400 is "1". The signal 110 output from the ROM 8 is input to the selector 12, and depending on the value of the signal 110, the signal 120 from the RAM 9 if the signal 110 is "0", and the signal 1 from the RAM 10 if the signal 110 is "1".
If the signal 30 is "2", the signal 140 from the RAM 11 is selected, if the signal 110 is "3", the signal 150 is selected, and if the signal 110 is "4", the signal 160 is selected and output as the threshold signal 200. . RAM 9 stores a uniform random number sequence (integer) from 20 to 230,
10 stores a uniform random number sequence (integer) from 50 to 200, and R
AM11 stores a uniform random number sequence (integer) of 100 or more and 150 or less. The signal 150 is 127 and the signal 160 is 255. Here, as described above, using three RAMs and setting the threshold value to 3
Although a uniform random number sequence in stages is used, a random number sequence in multiple stages may be used as a threshold by increasing the number of RAMs. At this time, it is better to widen the range of random number generation in a portion where the image density is low, and to narrow the range of random number generation as the density increases. The signal 160 may have a value of 255 or more. In addition, the portion where the concentration is 0 is used to prevent the occurrence of dots.
If the density is 0, a fixed threshold (for example, 127) is set to the threshold signal 200
And As a result, for example, a dot generated in the background portion of the character portion can be prevented. In the above configuration, by lowering the binarization threshold with a certain probability in a portion where the image density is low, it is possible to prevent a dot that has occurred in a portion where the image density is low from missing and becoming white. Further, by controlling the size of the threshold value in accordance with the image density, it is possible to suppress the deterioration of the character portion and to maintain the smoothness of the image. Further, since a random number is used as the threshold value, the uniformity of a portion where the image density is low after binarization is increased. FIG. 3 is a block diagram of the binarizing circuit 5. The corrected signal 100 (density of the pixel of interest) output from the correction circuit 3 is combined with the error E _ij (total sum of errors distributed to the pixel of interest) stored in the error buffer memory 14 and the adder 13.
, And as a result, an error corrected signal 210 is output. Next, the error corrected signal 210 is input to the comparator 15, where it is compared with the threshold signal 200. And the error corrected signal 210
Is greater than threshold signal 200, "1";
Is output as a binary signal 300. On the other hand, in the converter 16, the input binary signal 300 is "0".
If the value is “1”, the value is converted to “ _Dmax ”, and the value is output as the signal 220. The signal 210 and the signal 220 are input to the arithmetic unit 17. Here, the difference between the two signals is calculated and output as a signal 230 (ΔE _ij ). This signal 230 is input to the weighting circuit 18, where it is weighted (α _kl ) and then added to the error at a predetermined pixel position in the error buffer. FIG. 4 shows an example of the weight coefficient (α _kl ). Here, * corresponds to the target pixel position (I, J). By repeating the above operation, binarization by the error diffusion method is performed. In this embodiment, the corrected signal 100
Because the covered in 8 bits although a D _max = 255, if the corrected signal 100 to handle in m bits, and ^{_{D max = 2 m-1 +2}} m-2 + ... + 2 0. FIG. 5 shows a block diagram of the decision circuit 6. The binary signal 300 is input to the line buffer 19 and latched at the same time. A signal read from the line buffer 19 is also input to the line buffer 18 and latched at the same time. That is, assuming that the position of the pixel of interest to be processed is (I, J), the surrounding pixel position (I-2, J-
2), (I-1, J-2), (I, J-2), (I + 1, J-
2), (I + 2, J-2), (I-2, J-1) (I-1, J-
1), (I, J-1), (I + 1, J-1), (I + 2, J-
1), (I-2, J) and (I-1, J), the binarized data of 12 pixels are latched. The latched data for 12 pixels is input to the OR circuit 20. Here, data “OR” for 12 pixels is obtained, and the result is output as a signal 320. The corrected signal 100 is input to the comparator 17, and the threshold D = 20
The signal 310 is output as “1” if the signal 100 is larger than the threshold value D, and “0” if the signal 100 is smaller than the threshold value D. Thus, the density of the image can be determined. The selector 21 outputs the signal 320 if the signal 310 is “0” and the signal 330 if the signal 310 is “1” according to the value of the signal 310.
Output as However, the value of the signal 330 is “0”. That is, for a pixel having a low image density, the binarized data around the pixel of interest is examined, and if there is a signal for turning on the dot among them, 320 becomes 1;
The signal 400 to 1 becomes 1, whereby the threshold setting circuit selects a threshold. At this time, if there is no signal for turning on the dot around the pixel of interest, the signal 20 becomes 0.
Then, the threshold is selected by this. For pixels with high image density, signal 330 is
Since the threshold value is selected in step 9, the threshold value setting circuit 4 selects a threshold value based on the selected value, and performs a binarization process. According to the above configuration, no dot is formed around the area where the dot is formed in the low density portion. Therefore, it is possible to prevent the above-described dot whiteout phenomenon in the low image density portion, and to examine the binarized data around the target pixel to determine the proximity of the dot generated in the low image density portion. The phenomenon of being hit can be prevented. [Other Embodiment 1] FIG. 6 is a block diagram when a part of the threshold value setting circuit 4 in the above embodiment is changed. The signal 100 output from the correction circuit 3 is input to the ROM 22. In the ROM 22, a signal 410 is output by the following equation. (Signal 410) = [(L1-L2) * (Signal 100) / 255] where [] is a Gaussian symbol. Also here
L1 = 185 and L2 = 20 are used. FIG. 7 shows signal 100 and signal 4
The relationship of 10 is shown, but this is merely an example, and the present invention is not limited to this as long as the relationship that the signal 410 is small when the signal 100 is small is also small. L1 and L2 are not limited to this as long as the relationship of L1> L2 is satisfied. The RAM 23 stores a uniform random number sequence from 0 to L3. However, L3 + L1 <255 is satisfied. In the adder 24, the signal 410 and the signal 420 are added and output as a signal 430. In the selector 25, the signal 400 is set to “0” by the determination signal 400.
Signal 430 if signal 400 is "1"
Is output as the threshold signal 200. Here, signal 440 is 255
, But any value of 255 or more is acceptable. With the above configuration, it is possible to provide a threshold setting function similar to that of the above-described embodiment and reduce the hardware scale. [Other Embodiment 2] FIG. 8 is a block diagram when the judgment circuit 6 in the above embodiment is changed. The binary signal 300 is input to the line buffer 26 and simultaneously latched. The signal read from the line buffer 26 is also input to the line buffer 27 and latched at the same time. That is, assuming that the position of the pixel of interest to be processed is (I, J), the surrounding pixel position (I-2, J-
2), (I-1, J-2), (I, J-2), (I + 1, J-
2), (I + 2, J-2), (I-2, J-1), (I-1, J-1)
-1), (I, J-1), (I + 1, J-1), (I + 2, J-
1), (I-2, J) and (I-1, J), the binarized data of 12 pixels are latched. In the OR circuit 28, the pixel positions (I-1, J-1), (I, J-
1), 'OR' of the binarized data for four pixels of (I + 1, J-1), (I-1, J) is obtained, and as a result, a signal 520 is output. In OR29, pixel positions (I-2, J-2), (I-1, J-
2), (I, J-2), (I + 1, J-2), (I + 2, J-
2), (I-2, J-1), (I + 2, J-1), (I-2, J-1)
'OR' of the binarized data for eight pixels of J) is performed, and as a result, a signal 530 is output. The LUT 30 outputs a three-level switching signal 510 according to the input corrected signal 100. The switching signal 510 is “1” when the corrected signal 100 is equal to or less than 20;
It is set to “0” when it is 1 or more. In the selective OR circuit 31, the switching signal 510 output from the LUT 30
If the switching signal 510 is “0”, “0”, if “1”, the value obtained by taking the OR of the signals 520 and 530, and if “2”, the signal 520 as the determination signal 400 Output. For example, when the corrected signal 100 is 18, the switching signal 510 is “1”. At this time, if the signal 520 is “1” and the signal 530 is “0”, the determination signal 400
Becomes “1”. Here, the area to be referred to with respect to the value of the corrected signal 100 is determined in three stages (that is, whether the surroundings of the target pixel are not examined at all, the surrounding four pixels are examined, or the surrounding 12 pixels are examined).
Is set to Thus, the lower the density of the image,
Since the range for examining the surrounding area is enlarged, the dots can be dispersed according to the density, and the quality of the image is improved. By increasing the number of line buffers, latches and OR circuits as needed, the area to be referenced can be set in multiple stages. By the way, if there are four stages, the following can be considered. Let the position of the pixel of interest to be processed now be (I, J). The surrounding pixel positions (I-3, J-3), (I-2, J-3)
-3), (I-1, J-3), (I, J-3), (I + 1, J-
3), (I + 2, J-3), (I + 3, J-3), (I-3, J
-2), (I-2, J-2), (I-1, J-2), (I, J-
2), (I + 1, J-2), (I + 2, J-2), (I + 3, J
-2), (I-3, J-1), (I-2, J-1), (I-1,
J-1), (I, J-1), (I + 1, J-1), (I + 2, J-
1), (I + 3, J-1), (I-3, J), (I-2, J),
It is assumed that there are line buffers and latches necessary to hold the binarized data for 24 pixels of (I-1, J). And
It is assumed that there are three OR circuits (a, b, c) and one selective OR circuit (d). In the OR circuit a, the pixel position (I-1, J-1),
'OR' of the binarized data of four pixels (I, J-1), (I + 1, J-1), (I-1, J) is taken, and as a result, a signal e is output . In the OR circuit b, the pixel position (I-2, J
-2), (I-1, J-2), (I, J-2), (I + 1, J-
2), (I + 2, J-2), (I-2, J-1), (I + 2, J
-1), 'O' of the binarized data for 8 pixels of (I-2, J)
R ′ is taken, and as a result a signal f is output. In the OR circuit c, pixel positions (I-3, J-3), (I-2, J-3),
(I-1, J-3), (I, J-3), (I + 1, J-3),
(I + 2, J-3), (I + 3, J-3), (I-3, J-
2), (I + 3, J-2), (I-3, J-1), (I + 3, J
-1), 'O' of the binarized data for 12 pixels of (I-3, J)
R ′ is taken, and as a result a signal g is output. If the corrected signal 100 is less than or equal to 10, the selective OR circuit “d” takes the result of taking the “OR” of the signal e, the signal f, and the signal g. The result obtained by taking the “OR” of f may be such that the signal e is output as the determination signal if the corrected signal 100 is 21 or more and 50 or less, and “0” is output if the corrected signal 100 is 51 or more. Here, the corrected signal
100 levels of 10 or less, 11 or more, 20 or less, 21 or more, 50 or less, 5
There are four or more stages, but this is only an example. In addition, a color image can be realized by having the circuit shown in the present embodiment for a predetermined color. As described above, according to the present embodiment, the binarization threshold value is reduced at a certain probability in a portion where the image density is low, so that a dot that occurs in the portion where the image density is low is prevented from being hit and becoming white. it can. Further, by controlling the size of the threshold value according to the image density, it is possible to suppress the deterioration of the character portion and to maintain the smoothness of the image. In addition to simply lowering the threshold value for binarization, it is determined whether or not there is a dot hit in the already processed area around the target pixel, and the target pixel is quantized according to the determination result. By doing so, it is also possible to prevent a phenomenon in which dots are generated close to each other and occurred in a portion where the image density is low. Further, as the density of the image is lower, the processed area to be referred to is enlarged, so that dots can be printed with uniformity corresponding to the image density, and the quality of the image is improved. In this embodiment, the white spots and dots in the low-density portion are prevented from being closely hit.
The present invention can also prevent white noise that occurs because dots are not formed in high density portions. In this case, the dot is made variable according to the density of the threshold value (random number), and if there is no dot in the reference area around the image pixel of interest, the dot must be formed. In this case, a dot may be hit or not hit according to the threshold value. [Effects of the Invention] As described above, according to the present invention, the input image data is binarized while correcting the error data between the input and output densities generated by the binarization processing. An excellent image can be obtained, and the threshold value for binarization is set according to the image density level of the input image data. By setting the low-level threshold with the probability that the image is not whitened in a portion where the image density is low, the reproduced image faithful to the input image density can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the present embodiment, FIG. 2 is a block diagram of a threshold setting circuit 4, FIG. 3 is a block diagram of a binarization circuit 5, and FIG. FIG. 5 is a diagram showing an example of a weighting factor, FIG. 5 is a block diagram of the judgment circuit 6, FIG. 6 is a block diagram of the case where the threshold setting circuit 4 is changed, and FIG. FIG. 8 is a block diagram showing a case where the judgment circuit 6 is changed, and FIG. 9 is a diagram showing a conventional problem. In the figure, 1 is an input device, 2 is an A / D converter, 3 is a correction circuit, 4
Is a threshold setting circuit, 5 is a binarization circuit, 6 is a judgment circuit, and 7 is an output device.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-62-139473 (JP, A)                 JP-A-62-242473 (JP, A)                 JP-A-58-173973 (JP, A)                 JP-A-60-236363 (JP, A)                 JP-A-63-312150 (JP, A)

Claims (1)

(57) [Claims] Input means for inputting image data representing image density; setting means for setting a threshold value for binarizing input image data according to an image density level of the image data input by the input means; Binarizing means for binarizing input image data into binary data using the threshold value set in the step (a), and correcting error data between input and output densities generated by the binarizing processing of the binarizing means. Correction means; and output means for outputting a binarization result of the binarization means. When the image density level of the input image data is low, the setting means has a low level with a probability corresponding to the image density level. An image processing apparatus for setting a threshold value.