JP2660889B2 - Power supply current measuring device - Google Patents
Power supply current measuring deviceInfo
- Publication number
- JP2660889B2 JP2660889B2 JP26535792A JP26535792A JP2660889B2 JP 2660889 B2 JP2660889 B2 JP 2660889B2 JP 26535792 A JP26535792 A JP 26535792A JP 26535792 A JP26535792 A JP 26535792A JP 2660889 B2 JP2660889 B2 JP 2660889B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- amplifier
- resistor
- input
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Testing Of Individual Semiconductor Devices (AREA)
- Measurement Of Current Or Voltage (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、被測定物に電圧を供給
し、被測定物に流れる電流を測定する電源電流測定装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply current measuring device for supplying a voltage to a device under test and measuring a current flowing through the device under test.
【０００２】[0002]
【従来の技術】被測定素子又は被測定回路である被測定
物（以下ＤＵＴという）の電圧−電流特性を得るために
被測定素子に直流電圧を出力する電源電流測定装置は、
通常、その出力部に帰還型増幅器を使用する。しかし、
この帰還型増幅器は、ＤＵＴが負抵抗値を有すると必ず
発振し、電源電流測定装置が正常に動作しなくなるとい
う問題がある。この発振を防止するためには、帰還型増
幅器の出力端子及びＤＵＴの間に、正抵抗値を有する抵
抗器を接続し、ＤＵＴの負抵抗値との合計抵抗値を正に
する。2. Description of the Related Art A power supply current measuring device for outputting a DC voltage to a device under test in order to obtain a voltage-current characteristic of a device under test (hereinafter referred to as a DUT) which is a device under test or a circuit under test,
Usually, a feedback amplifier is used at its output. But,
This feedback amplifier has a problem that the oscillation always occurs when the DUT has a negative resistance value, and the power supply current measuring device does not operate normally. In order to prevent this oscillation, a resistor having a positive resistance is connected between the output terminal of the feedback amplifier and the DUT, and the total resistance of the DUT and the negative resistance is made positive.
【０００３】[0003]
【発明が解決しようとする課題】図２は、電源電流測定
装置１０の出力端子及びＤＵＴ１２の間に発振防止用の
抵抗器１４を接続した回路図を示す。電源電流測定装置
１０は、演算増幅器１６、電流検出用抵抗器１８及び減
算回路である電圧検出器２０を含む。演算増幅器１６の
非反転入力端子には入力電圧ＶＩＮが供給される。既知
の抵抗値ｒである電流検出用抵抗器１８の一端は、演算
増幅器１６の出力端子に接続され、他端は演算増幅器１
６の反転入力端子に接続されて、演算増幅器１６及び抵
抗器１８は帰還型増幅器を構成する。抵抗器１８の両端
電圧は、電圧検圧検出器２０で検出され、その出力電圧
Ｖｄを抵抗値ｒでわり算して、ＤＵＴ１２に流れる電流
値を測定できる。FIG. 2 shows a circuit diagram in which a resistor 14 for preventing oscillation is connected between the output terminal of the power supply current measuring device 10 and the DUT 12. The power supply current measuring device 10 includes an operational amplifier 16, a current detecting resistor 18, and a voltage detector 20 as a subtraction circuit. The input voltage VIN is supplied to a non-inverting input terminal of the operational amplifier 16. One end of the current detecting resistor 18 having a known resistance value r is connected to the output terminal of the operational amplifier 16, and the other end is connected to the operational amplifier 1.
6, the operational amplifier 16 and the resistor 18 constitute a feedback amplifier. The voltage across the resistor 18 is detected by the voltage detection detector 20, and the output voltage Vd can be divided by the resistance value r to measure the current value flowing through the DUT 12.
【０００４】抵抗器１４は電圧降下を生じさせ、電源電
流測定装置の入力電圧ＶINに対してＤＵＴ１２への出力
電圧ＶOUTが比例しない。そこで、ＤＵＴ１２に所望の
電圧ＶOUTを供給するには、例えば、電圧ＶOUTを電圧測
定器で測定しながら入力電圧ＶINを変化させて電圧ＶOU
Tを設定するなど、設定が面倒になる。The resistor 14 causes a voltage drop, and the output voltage VOUT to the DUT 12 is not proportional to the input voltage VIN of the power supply current measuring device. In order to supply the desired voltage VOUT to the DUT 12, for example, the input voltage VIN is changed while measuring the voltage VOUT with a voltmeter, and the voltage VOU is changed.
Setting is complicated, such as setting T.
【０００５】したがって、本発明の目的は、出力部にＤ
ＵＴの負抵抗を補償する抵抗器を含み、この抵抗器を介
した出力電圧が入力電圧に比例する電源電流測定装置の
提供にある。Therefore, an object of the present invention is to provide a D
It is an object of the present invention to provide a power supply current measuring device including a resistor for compensating a negative resistance of a UT, and an output voltage via the resistor being proportional to an input voltage.
【０００６】[0006]
【課題を解決するための手段及び作用】本発明は、被測
定物に所定電圧を供給したときに被測定物に流れる電流
値を測定する電源電流測定装置を提供する。加算増幅器
は、演算増幅器と、この演算増幅器の非反転入力端子に
接続された第１及び第２入力端子と、演算増幅器の反転
入力端子に接続された出力端子とを有し、第１及び第２
入力端子に夫々入力される第１及び第２入力電圧を加算
し第１増幅率Ａ１で増幅する。第１抵抗器は、既知の抵
抗値ｒを有し、演算増幅器の出力端子と加算増幅器の出
力端子との間に接続され、加算増幅器が供給する電流を
電圧に変換して加算増幅器が供給する電流値Ｉの検出に
利用される。電源手段は、ＣＰＵなどの制御手段の制御
に基いて加算増幅器の第１入力端子に第１入力電圧を供
給する。第２抵抗器は、既知の抵抗値Ｒを有し、加算増
幅器の出力端子及び被測定物間に接続され、被測定物が
負抵抗値になった場合の加算増幅器の発振を防止する。
電圧検出回路は、第１抵抗器の両端間電圧を検出し、こ
れによって加算増幅器が供給する電流に比例した電圧を
生成する。増幅器は、電圧検出回路の出力電圧を第２増
幅率Ａ２で増幅して加算増幅器の第２入力端子に第２入
力電圧として供給する。このとき、第２入力電圧が第２
抵抗器Ｒの両端間電圧を第１増幅率Ａ１でわり算した
値、即ちＲ・Ｉ／Ａ１になるように、増幅器の増幅率Ａ
２をＡ２＝Ｒ／ｒ・Ａ１に設定している。これにより加
算増幅器の出力電圧ＶＡは、ＶＡ＝Ａ１・ＶＩＮ＋Ｒ・
Ｉとなるので、電源電流測定装置の出力電圧ＶＯＵＴは
第２抵抗器による電圧降下Ｒ・Ｉにより、ＶＯＵＴ＝Ａ
１・ＶＩＮとなり、第２抵抗器（補償用抵抗器）の抵抗
値に依存しなくなる。SUMMARY OF THE INVENTION The present invention provides a power supply current measuring device for measuring a value of a current flowing through a device under test when a predetermined voltage is supplied to the device under test. The summing amplifier has an operational amplifier, first and second input terminals connected to a non-inverting input terminal of the operational amplifier, and an output terminal connected to an inverting input terminal of the operational amplifier. 2
The first and second input voltages respectively input to the input terminals are added and amplified at a first amplification factor A1. The first resistor has a known resistance value r, is connected between the output terminal of the operational amplifier and the output terminal of the summing amplifier, converts the current supplied by the summing amplifier into a voltage, and supplies the voltage by the summing amplifier. It is used for detecting the current value I. The power supply supplies a first input voltage to the first input terminal of the summing amplifier under the control of control means such as a CPU. The second resistor has a known resistance value R, is connected between the output terminal of the summing amplifier and the device under test, and prevents oscillation of the summing amplifier when the device under test has a negative resistance value.
The voltage detection circuit detects a voltage between both ends of the first resistor, and thereby generates a voltage proportional to the current supplied by the summing amplifier. The amplifier amplifies the output voltage of the voltage detection circuit at the second amplification factor A2 and supplies the output voltage to the second input terminal of the addition amplifier as the second input voltage. At this time, the second input voltage becomes the second input voltage.
The amplification factor A of the amplifier is set so as to obtain a value obtained by dividing the voltage between both ends of the resistor R by the first amplification factor A1, that is, R · I / A1.
2 is set to A2 = R / r · A1. As a result, the output voltage VA of the summing amplifier becomes VA = A1 · VIN + R ·
I, the output voltage VOUT of the power supply current measuring device is VOUT = A due to the voltage drop RI by the second resistor.
1 · VIN, and does not depend on the resistance value of the second resistor (compensation resistor).
【０００７】[0007]
【実施例】図１は、本発明の電源電流測定装置を示す回
路図である。ＣＰＵ２２は、ホスト・コンピュータ又は
キーボードからの入力命令に従い、バス２４を介してデ
ジタル・アナログ変換器（以下ＤＡＣという）２６にデ
ジタル・データを供給し、アナログ・デジタル変換器
（以下ＡＤＣという）２８からデジタル・データを受け
取り、測定に必要な処理を行う。ＣＰＵ２２により得ら
れた測定結果は、陰極線管の如き表示器３０に表示され
る。FIG. 1 is a circuit diagram showing a power supply current measuring device according to the present invention. The CPU 22 supplies digital data to a digital-to-analog converter (hereinafter, referred to as DAC) 26 via a bus 24 in accordance with an input command from a host computer or a keyboard. Receives digital data and performs necessary processing for measurement. The measurement results obtained by the CPU 22 are displayed on a display 30 such as a cathode ray tube.
【０００８】デジタル・アナログ変換器（電源手段）２
６は、ＣＰＵ（制御手段）２２からの入力デジタル・デ
ータに応じてアナログ入力電圧ＶＩＮを発生する。加算
増幅器５０は、演算増幅器３２と、抵抗器３４、３６、
３８、４０、４２、４４及び４６と、緩衝増幅器４８を
含み、抵抗器３４及び３８夫々の一端（第１及び第２端
子）で第１入力電圧及び第２入力電圧を受けてこれらを
加算し増幅する。この場合では、抵抗器３４を介して第
１入力電圧としてアナログ入力電圧ＶＩＮを受ける。抵
抗器３４及び３８の他端は、演算増幅器３２の非反転入
力端に共通に接続される。抵抗器３６の一端は接地さ
れ、他端は演算増幅器３２の非反転入力端に接続され
る。抵抗器４０、４２及び４４の一端は、演算増幅器３
２の反転入力端子に接続され、抵抗器４０及び４２の他
端は共に接地される。抵抗器４６の一端は、演算増幅器
３２の出力端子に接続され、他端は緩衝増幅器４８を介
して抵抗器４４の他端に接続される。なお、抵抗器４６
の他端（演算増幅器３２の出力端子に接続されていない
端子）が加算増幅器５０の出力端子となる。抵抗器３
４、３８、４０及び４２は等しい抵抗値Ｒ１を有し、抵
抗器４４及び３６は等しい抵抗値Ｒ２とを有し、抵抗器
４６は電流検出用抵抗器であり正確な抵抗値ｒを有す
る。この様に構成した加算増幅器５０は、抵抗器３４及
び３８に供給される電圧を加算し、抵抗器４０及び４２
に供給される電圧を減算する加減算増幅器であるが、抵
抗器４０及び４２に供給される電圧は０Ｖであるので結
果的に加算増幅器として働き、第１及び第２入力端子に
供給された電圧を加算し、且つ加算電圧値を増幅率Ａ１
＝Ｒ２／Ｒ１で増幅する。Digital-to-analog converter (power supply means) 2
6 generates an analog input voltage VIN according to input digital data from the CPU (control means) 22. Addition
The amplifier 50 includes an operational amplifier 32 and resistors 34, 36,
38, 40, 42, 44 and 46 and the buffer amplifier 48
And one end of each of the resistors 34 and 38 (first and second ends)
Receiving the first input voltage and the second input voltage at
Add and amplify. In this case, the resistor 34
An analog input voltage VIN is received as one input voltage. Usually
The other ends of the resistors 34 and 38 are connected to the non-inverting input of the operational amplifier 32.
Commonly connected to the force end. One end of the resistor 36 is grounded.
The other end is connected to the non-inverting input terminal of the operational amplifier 32.
You. One ends of the resistors 40, 42 and 44 are connected to the operational amplifier 3
2, and the other ends of the resistors 40 and 42 are both grounded. One end of the resistor 46 is connected to the output terminal of the operational amplifier 32, and the other end is connected to the other end of the resistor 44 via the buffer amplifier 48. The resistor 46
(Not connected to the output terminal of the operational amplifier 32)
Terminal) is the output terminal of the summing amplifier 50. Resistor 3
4, 38, 40, and 42 have equal resistance R1, resistors 44 and 36 have equal resistance R2, and resistor 46 is a current sensing resistor and has an accurate resistance r. The summing amplifier 50 configured in this manner adds the voltages supplied to the resistors 34 and 38, and adds the resistors 40 and 42.
However, since the voltage supplied to the resistors 40 and 42 is 0 V, the amplifier functions as an addition amplifier, and the voltage supplied to the first and second input terminals is reduced. Add and add the added voltage value to the amplification factor A1
= Amplify by R2 / R1.
【０００９】抵抗器４６の他端である加算増幅器５０の
出力端子及び本発明の電源電流測定装置の出力端子５４
間には、抵抗器５２が接続され、出力端子５４及び接地
間にはＤＵＴ５６が接続される。ＤＵＴ５６が有する負
抵抗により帰還型増幅器である加算増幅器５０が発振す
るのを防止するために、抵抗器５２はＤＵＴ５６の負抵
抗値を打ち消す正抵抗値Ｒを有する。この抵抗値Ｒは、
抵抗器５２の正抵抗値及びＤＵＴ５６の負抵抗値の合計
値が正に安定し、且つ抵抗器５２による電圧降下を最小
限にする値を選択することが望ましい。The output terminal of the summing amplifier 50, which is the other end of the resistor 46, and the output terminal 54 of the power supply current measuring device of the present invention.
A resistor 52 is connected between them, and a DUT 56 is connected between the output terminal 54 and the ground. The resistor 52 has a positive resistance value R that cancels the negative resistance value of the DUT 56 in order to prevent the negative amplifier of the DUT 56 from oscillating due to the negative resistance of the DUT 56. This resistance value R is
It is desirable to select a value in which the sum of the positive resistance of the resistor 52 and the negative resistance of the DUT 56 is positively stable and minimizes the voltage drop due to the resistor 52.
【００１０】抵抗器４６の両端電圧は、演算増幅器５
８、抵抗器６０、６２、６４及び６６を含む減算回路６
８で検出される。抵抗器４６の演算増幅器３２側の一端
は緩衝増幅器７０及び抵抗器６０を介して演算増幅器５
８の非反転入力端子に接続され、抵抗器４６の他端は緩
衝増幅器７２及び抵抗器６２を介して演算増幅器５８の
反転入力端子に接続される。抵抗器６４は演算増幅器５
８の非反転入力端子及び接地間に接続され、抵抗器６６
は演算増幅器５８の反転入力端子及び出力端間に接続さ
れる。抵抗器６０、６２、６４及び６６は等しい抵抗値
を有し、その結果、減算増幅器６８は、抵抗器４６の両
端間電圧に等しい電圧を出力する。緩衝増幅器４８、７
０及び７２の高入力インピーダンスにより、抵抗器４６
に流れる電流Ｉと等しい電流が抵抗器５２及びＤＵＴ５
６に流れる。抵抗器４６の両端電圧はｒＩ（Ｖ）であ
り、減算回路６８の出力電圧ＶDは、ＶD＝ｒＩ（Ｖ）と
なる。The voltage across the resistor 46 is determined by the operational amplifier 5
8, subtraction circuit 6 including resistors 60, 62, 64 and 66
8 is detected. One end of the resistor 46 on the operational amplifier 32 side is connected via the buffer amplifier 70 and the resistor 60 to the operational amplifier 5.
The other end of the resistor 46 is connected to the inverting input terminal of the operational amplifier 58 via the buffer amplifier 72 and the resistor 62. The resistor 64 is connected to the operational amplifier 5
8 is connected between the non-inverting input terminal of C.
Is connected between the inverting input terminal and the output terminal of the operational amplifier 58. Resistors 60, 62, 64 and 66 have equal resistance values, so that subtraction amplifier 68 outputs a voltage equal to the voltage across resistor 46. Buffer amplifiers 48, 7
Due to the high input impedance of 0 and 72,
The current equal to the current I flowing through the resistor 52 and the DUT 5
Flow to 6. The voltage across the resistor 46 is rI (V), and the output voltage VD of the subtraction circuit 68 is VD = rI (V).
【００１１】減算増幅器６８の出力電圧ＶＤは、ＡＤＣ
２８に供給されてＶＤに相当するデジタル値に変換され
た後、ＣＰＵ２２に送られる。ＣＰＵ２２は、ＶＤをｒ
でわり算して電流値Ｉを求める。一方、出力電圧ＶＤ
は、演算増幅器７４、抵抗器７６、７８、８０及び８２
を含む正相増幅器８４の入力端に供給される。正相増幅
器８４では、電圧ＶＤは抵抗器７６を介して演算増幅器
７４の非反転入力端子に接続される。抵抗器７８は、演
算増幅器７４及び接地間に接続される。抵抗器８０及び
８２の一端は演算増幅器７４の反転入力端子に接続さ
れ、抵抗器８０の他端は接地され、抵抗器８２の他端
は、演算増幅器７４の出力端子に接続される。抵抗器７
６及び８０は等しい抵抗値Ｒ３を有し、抵抗器７８及び
８２は等しい抵抗値Ｒ４を有し、その結果、正相増幅器
６４の増幅率Ａ２は、Ａ２＝Ｒ４／Ｒ３となる。この正
相増幅器８４の出力端子は、加算増幅器５０の第２入力
端子である抵抗器３８の一端に接続される。The output voltage VD of the subtraction amplifier 68 is calculated by an ADC
After being supplied to the CPU 28 and converted into a digital value corresponding to VD, the digital value is sent to the CPU 22. The CPU 22 sets VD to r
To obtain a current value I. On the other hand, the output voltage VD
Are operational amplifiers 74, resistors 76, 78, 80 and 82
Are supplied to the input terminal of a positive-phase amplifier 84 including In the positive-phase amplifier 84, the voltage VD is connected to the non-inverting input terminal of the operational amplifier 74 via the resistor 76. Resistor 78 is connected between operational amplifier 74 and ground. One ends of the resistors 80 and 82 are connected to the inverting input terminal of the operational amplifier 74, the other end of the resistor 80 is grounded, and the other end of the resistor 82 is connected to the output terminal of the operational amplifier 74. Resistor 7
6 and 80 have equal resistance R3, and resistors 78 and 82 have equal resistance R4, so that the amplification A2 of positive-phase amplifier 64 is A2 = R4 / R3. The output terminal of the positive-phase amplifier 84 is connected to one end of the resistor 38, which is the second input terminal of the summing amplifier 50.
【００１２】加算増幅器５０の他方の入力端子に供給さ
れる正相増幅器８４の出力電圧をＶIN’とすると、加算
増幅器５０の出力電圧ＶAは、 ＶA＝Ａ1（ＶIN＋ＶIN’） ・・・（１） となる。一方、減算増幅器６８の出力電圧ＶD＝ｒＩは
正相増幅器８４で増幅されて、電圧ＶIN’は、 ＶIN’＝Ａ2・ｒＩ ・・・（２） となる。ここで、本発明の特徴は、 ＶIN’＝Ｒ・Ｉ／Ａ1 ・・・（３） となるように、Ａ2の値を設定することである。そのた
めに、上述の抵抗値Ｒ1、Ｒ2、Ｒ3及びＲ4を、Ｒ／ｒ＝
Ｒ2・Ｒ4／Ｒ1・Ｒ3の関係に選択することで、Ａ2＝Ｒ
／（ｒ・Ａ1）に設定する。式（３）を式（１）に代入
すると、 ＶA ＝Ａ1｛ＶIN＋（Ｒ・Ｉ／Ａ1）｝ ・・・（４） ＝Ａ1・ＶIN＋Ｒ・Ｉ となる。また、ＶAは、 ＶA＝ＶOUT＋ＲＩ ・・・（５） であるので、式（４）＝式（５）を解くと、 ＶOUT＝Ａ1・ＶIN となり、増幅率Ａ1＝Ｒ2／Ｒ1で、出力電圧ＶOUTは入力
電圧ＶINに比例することになる。Assuming that the output voltage of the positive-phase amplifier 84 supplied to the other input terminal of the summing amplifier 50 is VIN ', the output voltage VA of the summing amplifier 50 is: VA = A1 (VIN + VIN') (1) Becomes On the other hand, the output voltage VD = rI of the subtraction amplifier 68 is amplified by the positive-phase amplifier 84, and the voltage VIN 'becomes VIN' = A2.rI (2). Here, a feature of the present invention is that the value of A2 is set so that VIN '= R.I / A1 (3). For this purpose, the above-mentioned resistance values R1, R2, R3 and R4 are set to R / r =
By selecting the relationship of R2 / R4 / R1 / R3, A2 = R
/ (R · A1). By substituting equation (3) into equation (1), VA = A1 {VIN + (RI / A1)} (4) = A1VIN + RI Further, since VA is VA = VOUT + RI (5), solving Equation (4) = Equation (5) gives VOUT = A1 · VIN, the amplification factor A1 = R2 / R1, and the output voltage VOUT Is proportional to the input voltage VIN.
【００１３】[0013]
【発明の効果】本発明の電源電流測定装置によれば、Ｄ
ＵＴの負抵抗による発振を防止するための補償用抵抗器
（第２抵抗器）を介してＤＵＴに電圧を供給する際に、
補償用抵抗器による電圧降下に関係なく、入力電圧に比
例した出力電圧をＤＵＴに供給することができる。According to the power supply current measuring device of the present invention, D
Compensation resistor to prevent oscillation due to negative resistance of UT
When supplying a voltage to the DUT via the (second resistor) ,
An output voltage proportional to the input voltage can be supplied to the DUT regardless of the voltage drop caused by the compensation resistor.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の電源電流測定装置を示す回路図。FIG. 1 is a circuit diagram showing a power supply current measuring device according to the present invention.
【図２】従来の電源電流測定装置の一部を示す回路図。FIG. 2 is a circuit diagram showing a part of a conventional power supply current measuring device.
２２ 制御手段 ２６ 電源手段 ３２ 演算増幅器 ４６ 第１抵抗器 ５０ 加算増幅器 ５２ 第２抵抗器 ６８ 電圧検出回路 ８４ 増幅器 Reference Signs List 22 control means 26 power supply means 32 operational amplifier 46 first resistor 50 addition amplifier 52 second resistor 68 voltage detection circuit 84 amplifier
Claims (1)
記被測定物に流れる電流値を測定する電源電流測定装置
であって、 演算増幅器と、該演算増幅器の非反転入力端子に接続さ
れた第１及び第２入力端子と、上記演算増幅器の反転入
力端子に接続された出力端子とを有し、上記第１及び第
２入力端子に夫々入力される第１及び第２入力電圧を加
算し第１増幅率で増幅する加算増幅器と、 上記演算増幅器の出力端子と上記加算増幅器の上記出力
端子との間に接続された電流検出用第１抵抗器と、 制御手段の制御に基いて上記加算増幅器の上記第１入力
端子に上記第１入力電圧を供給する電源手段と、 上記加算増幅器の上記出力端子及び上記被測定物間に接
続された第２抵抗器と、 上記第１抵抗器の両端間電圧を検出する電圧検出回路
と、 該電圧検出回路の出力電圧を第２増幅率で増幅して上記
加算増幅器の上記第２入力端子に上記第２入力電圧とし
て供給する増幅器とを具え、 上記第２入力電圧が上記第２抵抗器の両端間電圧を上記
第１増幅率でわり算した値になるように、上記増幅器の
上記第２増幅率を設定したことを特徴とする電源電流測
定装置。1. A power supply current measuring device for measuring a current value flowing through a device under test when a predetermined voltage is supplied to the device under test, comprising: an operational amplifier connected to a non-inverting input terminal of the operational amplifier. First and second input terminals, and an output terminal connected to the inverting input terminal of the operational amplifier, and sums the first and second input voltages input to the first and second input terminals, respectively. A summing amplifier for amplifying at a first amplification factor; a first current detection resistor connected between an output terminal of the operational amplifier and the output terminal of the summing amplifier; Power supply means for supplying the first input voltage to the first input terminal of the summing amplifier; a second resistor connected between the output terminal of the summing amplifier and the device under test; A voltage detection circuit for detecting a voltage between both ends; An amplifier for amplifying the output voltage of the voltage detection circuit at a second amplification factor and supplying the amplified voltage to the second input terminal of the summing amplifier as the second input voltage, wherein the second input voltage is the voltage of the second resistor. A power supply current measuring device, wherein the second amplification factor of the amplifier is set to be a value obtained by dividing the voltage between both ends by the first amplification factor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26535792A JP2660889B2 (en) | 1992-09-08 | 1992-09-08 | Power supply current measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26535792A JP2660889B2 (en) | 1992-09-08 | 1992-09-08 | Power supply current measuring device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0688839A JPH0688839A (en) | 1994-03-29 |
| JP2660889B2 true JP2660889B2 (en) | 1997-10-08 |
Family
ID=17416057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26535792A Expired - Lifetime JP2660889B2 (en) | 1992-09-08 | 1992-09-08 | Power supply current measuring device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2660889B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100554690B1 (en) * | 2002-03-05 | 2006-02-24 | 주식회사 시스하이텍 | Test system and method of a power supply |
| US6956393B1 (en) * | 2004-05-26 | 2005-10-18 | Advantest Corporation | Source current measurement apparatus and test apparatus |
| WO2007061369A1 (en) * | 2005-11-23 | 2007-05-31 | Telefonaktiebolaget Lm Ericsson (Publ) | Pre-biased circuit for synchronous rectified power converters |
| JP6738236B2 (en) * | 2016-08-12 | 2020-08-12 | 東京エレクトロン株式会社 | Device inspection circuit, device inspection device and probe card |
-
1992
- 1992-09-08 JP JP26535792A patent/JP2660889B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0688839A (en) | 1994-03-29 |
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