JP2658923B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit,
Particularly, the ECL level and the pseudo ECL level (hereinafter, PECL level)
And a level conversion circuit for converting a signal level between the signal level and the signal level.

[0002]

2. Description of the Related Art A conventionally used ECL level (V
_OL変 換 -1.6V; V _OH ≒ -0.8V) to PECL level (V _OL ≒ + 3.4V; V _OH ≒ + 4.2V) or from PECL level to ECL level for level conversion The circuit was a level shift circuit using DC coupling as shown in FIG.

FIG. 3 is a diagram showing a conventional level conversion circuit, and is a circuit diagram for performing level conversion from a PECL level to an ECL level.

The configuration of the level conversion circuit shown in FIG. 3 will be described.
A signal output from the PECL level output circuit 31 using the power supply V _CC (V _CC = + 5 V) is supplied to the ECL level input circuit 34 using the power supply V _EE (V _EE = −5.2 V) via the PNP transistor 37. Is input to One terminal of the resistor 32 is grounded, and the other terminal is connected to the output signal of the PECL level output circuit 31 to pull down the output signal. The emitter of the PNP transistor 37 is connected to the output terminal of the PECL level output circuit 31, the collector is connected to the input terminal of the ECL level input circuit 34, and the base is connected to a predetermined voltage V _REF (V _REF is a constant value). I have. One terminal of the resistor 38 is connected to the power supply _VEE , and the other terminal is connected to an input signal to the ECL level input circuit 34 to pull up the input signal.

[0005]

In the conventional level conversion circuit, the operation speed of the level conversion circuit using the PNP transistor as shown in FIG. 3 is limited.
There is a disadvantage that it cannot be applied to GHz class signals. Further, a level conversion circuit using an NPN transistor or the like requires a large number of elements, so that there is a disadvantage that the circuit scale becomes large.

In view of the above, an object of the present invention is to provide a level conversion circuit capable of coping with a high frequency with low power consumption without complicating the circuit configuration.

[0007]

A level conversion circuit according to the present invention has a pseudo ECL level output circuit, an ECL level input circuit, one terminal connected to the pseudo ECL level output circuit, and the other terminal grounded. And a capacitor having one terminal connected to the pseudo ECL level output circuit and the other terminal connected to the ECL level input circuit, and a clamp circuit connected to the ECL level input circuit. Have.

In the above-mentioned level conversion circuit of the present invention, the pseudo ECL level output circuit outputs an ECL signal via the capacitor.
The clamp circuit is AC-coupled to a level input circuit, and has a DC regeneration function.

The level conversion circuit according to the present invention comprises an ECL level output circuit, a pseudo ECL level input circuit, and a resistor having one terminal connected to the ECL level output circuit and the other terminal connected to a predetermined power supply. And a capacitor having one terminal connected to the ECL level output circuit, the other terminal connected to the pseudo ECL level input circuit, and a clamp circuit connected to the pseudo ECL level input circuit.

The level conversion circuit according to the present invention is characterized in that the EC
An L level output circuit outputs the pseudo E through the capacitor.
The clamp circuit is AC-coupled to a CL level input circuit, and has a DC regeneration function.

[0011]

According to the level conversion circuit of the present invention having the above-described configuration, the pseudo ECL level output circuit uses the capacitor E as the output.
Since the clamp circuit is AC-coupled to the CL level input circuit and has a DC regeneration function, the values of V _OH and V _{OL in} the case of a mark rate of 1/2 with respect to a change in the mark rate are retained, and DC regeneration is performed. This makes it possible to realize a low power consumption level conversion circuit without complicating the circuit configuration. In addition, since the ECL level output circuit is AC-coupled to the pseudo ECL level input circuit via a capacitor and the clamp circuit has a DC regeneration function, V _OH when the mark rate is 1/2 with respect to fluctuations in the mark rate. , V _OL
, And DC regeneration is possible, and a level conversion circuit with low power consumption can be realized without complicating the circuit configuration. Furthermore, since a PNP transistor is not used, the present invention can be applied to a case where a high-frequency signal is handled.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a level conversion circuit according to the present invention will be described with reference to the drawings.

Since the PECL circuit operates on the power supply V _CC ,
The same power supply as the TTL circuit can be used, and the power supply V _CC
, It is possible to reduce the types of power supplies to be used. Therefore, the number of on-board power supplies used can be reduced, which is suitable for low power consumption. However, at present, the PECL circuit and the ECL circuit are mixedly used, and in such a case, the level conversion circuit of the present invention converts the output signal of the PECL circuit into the input signal of the ECL circuit or the output signal of the ECL circuit in such a case. It is used for level conversion of a signal into an input signal of a PECL circuit.

FIG. 1 is a diagram showing an embodiment of a level conversion circuit according to the present invention, and is a circuit diagram for performing level conversion from a PECL level to an ECL level. The configuration of the level conversion circuit shown in FIG. 1 will be described. P using power supply V _CC
Signal output from the ECL level output circuit 11 is inputted to the ECL level input circuit 14 to use the power V _EE through a capacitor 13. The output signal of the PECL level output circuit 11 is also connected to one terminal of the resistor 12, and the other terminal of the resistor 12 is grounded. Further, a clamp circuit 15 having a DC regeneration function is connected to the ECL level input circuit 14. In this embodiment, the simplest diode 16 is used as the clamp circuit 15. One of two resistors connected to both ends of the diode 16 is grounded, and the other is connected to the power supply _VEE . However, the connection destination is not limited to this, and depending on the connection destination, The function of the clamp circuit 15 does not change.

Next, the operation of the level conversion circuit shown in FIG. 1 will be described. Since the PECL level output circuit 11 is normally of an open-emitter output type, it is pulled down by the resistor 12, and becomes V _OL ≒ + 3.4 V; V _OH ≒ + 4.2 V, and outputs a signal having an amplitude of about 0.8 V. I do. Since the DC component of the output signal is cut off by the capacitor 13, the DC level changes with a transient phenomenon due to a change in the mark ratio of the output signal.

The voltage value of the input signal of the ECL level input circuit 14 is set by the clamp circuit 15 so as to be about -1.2 V when the mark ratio is 1/2. This value is ECL
Since the center voltage value of the level and the amplitude of the output signal of the PECL level output circuit 11 are 0.8 V, when the mark ratio is 1/2, V _OL ≒ -1.6 V; V _OH ≒ -0.
8V.

When the mark ratio is 1/12, the capacitor 13 is charged.
6 becomes conductive and the time constant when the capacitor 13 discharges the electric charge because the extremely small forward resistance r _f of the diode 16 is extremely small, the mark rate 1/2
In this case, the values of V _OL and V _OH can be held.

Furthermore, although the capacitor 13 is the direction in which the discharge when the mark ratio is 11/12, the diode 16 becomes a cutoff state, and reverse resistance r _b of the diode 16 capacitor 13 since very large charge The time constant when discharging is extremely large, and it is possible to maintain the values of V _OH and V _{OL in} the case of a mark ratio of １ ／.

As described above, in the clamp circuit 15 according to the present embodiment, V _OH and V _OH when the mark ratio is 1/2 with respect to the fluctuation of the mark ratio from about 1/12 to 11/12.
The value of _OL can be held, and DC regeneration is possible.

FIG. 2 is a diagram showing another embodiment of the level conversion circuit according to the present invention, and is a circuit diagram for performing level conversion from an ECL level to a PECL level. The configuration of the level conversion circuit shown in FIG. 2 will be described. A signal output from the ECL level output circuit 21 is input via a capacitor 23 to a PECL level input circuit 24 using a power supply V _CC . The output signal of the ECL level output circuit 21 is also connected to one terminal of the resistor 22, and the other terminal of the resistor 22 is connected to the power supply _VEE . Furthermore, PE
A CL circuit 25 having a DC regeneration function is connected to the CL level input circuit 24. In this embodiment, the simplest diode 26 is used as the clamp circuit 25.
You are using The two resistors connected to both ends of the diode 26 are connected, one of which is connected to the power supply V _CC and the other of which is grounded. However, the connection destination is not limited to this. The function of the clamp circuit 25 does not change.

The operation principle of the level conversion circuit shown in FIG. 2 is the same as that of the level conversion circuit shown in FIG.

Also in the clamp circuit 25 in this embodiment, the values of V _OH and V _{OL in} the case where the mark ratio is 1/2 with respect to the fluctuation of the mark ratio from about 1/12 to 11/12 can be held. It is possible to perform DC regeneration.

[0023]

As described above, the level conversion circuit of the present invention has a pseudo ECL level output circuit, an ECL level input circuit, one terminal connected to the pseudo ECL level output circuit, and the other terminal grounded. And a capacitor having one terminal connected to the pseudo ECL level output circuit and the other terminal connected to the ECL level input circuit, and a clamp circuit connected to the ECL level input circuit. The pseudo ECL level output circuit is AC-coupled to the ECL level input circuit via a capacitor, and the clamp circuit has a DC regeneration function. The values of V _OH and V _{OL at} the rate of 1/2 can be held and DC regeneration is possible, without complicating the circuit configuration and low power consumption. Has the effect that the level conversion circuit of FIG.

Further, an ECL level output circuit and a pseudo EC
An L-level input circuit, one terminal is connected to an ECL level output circuit, the other terminal is connected to a predetermined power supply, and a resistor is connected to one terminal to the ECL level output circuit, and the other terminal is connected to a pseudo terminal. A capacitor connected to the ECL level input circuit and a clamp circuit connected to the pseudo ECL level input circuit, wherein the ECL level output circuit is AC-coupled to the pseudo ECL level input circuit via the capacitor; Since the clamp circuit has a DC regeneration function, the values of V _OH and V _{OL in} the case of a mark rate of に 対 し て are retained with respect to a change of the mark rate from about 1/12 to about 11/12, and DC regeneration is performed. This makes it possible to realize a low power consumption level conversion circuit without complicating the circuit configuration.

Further, by not using a PNP transistor, there is an effect that the present invention can be applied even when a high-frequency signal of 1 GHz class is handled. From these facts, the practical value of the level conversion circuit of the present invention is very large.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a level conversion circuit according to the present invention.

FIG. 2 is a diagram showing another embodiment of the level conversion circuit according to the present invention.

FIG. 3 is a diagram showing a level conversion circuit in a conventional example.

[Explanation of symbols]

11, 31 PECL level output circuit 12, 22, 32, 38 resistor 13, 23 capacitor 14, 34 ECL level input circuit 15, 25 clamp circuit 16, 26 diode 21 ECL level output circuit 24 PECL level input circuit 37 PNP transistor V _CC Power supply (+ 5V) V _EE power supply (-5.2V)

Claims (2)

(57) [Claims] An ECL level input circuit is connected between a pseudo ECL level output circuit and an ECL level input circuit.
Level using a clamp circuit having a DC regeneration function.
In a level conversion circuit that performs level conversion, one terminal is connected to the pseudo ECL level output circuit, the other terminal is connected to a grounded resistor, one terminal is connected to the pseudo ECL level output circuit, and the other terminal is connected to the pseudo ECL level output circuit. and a capacitor terminal connected to said ECL level input circuit, the pseudo ECL level output circuit through the capacitor
AC-coupled to the ECL level input circuit
A level conversion circuit. 2. An ECL level output circuit and a pseudo ECL level circuit
Between the pseudo ECL level input circuit and the
Using a clamp circuit that is connected and has a DC regeneration function
In a level conversion circuit for performing level conversion, one terminal is connected to the ECL level output circuit,
One terminal is connected to a predetermined power supply,
Terminal is connected to the ECL level output circuit,
Is connected to the pseudo ECL level input circuit.
And the ECL level output circuit is connected via the capacitor.
AC coupled to the pseudo ECL level input circuit
A level conversion circuit.