JP2658232B2 - N-base counter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a configuration of a counter having a small number of gates (four transistors are counted as one gate).

[Conventional technology]

First, let's clarify the meaning of words. The synchronous counter is one in which the clock terminals of all flip-flops constituting the counter are connected in common, and the other is called an asynchronous counter. The logical counter is a counter which, when the output of each flip-flop constituting the counter is viewed as a binary number, increases sequentially by one from 0, and the counter which is not the same is called a non-logical counter. For example, considering a quaternary counter, (00) →
(01) → (10) → (11) → (00) is a logical counter, which is (00) → (01) → (11) → (1
It is the non-logical counter that moves from 0) to (00). The present invention deals with a logical counter.

Conventionally, most of the counters of ²ⁿ or more are 8th
Synchronous counters have been used as shown. FIG. 8 is an example of a 23-base counter. 101 is a counter input, 107 is a counter output, and 102 to 106 are flip-flops. 108 to 110 are AND gates, 111 to 114 are Exclusive OR gates, 115 to 119 are AND gates, and 120 is a NAND gate. While the output of the NAND gate 120 is high, the counter counts up by one at every falling edge of the counter input 101, and when the output of the NAND gate 120 goes low, all the D inputs of each flip-flop go low. At the next falling edge of the counter input 101, the counter becomes 0. NAND gate 1
20 becomes 0 when Q ₄ , Q ₂ , and Q ₁ are high, that is, when the counter becomes (Q ₄ , Q ₃ , Q ₂ , Q ₁ , Q ₀ ) = (10110). That is, the counter counts up from 0 to 1, 2, 3,..., And when it reaches 22, the output of the NAND gate 120 goes low, the counter returns to 0, and operates as a 23-base counter.

In general, ^if the counters other than the ^2n- base are configured in a synchronous manner, a counter having an arbitrary frequency division ratio can be designed in almost the same way as the 23-base counter in FIG. That is, when designing an N-ary counter, it is only necessary to change the NAND gate 120 in FIG. 8 so that the output becomes low at the time of N-1.

However, the conventional synchronous counter has a disadvantage that the number of gates increases in a method of designing a counter having an arbitrary frequency division ratio.

[Problems to be solved by the invention]

As a counter other than the 2 ^n- ary counter, a synchronous type has almost been used, but for the 2 ^n- ary counter, in addition to the synchronous type shown in FIG. 7 (b), an asynchronous type as shown in FIG. 7 (a) is used. Expression counters have also been used considerably.

Comparing the asynchronous hexadecimal counter of FIG. 7 (a) with the synchronous hexadecimal counter of FIG. 7 (b), it can be seen that the asynchronous type has a considerably smaller number of gates than the synchronous type. Although the asynchronous counter has a drawback that the operation speed is slow, when the operation speed does not matter much, the cost is reduced by the small number of gates, and the merit is very large. However, for non- ²ⁿ counters, such as the 23-ary counter in FIG. 8, no suitable asynchronous counter has been available. SUMMARY OF THE INVENTION An object of the present invention is to provide an inexpensive counter having an asynchronous counter having a small number of gates even for a counter which is not ^2n- ary.

[Means for solving the problem]

The N-ary counter of the present invention has a first input terminal and a first output terminal and has a division ratio of 2
In a binary counter and (A), a second input terminal and 2 ^n-1 +1 binary counter is a divide ratio and a second output terminal ^{2 n-1 +1 (B)} , third An input terminal, a third output terminal, and a frequency division ratio control terminal, the frequency division ratio of which can be switched between 2 ⁿ and 2 ^{n -1} and a 2 ⁿ / 2 ^{n -1} + decimal counter (C); In the N-ary counter using at least one of the following, a binary number obtained by binarizing N-1 is divided into blocks each from the lower (LSB) side to the bit where 1 first exists. A number is sequentially attached to the block from the upper (MSB) side, and the first block among the blocks to which the number is attached corresponds to the binary counter (A) when the number is 1 bit, and the number is 2 bits or more. At this time, the 2 ^n-1 + 1-ary counter (B) corresponds to the m-th block among the blocks to which the number is attached. When the lock is 1 bit, the binary counter (A) is corresponded. When the lock is 2 bits or more, the 2 ⁿ / 2 ^n-1 + 1-ary counter (C) is corresponded. , respectively cascaded to the block sequence in the reverse, when the m-th block 2 ⁿ / 2 ^n-1 +1 binary counter (C) corresponds, the 2 ⁿ / 2 ^n-1 +1 ary counter (C) The dividing ratio control terminal is characterized in that the logical product of all outputs of the counter corresponding to each block before the (m-1) -th block is input.

(However, N, n, and m are integers of 2 or more.) The operation of the present invention will be described with reference to FIG.

FIG. 1A shows an embodiment of the present invention, in which the synchronous 23-ary counter of FIG. 8 is realized asynchronously. Before explaining the operation of FIG. 1A, the configuration of the asynchronous logic counter of the present invention will be described first.

Step 1: To configure an N-ary counter First, N-1 is displayed in binary. [In the case of a 23-digit counter, N-1 = 22, and (Q ₄ , Q ₃ , Q ₂ , Q ₁ , Q ₀ ) = (10110). Step 2: Look at the binary display of N-1 from the bottom,
If '1' appears, divide it into blocks including '1'.
At this time, each block is composed of one '1' and zero or more '0's, and has the form of (10 ... 0). The first block, the second block,... [In the case of a 23-base counter, the first block is divided into three blocks, Q ₄ ,
Is Q _3, the _{(Q 4, Q 3) =} (10). The second block is Q
Is _{2, (Q2) = (1} ), the third block is Q ₁ Q _0, the _{(Q 1 Q 0) = (} 10). In the future, the above (1)
Those expressed as (0), (1), and (10) are referred to as block display of each block.

Step 3: First block is A type counter unit or B
Replace with a type counter unit.

(A) When the first block has only one bit and the block display is (1), the block is replaced by a binary counter. In this specification, a binary counter is referred to as an A-type counter unit.

(B) When the first block is 2 bits or more and the block display is (10 ... 0), if the number of bits in the block is n, it is replaced by a (2 ^n-1 +1) -ary counter. In this specification, the (2 ^n-1 +1) -ary counter will be referred to as a B-type counter unit.

[In the case of a 23-base counter, the first block has a block display of (10) and a ternary counter (B-type counter unit)
Replace with Step 4: The second and subsequent blocks are replaced with an A-type counter unit or a C-type counter unit.

(A) When the block after the second block has only one bit and the block display is (1), the block is replaced by a binary counter (A-type counter unit).

(B) When the blocks after the second block are 2 bits or more and the block display is (10... 0), assuming that the number of bits in the block is n, the frequency division ratio is 2 ⁿ and 2 ^n-1 +1. Replaced by a C-type counter unit with a street. In this specification, the following is called a C-type counter unit. That is, it has a division ratio control input and when this is low
It is a ^2n- ary counter, and when high, it becomes a ( ^2n-1 + 1) -ary counter, which is also referred to as ²ⁿ / ( ^2n-1 +
1) A binary counter is represented. [In the case of a 23-ary counter, the second block is indicated by block (1) and is replaced by an A-type counter unit (binary counter). The third block is (10) and is replaced by a C-type counter unit (4/3 ternary counter). Step 5: Each counter unit cascades using the output of the preceding counter unit as a clock input.
[In the 23-base counter, the output of the third block C-type counter unit is connected to the clock input of the second block A-type counter, and the output of the second block A-type counter unit is connected to the output of the first block B-type counter unit. Connect to clock input. Step 6: AND the outputs of all counter units downstream from itself to the division ratio control input of the C-type counter unit.
Input signal. [In the case of a 23-base counter, the division ratio control input of the C-type counter unit of the third block includes the first
A signal obtained by ANDing the output of the B-type counter unit of the block and the output of the A-type counter unit of the second block is input. The asynchronous logic type counter of the present invention can be configured by taking the above six steps into consideration. The former stage in the description is a block having a larger number when it is referred to as a block. That is, the former stage of the second block is the third block, and the latter stage is the first block.

Returning now to the description of the operation of the 23-base counter in FIG. 1 is a clock input to the counter, and 2 is an output of the counter. Reference numeral 6 denotes a C-type counter unit (a quaternary counter), 7 denotes an A-type counter unit (a binary counter), and 8 denotes a B-type counter unit (a ternary counter). Reference numeral 3 denotes a frequency division ratio control input of the C-type counter unit 6, and when this is low, the C-type counter unit 6
Is a quaternary counter, and when high, a ternary counter. Reference numeral 4 denotes an output of the C-type counter unit 6, which is an input of the A-type counter unit 7. Reference numeral 5 denotes an output of the A-type counter unit 7, which is an input of the B-type counter unit 8. Reference numeral 9 denotes an AND gate, which performs an AND operation on the output of the A-type counter unit 7 and the output of the B-type counter unit 8, and uses the result as the frequency division ratio control input 3 of the C-type counter unit 6. 10 to 14 is a flip-flop, it referred to as FF ₀ ~FF _4. Also it will be referred to as the Q output of each flip-flop with Q ₀ ~Q _4.

The B-type counter unit 8 of the first block is a ternary counter, and Q ₃ and Q ₄ change with respect to the clock input 5 (= Q ₂ ) as shown in (3) of FIG. 1B. A type counter unit 7 of the second block is a binary counter, a change in Q ₂ as (2) of FIG. 1 with respect to the clock input 4 (= Q ₁₎ (b). The C-type counter unit 6 of the third block is a 4/3 counter, and the frequency division ratio control input 3 (=
When S) is low, it operates as a quaternary counter, and when the frequency division ratio control input 3 (= S) is high, it operates as a ternary counter. When S is low, Q ₀ and Q ₁ are clock input 1 (=
I) changes as shown in FIG. 1 (b) (1) (i), and when S is high, (i) in FIG. 1 (b) (1)
It changes like i). When the operations of the respective counter units in FIG. 1B are connected, the operation of the entire counter in FIG. 1A is as shown in FIG. 1C. That is,
In FIG. 1A, S is low until Q ₄ = Q ₂ = 1, and the C-type counter unit 6 of the third block operates as a quaternary counter. The operation from T ₀ to T ₁₉ is the same as that of the 2 ⁿ counter. At T ₂₀
Q ₄ = Q ₂ = 1, and the third block operates as a ternary counter. That is after you transition from T ₂₀ and T _21, T _22, Q
_0, Q ₁ is returned to _{(Q 0, Q 1) =} (0,0). In this case Q ₁ That is, since the clock input 4 of the second block changes from high to low, Q ₂ is also inverted from 1 to 0. Q ₂ is a clock input of the first block, this time (Q _3, Q ₄₎ is (0,
Transition from (1) to (0,0). In this way after all, the next T ₂₂ is Q
₈ to Q ₄ all 0, the counter returns to T _0, as a whole operates as a 23-ary counter.

〔Example〕

FIG. 2A shows an embodiment of the A-type counter unit, the B-type counter unit and the C-type counter unit.
In (1) of FIG. 2 (a), the upper part of the figure shows a symbol, and the lower part shows a circuit diagram (the same applies hereinafter). I is the clock input of each counter unit, and O is the output of the counter unit. In the C-type counter unit of (3) in FIG. 2 (a), S is a frequency division ratio control input. The B-type counter unit and the C-type counter unit show a general form in the case of n bits, where n = 2, 3,
Circuit diagrams for cases 4 and 5 are as shown in FIG. 3 and FIG. For each counter unit, symbols are shown together with actual circuit examples.

The operation of the B-type counter unit of (2) in FIG. 2A and the C-type counter unit of (3) in FIG. 2A will be briefly described. FIG. 2 (b) shows the operation of the B-type counter unit. Marked FF ₀ ~FF _n-1 of the flip-flops constituting the B-type counter unit from lower in the order in the second view of (a) (2), the Q output of each flip-flop Q ₀ ~Q _n-1, D input the will be referred to as Q ₀ ~Q _n-1. While Q _n-1 = 0 Next, to configure the FF ₀ to ff _n-2 of the n-1 flip-flops ripple counter, while the counter as of FIG. 2 (b) from T ₀ to T2 ^n-1 _-1 1 Count up by one. D _n-1 is 1 only when Q ₀ to Q _n-2 are all 1
Therefore, it becomes ¹ for the first time at T ₂ ^n-1 . At this time, Q ₀ to Q _n−2 all return to 0. Q at T ₂ ^n-1
_{When n-1} = 1, And D _n-1 is also 0, so that T ₂ ^n-1 is followed by Q _{0 to} Q _n-1
All become 0. That is, after T ₂ ^n-1 returns to T ₀ ,
The counter operates as a 2 ^n-1 +1 counter.

FIG. 2C shows the operation of the C-type counter unit. Figure 2 (a) (3) The second diagram (a) of (2) as well as each flip-flop and the Q output thereof at, D enter each _{FF 0 ~FF n-1, Q} 0 ~Q n _-1, D ₀ ~
D _n-1 . S is a frequency division ratio control input. S
= 0, That is, FF _{0 to} FF _n-2 are ripple counters,
_n-1 is inverted when the Q ₀ to Q _n-2 are all 1, because at other times to the same value, after all, FF ₀ to ff _n-1 becomes 2 ^n-ary counter, Figure 2 It operates as in (C) (1). When S = 1 Becomes Also, D _n-1 = ｛(Q ₀ · Q ₁ ····· Q _n-2 ) Q _n-1 ｝ · _{Next, Q 0 · Q 1 · ...} · Q when _n-2 · Q _n-1 is considered to be actually a state that does not appear in _{D n-1 = Q 0 ·} Q 1 · ... · Q n-2
Becomes That is, when S = 1, the C-type counter unit becomes the same 2 ^n-1 + 1-ary counter as the B-type counter unit, and operates as shown in (2) of FIG. 2 (C).

The asynchronous logic type counting according to the present invention can be implemented by the A-type counter unit, the B-type counter unit and the C-type counter unit described above.
It is obtained by combining a mold counter unit. 5th Embodiment from Binary Counter to 32nd Counter
Figures (a) to (d) are shown. The embodiment is expressed using the symbols shown in FIGS. 2 (a), 3 and 4. The configuration of each counter in the embodiment follows the configuration of the above-described six steps.

(Effects of Embodiment) FIGS. 6A and 6B show a comparison of the number of gates between the counter according to the present invention and the conventional synchronous counter. For example, looking at the 23-base counter, the conventional counter in FIG.
In contrast to the gate, the counter according to the invention in FIG.
There are 38 gates, about 30% fewer gates. Looking at the binary counter from the binary counter, the gate count is about 25% smaller on average.

At present, gate arrays and standard cells are very often used in electronic equipment, but in the case of gate arrays, etc., the number of gates and cost are almost proportional, and by using the counter according to the present invention, about 25% Costs can be reduced. Also, the counter is the basis of all electronic circuits, its application range is very wide, and the effect of the present invention seems to be very large.

FIGS. 6 (a) and 6 (b) show the configuration of the counter according to the present invention together with the comparison of the number of gates. The N-ary counter (N = 2 to 32) is represented by a binary number of N−1, and when it is seen from the lower side, when 1 appears, it is divided into blocks including 1 and each divided block is an A-type counter unit. , B-type counter unit or C-type counter unit. Based on this, the counters in FIGS. 5A to 5D are configured.

〔The invention's effect〕

As described above, according to the present invention, the number of counters can be reduced, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 (a) is a diagram showing an embodiment of the present invention for a 23-ary counter, and FIGS. 1 (b) and 1 (c) are explanatory diagrams of the operation thereof. FIG. 2 (a) is a diagram showing an embodiment of an A-type counter unit, a B-type counter unit, and a C-type counter unit which are important components of the counter of the present invention. FIG. 2C is a diagram for explaining the operation. FIGS. 3 (a) to 3 (d) are diagrams specifically showing an embodiment of a B-type counter unit and a C-type counter unit. FIGS. 5 (a) to 5 (d) are diagrams showing an embodiment of the present invention for a binary to hexadecimal counter. 6 (a) and 6 (b) are diagrams showing the configuration of the present invention and a comparison of the number of gates between the counter of the present invention and the conventional counter for a binary to hexadecimal counter. FIGS. 7A and 7B are diagrams showing a conventional hexadecimal counter.
FIG. 8 is a diagram showing an example of a conventional counter for a 23-base counter. 1 ... Counter clock input 2 ... Counter output 3 ... Division ratio control input 4 ... Third block output 5 ... Second block output 6 ... Third block (C-type counter unit) 7 ... Second block (A-type counter unit) 8 First block (B-type counter unit) 9 AND gate 10 to 14 Flip-flop 101 Clock input of counter 102 to 106 Flip-flop 107 …… Counter output 108 to 110, 115 to 119 …… AND gate 111 to 114 …… Exclusive OR gate 120 …… NAND gate

Claims (1)

(57) [Claims] 1. A binary counter (A) having a first input terminal and a first output terminal and having a division ratio of 2, and a second input terminal and a second output terminal. The division ratio is 2 ^n-1 +1 2
^n-1 +1 binary counter (B), and a third input terminal and the third output terminal and the frequency dividing ratio control terminal and dividing ratio has is 2 ⁿ and 2 ⁿ capable of switching and 2 ^n-1 / 2 ^n-1 + 1-ary counter (C) and at least one of the N-ary counters, wherein a binary number obtained by binarizing N-1 has 1 first from the lower (LSB) side. Up to the bits, each block is divided into one block, and a number is sequentially attached to each block from the upper side (MSB) side. The binary counter (A) is supported, and when the number of bits is 2 bits or more, the ^2n-1 + 1-ary counter (B) is used.
The m-th block among the blocks to which the numbers are attached corresponds to the binary counter (A) when the number is 1 bit, and the 2 ⁿ / 2 ⁿ⁻¹ +1 when the number is 2 bits or more. The corresponding counters are cascade-connected in reverse order of the block, and a 2 ⁿ / 2 ^n-1 + 1-ary counter (C) is provided in the m-th block. When it is supported, the logical product of all the outputs of the counters corresponding to each block before the (m-1) -th block is input to the division ratio control terminal of the 2 ⁿ / 2 ^n-1 +1 counter (C). An N-ary counter characterized by being processed. (Where N, n, and m are integers of 2 or more)