JP2657521B2 - Manufacturing method of thin film resonator - Google Patents

Manufacturing method of thin film resonator

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Publication number
JP2657521B2
JP2657521B2 JP63163125A JP16312588A JP2657521B2 JP 2657521 B2 JP2657521 B2 JP 2657521B2 JP 63163125 A JP63163125 A JP 63163125A JP 16312588 A JP16312588 A JP 16312588A JP 2657521 B2 JP2657521 B2 JP 2657521B2
Authority
JP
Japan
Prior art keywords
thin film
thin
silicon substrate
layer
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63163125A
Other languages
Japanese (ja)
Other versions
JPH0213109A (en
Inventor
寛 大橋
嘉彦 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP63163125A priority Critical patent/JP2657521B2/en
Publication of JPH0213109A publication Critical patent/JPH0213109A/en
Application granted granted Critical
Publication of JP2657521B2 publication Critical patent/JP2657521B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は薄膜共振部の内部歪応力を分散する構造を有
する薄膜共振子に関する。
Description: TECHNICAL FIELD The present invention relates to a thin film resonator having a structure for dispersing internal strain stress of a thin film resonator.

(従来の技術とその課題) 従来のこの種の素子を図面により説明する。(Prior art and its problems) A conventional element of this type will be described with reference to the drawings.

第3図は従来のこの種の薄膜共振子の断面図である。
11はシリコン基板、12はエピタキシャル層、13はSiO
2層、14は下部電極、15は圧電体材料であるZnO層、16は
上部電極である。この種の素子の動作原理は、下部電極
14及び上部電極16に高周波信号を加えることにより、圧
電体ZnO15は高周波信号の周期で伸縮を繰り返し、薄膜
共振部、即ちエピタキシャル層12、SiO2層13及び圧電体
15の厚さにより共振する。
FIG. 3 is a sectional view of a conventional thin film resonator of this type.
11 is a silicon substrate, 12 is an epitaxial layer, 13 is SiO
Two layers, 14 is a lower electrode, 15 is a ZnO layer which is a piezoelectric material, and 16 is an upper electrode. The principle of operation of this type of device is that the lower electrode
By applying a high-frequency signal to the upper electrode 16 and the upper electrode 16, the piezoelectric ZnO 15 repeats expansion and contraction at the cycle of the high-frequency signal, and the thin-film resonators, that is, the epitaxial layer 12, the SiO 2 layer 13, and the piezoelectric
Resonates with a thickness of 15.

この種の素子の製造方法は、ボロン等を高濃度にドー
プしたエピタキシャル層12を(100)シリコン基板11上
に形成し、このシリコン基板11の裏面を部分的にマスク
した後、異方性エッチング液にてシリコン基板11の裏面
よりエピタキシャル層12部分までエッチングを行う。次
に、SiO2層13をスパッタリング等で形成し、下部電極14
を真空蒸着法及びフォトリソグラフィ技術により形成す
る。さらにその上に圧電体15をスパッタリング等で形成
し、上部電極16を下部電極14と同様に形成することによ
り製造する。
This type of device is manufactured by forming an epitaxial layer 12 heavily doped with boron or the like on a (100) silicon substrate 11, partially masking the back surface of the silicon substrate 11, and then performing anisotropic etching. The liquid is etched from the back surface of the silicon substrate 11 to the epitaxial layer 12 portion. Next, an SiO 2 layer 13 is formed by sputtering or the like, and the lower electrode 14 is formed.
Is formed by a vacuum evaporation method and a photolithography technique. Further, a piezoelectric body 15 is formed thereon by sputtering or the like, and an upper electrode 16 is formed in the same manner as the lower electrode 14, thereby producing the piezoelectric element.

第4図はこの種の素子の他の例の断面図である。21は
シリコン基板、23は下部SiO2層、24は下部電極、25は圧
電体、26は上部電極、27は上部SiO2層、28は開口部、29
は薄膜共振部保持部である。次にその動作原理は、第1
図同様下部電極24及び上部電極26に加えられた高周波信
号により、圧電体25は伸縮を繰り返し、薄膜共振部、即
ち下部SiO2層23、圧電体25、及び上部SiO2層27の厚さに
より共振する。
FIG. 4 is a sectional view of another example of this type of element. 21 is a silicon substrate, 23 is a lower SiO 2 layer, 24 is a lower electrode, 25 is a piezoelectric body, 26 is an upper electrode, 27 is an upper SiO 2 layer, 28 is an opening, 29
Denotes a thin film resonance part holding part. Next, the principle of operation is as follows.
As shown in the figure, the high frequency signal applied to the lower electrode 24 and the upper electrode 26 causes the piezoelectric body 25 to repeatedly expand and contract, and the thickness of the thin film resonance part, that is, the lower SiO 2 layer 23, the piezoelectric body 25, and the upper SiO 2 layer 27 Resonate.

第4図の構造の製造方法は、開口部28をマスクし、シ
リコン基板21上に下部SiO2層23、下部電極24、圧電体2
5、上部電極26及び上部SiO2層27を第3図同様の方法に
て形成する。次に、マスクされた開口部28より異方性エ
ッチングし素子を製造する。
In the method of manufacturing the structure shown in FIG. 4, the opening 28 is masked and the lower SiO 2 layer 23, the lower electrode 24, the piezoelectric
5. An upper electrode 26 and an upper SiO 2 layer 27 are formed in the same manner as in FIG. Next, anisotropic etching is performed from the masked opening 28 to manufacture an element.

ここで、上記製造方法において一般に多層に薄膜を形
成する場合、例えばスパッタリング法にて形成する場合
では基板温度は約600℃になり、これを室温(約25℃)
に戻すと熱膨張差のため薄膜界面には歪応力が発生す
る。第3図の構造では薄膜共振部は厚み方向に対称であ
り、また第4図の構造では薄膜共振部は厚み方向に対称
であるが、薄膜共振部保持部29では非対称である。この
ように、第3図、第4図のように従来の薄膜共振子では
いずれも厚み方向に非対称な部分がある。厚み方向に非
対称であると、膜界面の歪応力が多層膜全体として打ち
消されず破壊しやすい欠点があった。
Here, when a thin film is generally formed in multiple layers in the above-described manufacturing method, for example, when the thin film is formed by a sputtering method, the substrate temperature is about 600 ° C., which is set to room temperature (about 25 ° C.)
When the temperature is returned to, a strain stress is generated at the thin film interface due to a difference in thermal expansion. In the structure of FIG. 3, the thin film resonator is symmetric in the thickness direction, and in the structure of FIG. 4, the thin film resonator is symmetric in the thickness direction, but in the thin film resonator holder 29, it is asymmetric. Thus, as shown in FIGS. 3 and 4, in the conventional thin-film resonator, there are portions that are asymmetric in the thickness direction. If it is asymmetrical in the thickness direction, there is a disadvantage that the strain stress at the film interface is not canceled out as a whole of the multilayer film and is easily broken.

上記した薄膜共振子では、素子作製時に蓄積する内部
応力により、薄膜共振部にたわみ、クラックの発生を充
分低減させることは難しかった。
In the above-described thin-film resonator, it has been difficult to sufficiently reduce bending and cracks in the thin-film resonator due to internal stress accumulated during device fabrication.

(課題を解決するための手段) 本発明は、上記問題点を解決するため、形成する薄膜
共振部の厚みの1/2以上の深さにシリコン基板を異方性
エッチングし、前記薄膜共振部の厚みの約1/2の深さを
残して前記エッチングした部分にエッチング材を埋め、
その上面において圧電体材料を上部電極と下部電極とで
挟み、前記上部電極と下部電極をSiO2層により挟み前記
薄膜共振部を形成し、前記シリコン基板のエッチング部
に埋められたエッチング材をエッチングすることにより
前記薄膜共振部とシリコン基板とを分離して、前記薄膜
共振部の厚み方向の中心面を前記シリコン基板の表面と
ほぼ同一とする。
(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides an anisotropic etching of a silicon substrate to a depth of 1/2 or more of the thickness of a thin film resonator to be formed. An etching material is buried in the etched portion, leaving a depth of about 1/2 of the thickness of the
On the upper surface thereof, a piezoelectric material is sandwiched between an upper electrode and a lower electrode, the upper electrode and the lower electrode are sandwiched by an SiO 2 layer to form the thin-film resonating portion, and the etching material embedded in the etching portion of the silicon substrate is etched. By doing so, the thin-film resonating portion and the silicon substrate are separated from each other, and the center plane in the thickness direction of the thin-film resonating portion is made substantially the same as the surface of the silicon substrate.

(実施例) 上記問題点を解決するためになされた本発明の薄膜共
振子の実施例を第1図の断面図により詳細に説明する。
31はシリコン基板、33は下部SiO2層、34は下部電極、35
は圧電体、36は上部電極、37は上部SiO2層、39は薄膜共
振部保持部、40は薄膜薄膜共振部とシリコン基板を分離
する空間層である。
(Embodiment) An embodiment of a thin-film resonator of the present invention made to solve the above problem will be described in detail with reference to the cross-sectional view of FIG.
31 is a silicon substrate, 33 is a lower SiO 2 layer, 34 is a lower electrode, 35
Is a piezoelectric body, 36 is an upper electrode, 37 is an upper SiO 2 layer, 39 is a thin film resonator holding section, and 40 is a space layer separating the thin film thin film resonator and the silicon substrate.

本発明の素子を動作させるためには、下部電極34と上
部電極36の間に高周波信号を加えることにより、圧電体
35は高周波信号の周期で伸縮を繰り返し、薄膜共振部、
即ち下部SiO2層33、圧電体35及び上部SiO2層37の厚さに
より共振する。
In order to operate the device of the present invention, a high-frequency signal is applied between the lower electrode
35 repeats expansion and contraction at the cycle of the high frequency signal,
That is, resonance occurs due to the thicknesses of the lower SiO 2 layer 33, the piezoelectric body 35, and the upper SiO 2 layer 37.

本発明の製造方法を第2図にて説明する。(100)シ
リコン基板31表面の一部をマスクした後、異方性エッチ
ングを行う(a)。エッチングされる形状は、(100)
シリコン基板31の場合、下方を向いた低角55度の四角錘
台をなす。薄膜共振部を形成するためシリコン基板31の
エッチング部をZnO等後で容易にエッチング出来る材料
(エッチング材)にて埋める(b)。この厚さは、エッ
チング深さから薄膜共振子の厚さの約1/2を引いた厚さ
にする。下部SiO2層33をスパッタリング等にて形成し、
下部電極34を真空蒸着法及びフォトリソグラフィ技術に
て形成する(c)。圧電体35をスパッタリング等で形成
し、エッチング法等でパターンニングする(d)。上部
電極36を下部電極34同様に形成し、上部SiO2層37をスパ
ッタリング等にて形成する(e)。薄膜共振部をマスク
し、下部SiO2層33及び、上部SiO2層37をフッ酸等にてエ
ッチングし、シリコンエッチング部に埋められたZnO等
エッチング材の端面に露出させる(f)。シリコンエッ
チング部に埋められたエッチング材のZnO層を希釈した
塩酸等にてエッチングし薄膜共振部とシリコン基板を分
離する空間層40を形成する(g)。この時、電極材料に
より挟まれたZnO等圧電材料及びさらにその上下面をSiO
2により挟んだ薄膜共振部は空間層40によりシリコン基
板31と分離され構成される。また、シリコン基板エッチ
ング部に埋められるエッチング材の厚さをエッチング深
さから薄膜共振部の厚さの約1/2を引いた厚さにするこ
とにより、薄膜共振部の中心面をシリコン基板31の表面
及びその延長線とほぼ同一にすることができる。
The manufacturing method of the present invention will be described with reference to FIG. (100) After masking a part of the surface of the silicon substrate 31, anisotropic etching is performed (a). The shape to be etched is (100)
In the case of the silicon substrate 31, a quadrangular frustum with a low angle of 55 degrees facing downward is formed. The etched portion of the silicon substrate 31 is filled with a material (etching material) that can be easily etched later, such as ZnO, to form a thin film resonance portion (b). This thickness is set to a value obtained by subtracting about 1/2 of the thickness of the thin film resonator from the etching depth. The lower SiO 2 layer 33 is formed by sputtering or the like,
The lower electrode 34 is formed by a vacuum evaporation method and a photolithography technique (c). The piezoelectric body 35 is formed by sputtering or the like, and is patterned by an etching method or the like (d). The upper electrode 36 is formed in the same manner as the lower electrode 34, and the upper SiO 2 layer 37 is formed by sputtering or the like (e). The lower SiO 2 layer 33 and the upper SiO 2 layer 37 are etched with hydrofluoric acid or the like while masking the thin film resonance section, and are exposed on the end face of the etching material such as ZnO embedded in the silicon etching section (f). The ZnO layer of the etching material buried in the silicon etching part is etched with diluted hydrochloric acid or the like to form a space layer 40 separating the thin film resonance part and the silicon substrate (g). At this time, the piezoelectric material such as ZnO sandwiched between the electrode materials and the upper and lower
The thin-film resonating portion sandwiched between the two is separated from the silicon substrate 31 by the space layer 40 and configured. Also, by setting the thickness of the etching material embedded in the silicon substrate etching portion to a thickness obtained by subtracting about half the thickness of the thin film resonance portion from the etching depth, the center plane of the thin film resonance portion can be formed on the silicon substrate 31. Surface and its extension line can be substantially the same.

この様に製造すると、通常電極薄膜の厚さは他の薄膜
と比較し充分薄いので、薄膜共振部の全体は厚み方向に
ほぼ対称となり膜界面の歪応力が多層膜全体では打ち消
し、たわみ、クラックの発生を著しく低減できる。
When manufactured in this way, the thickness of the electrode thin film is usually sufficiently thin compared to other thin films, so that the entire thin film resonator is almost symmetrical in the thickness direction, and the strain stress at the film interface cancels, warps, and cracks in the entire multilayer film. Can be significantly reduced.

またここではZnO等圧電体の上下面をSiO2層にて挟ん
だ構造のものを示したが、特に上下のSiO2層の無い薄膜
共振部を持つ薄膜共振子にても同様にたわみ、クラック
の発生を著しく低減できるのは明かである。
Also, here, a structure in which the upper and lower surfaces of a piezoelectric material such as ZnO are sandwiched between SiO 2 layers is shown, but the same applies to a thin film resonator having a thin film resonator having no upper and lower SiO 2 layers. It is clear that the occurrence of phenomena can be significantly reduced.

(発明の効果) 以上説明したように、本発明による薄膜共振子は薄膜
共振部の歪応力を分散させる構造及び製造法なので、従
来問題となっていた、たわみ、クラック等の発生を著し
く低減させる効果があり、機械的強度の高い、共振時の
特性劣化の少ない薄膜共振子を提供できる。
(Effect of the Invention) As described above, the thin-film resonator according to the present invention has a structure and a manufacturing method for dispersing the strain stress of the thin-film resonating portion. It is possible to provide a thin-film resonator that is effective, has high mechanical strength, and has little deterioration in characteristics at the time of resonance.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の薄膜共振子の断面図、第2図は本発明
の薄膜共振子の製造法の説明図、第3図及び第4図は従
来の薄膜共振子の断面図である。 11,21,31……Si基板、12……エピタキシャル層、13……
SiO2層、14,24,34……下部電極、15,25,35……圧電体、
16,26,36……上部電極、23,33……下部SiO2層、27,37…
…上部SiO2層、28……開口部、29,39……薄膜共振部保
持部、40……空間。
FIG. 1 is a cross-sectional view of a thin-film resonator of the present invention, FIG. 2 is an explanatory view of a method of manufacturing the thin-film resonator of the present invention, and FIGS. 3 and 4 are cross-sectional views of a conventional thin-film resonator. 11,21,31 ... Si substrate, 12 ... Epitaxial layer, 13 ...
SiO 2 layer, 14,24,34 …… Lower electrode, 15,25,35 …… Piezoelectric,
16,26,36 …… Upper electrode, 23,33 …… Lower SiO 2 layer, 27,37…
... upper SiO 2 layer, 28 ... opening, 29, 39 ... thin film resonator holding part, 40 ... space.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】形成する薄膜共振部の厚みの1/2以上の深
さにシリコン基板を異方性エッチングし、前記薄膜共振
部の厚みの約1/2の深さを残して前記エッチングした部
分にエッチング材を埋め、その上面において圧電体材料
を上部電極と下部電極とで挟み、前記上部電極と下部電
極をSiO2層により挟み前記薄膜共振部を形成し、前記シ
リコン基板のエッチング部に埋められたエッチング材を
エッチングすることにより前記薄膜共振部とシリコン基
板とを分離して、前記薄膜共振部の厚み方向の中心面を
前記シリコン基板の表面とほぼ同一とすることを特徴と
する薄膜共振子の製造方法。
1. A silicon substrate is anisotropically etched to a depth of at least half the thickness of a thin-film resonating portion to be formed, and the silicon substrate is etched except for a depth of about half the thickness of the thin-film resonating portion. An etching material is buried in a portion, a piezoelectric material is sandwiched between an upper electrode and a lower electrode on an upper surface thereof, the upper electrode and the lower electrode are sandwiched by an SiO 2 layer to form the thin-film resonating portion, and an etching portion of the silicon substrate is formed. The thin film resonating portion and the silicon substrate are separated by etching the buried etching material, and a center plane in a thickness direction of the thin film resonating portion is made substantially the same as the surface of the silicon substrate. A method for manufacturing a resonator.
JP63163125A 1988-06-30 1988-06-30 Manufacturing method of thin film resonator Expired - Fee Related JP2657521B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63163125A JP2657521B2 (en) 1988-06-30 1988-06-30 Manufacturing method of thin film resonator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63163125A JP2657521B2 (en) 1988-06-30 1988-06-30 Manufacturing method of thin film resonator

Publications (2)

Publication Number Publication Date
JPH0213109A JPH0213109A (en) 1990-01-17
JP2657521B2 true JP2657521B2 (en) 1997-09-24

Family

ID=15767663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63163125A Expired - Fee Related JP2657521B2 (en) 1988-06-30 1988-06-30 Manufacturing method of thin film resonator

Country Status (1)

Country Link
JP (1) JP2657521B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260596A (en) * 1991-04-08 1993-11-09 Motorola, Inc. Monolithic circuit with integrated bulk structure resonator
DE59207751D1 (en) * 1991-04-30 1997-02-06 Metaverpa Nv Belt conveyor method and apparatus
JP2005236337A (en) 2001-05-11 2005-09-02 Ube Ind Ltd Thin-film acoustic resonator and method of producing the same
JP2004158970A (en) 2002-11-05 2004-06-03 Ube Ind Ltd Band filter employing thin film piezoelectric resonator
CN103745913B (en) * 2013-12-24 2016-07-06 上海新傲科技股份有限公司 The growing method of strained layer and the substrate with strained layer
CN103745915B (en) * 2013-12-24 2016-06-29 上海新傲科技股份有限公司 The growing method of strained layer and the substrate with strained layer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281807A (en) * 1985-10-05 1987-04-15 Toshiba Corp Piezoelectric thin film resonator
JPS6382116A (en) * 1986-09-26 1988-04-12 Matsushita Electric Ind Co Ltd Piezoelectric thin film resonator and its manufacture
JPH01157108A (en) * 1987-12-14 1989-06-20 Victor Co Of Japan Ltd Piezoelectric thin film resonator

Also Published As

Publication number Publication date
JPH0213109A (en) 1990-01-17

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