JP2655085B2 - Bus signal collisionless switching system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system for a digital circuit, and more particularly to a bus control system which guarantees collision-free operation at the moment of switching the transmission source of a bus signal when a technology which avoids competition between outputs is used. The present invention relates to a collision switching system.

[0002]

2. Description of the Related Art An example of a conventional bus signal switching system will be described with reference to FIG.

Referring to FIG. 7, buffers 1, 2,...
n-1 and n are buffers for driving the bus indicated by line 401. Each of these buffers is in a high impedance state at the time of non-output, and competition occurs when two or more buffers output different values at the same time.
In this example, buffers 48, 1, 2,..., N−1 and n are connected to lines 48 by control logics 1, 2,.
Bus driving instructions are given from 1 to 483. Under these conditions, it is necessary to appropriately control such that competition between buffer outputs is avoided as much as possible.

[0004]

In this conventional bus signal switching system, the time relationship at the moment when each bus drive instruction signal is validated and invalidated is determined by control logic circuits 1 and 2.
.., Skew of timing signals such as clocks given to n−1 and n, variation in propagation delay of elements constituting a circuit, or difference in paths on a circuit configured differently by the operation of various logic circuits; And the like are accumulated, and a high-impedance state and an indefinite period of the output state occur for a considerable period. Hereinafter, this state is referred to as an output indeterminate state, and this period is referred to as an output irregular feeling. Here, the difference between the paths on the circuit will be described below, for example, focusing on the portion shown in FIG. 8 in the configuration shown in FIG.

Referring to FIGS. 8 and 9, the delay of combinational circuit A is small, the delay of combinational circuit B is large,
Assume that the value "1" specifies activation. Line 9
When validating an invalid bus drive request on line 55, line 9
When the logical value on 56 is set to "1" to instruct the OR gate 953 to enable, the timing is advanced. Also, 95
When the instruction is made by setting the logical value on 7 to "1", the timing is delayed, and when the instruction is made from both, the timing is advanced. When the bus drive request in the valid state on the line 955 is ineffective, when the logic on the line 956 is set to “0” to instruct the OR gate 953 to invalidate, the timing is advanced, and the value on the line 957 is changed to “ If the instruction is made to be "0", it will be delayed, and if both are instructed, it will be late. Here, a shown in FIG. 9 is a skew of a timing signal such as a clock, b is a propagation delay of an element forming a circuit,
c indicates a variation due to a difference in a path on a circuit configured differently according to the operation of the logic circuit. When the output indefinite period occurs in this way, if the outputs of a plurality of buffers having such characteristics are connected to form a bus, the possibility of contention cannot be denied when the plurality of output indefinite periods overlap. There are two ways to solve the conflict of the output indefinite state in such a situation with variations.

Referring to FIG. 10A, one idea is that
The instantaneous collision is unavoidable in view of deterioration of characteristics such as reliability, power consumption, and ground level fluctuation of the buffer due to the short-circuit current.

Referring to FIG. 10B, another idea is to secure a sufficient timing margin to completely avoid the overlap between output irregularities, with the expectation that the performance will deteriorate due to a large unused period. . However, in the latter case, a margin is simply secured for all the variation factors, so that a technique such as delay adjustment has to insert a large delay beyond the limit. It is not unusual to abandon this method and insert a buffer period of one clock completely on the clock timing when switching the transmission source of the bus signal as shown in FIG. 10C. Of course, in this case as well, the performance will be severely damaged. Also, in general, the control logic may take an excessive value, such as a hazard or a spike, which is different from a value determined after a sufficient time elapses, such as a hazard or a spike, if the combination logic is designed without particular care. .

[0008] FIG. 11 shows a buffer signal from a buffer 1 to a buffer 2 in the conventional bus signal switching system shown in FIG.
Shows the time relationship when the transmission source is switched. Since the buffers 1 to n and the control logic circuits 1 to n in this example have symmetry, generality is not lost even if the numbers 1, 2, and n are specified to describe the buffers and control logic circuits. It is of course conceivable that other control logic circuits could cause hazards and spikes, but it is sufficient to explain this element and it is assumed that the others remain in an invalid state. Here, the bus drive requests on the lines 481, 482, and 483 are invalid at a low level and valid at a high level. First, the state on line 481 indicates the source has no effect, ie, it changes from high level to low level,
The state 82 indicates that the transmission source is to be validated, that is, changes from a low level to a high level. However, in each case only one change was necessary, and after several changes, it finally settled at the final level. Next, line 483 must remain low since it is not a source from the beginning and does not switch to a source. However, it reached a high level several times on the way, and eventually settled on the original low level.
When the levels of lines 481-483 change in this manner, the outputs of buffers 421, 422, and 423 are driven as shown in FIG. 11, resulting in a collision.
On the other hand, there is a case in which a buffer activation instruction signal is once received by a flip-flop and given after eliminating hazards and spikes. This method is compatible with the method described with reference to FIG. 10C and is considerably used. However, at the timing shown in FIG. 10C, as described above, a great performance cost is sacrificed, and otherwise, the fact that the flip-flop receives it is a certain design and timing constraint. And inevitable performance degradation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus signal collision-free switching system in which the outputs of a plurality of buffers are independently generated, and even if the outputs of the buffers are quickly switched, the conflict of the buffer outputs can be prevented. To provide.

It is another object of the present invention to provide a bus signal collision-free switching system capable of preventing contention of buffer outputs even if the outputs of a plurality of buffers are independently generated.

It is still another object of the present invention to provide a bus signal collision-free switching system capable of preventing contention of buffer outputs even if the outputs of a plurality of buffers are quickly switched.

[0012]

According to a first system of the present invention, a bus drive instruction which is valid in response to a valid bus drive request to itself and an all invalid bus drive instruction input from other than itself. And a plurality of bus driving buffers for driving corresponding outputs in response to valid bus drive instructions from these collision-free switching element means.

A second system according to the present invention comprises a bus from the certain collision-free switching element between the output of one collision-free switching element and the input of another collision-free switching element in the first system. A non-collision switching element in which a delay means for delaying a drive instruction for a predetermined time is added to the first system, is constituted by a NAND gate.

A third system according to the present invention is characterized in that the collisionless switching element means in the first system is constituted by a NAND gate.

A fourth system of the present invention is characterized in that the collisionless switching element means in the first system is constituted by a NOR gate.

[0016]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the first embodiment of the present invention connects each output terminal of n buffers 121-124 to form a bus. , 153,... 154
A bus drive request is generated, and the corresponding line 181, 182,
, 183,... 184. Each of these control logic circuits 151 to 154 is usually constituted by a sequential circuit or a combination circuit.

The # 1 non-collision switching element means 111, 112,..., 113,.
, 184, and 184, and a bus drive instruction from all other non-collision switching means other than itself, which is provided via the line 102, and the corresponding line 191 , 192, ..., 193, ... 1
A bus drive instruction is output to 94. For example, the collision-free switching element 113 of #i indicates that the bus drive request given from the i-th control logic circuit 153 via the line 183 is valid and all other collision-free switching elements 111, 112,. 1
When all the bus driving instructions given from the line 14 via the line 102 are invalid, a valid bus driving instruction is output to the line 193.

Each of the bus driving buffers 121-124 operates in response to a bus driving instruction given from a corresponding collision-free switching element means 111-114 via a corresponding line 191-194. That is, if the bus driving instruction is valid, the bus is driven, and if the bus driving instruction is invalid, the output of the buffer is in a high impedance state. The i-th control logic circuit 153 corresponds to the #i non-collision switching element means 113 and the i-th buffer 123.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to the drawings.

In the first embodiment of the present invention, # 1 to #
Since n non-collision switching element means of n have symmetry,
For convenience of explanation, the following description will be made by specifying the collision-free switching element means of # 1 and # 2.

The operation of switching the transmission source from the first buffer to the second buffer will be described with reference to FIGS. 1, 3A and 3B.

The bus drive requests on the lines 181 and 182 are invalid at a low level and valid at a high level.
Assume that a bus drive request from the control logic circuit 3-n is always invalid.

The operation when the bus drive request to the second buffer becomes valid after the bus drive request to the first buffer is invalidated will be described in detail with reference to FIGS. 1 and 3A.

Referring to FIGS. 1 and 3A, only the bus drive request provided from the first control logic circuit 151 via line 181 is valid and the other control logic circuits 152,
Lines 182, 183, and 1 from 153, and 154
All bus drive requests provided via 84 are invalid. In response to these bus drive requests, the collision-free switching elements 112, 1 other than the collision-free switching element 111 of # 1
Bus drive instructions from 13 and 114 are invalid. Therefore, the # 1 collision-free switching means 111 via the line 102
All the bus drive instructions to are invalid. Further, the bus drive request provided via line 181 as described above is valid. For this reason, the collision-free switching element 111 of # 1 validates and gives the bus drive instruction to the first buffer 121 via the line 191. In response to this valid bus drive instruction, the first buffer 121 is in a drive state.

Since the instruction is valid, the second,..., I-th and n-th control logic circuits 152,... Other than the bus drive first control logic circuit 151 provided via the lines 191 and 102 are provided. , 153,... And 154 are lines 19
, 193,... 194 are instructed to be disabled. ,..., N-th buffers 122,.
The outputs of 3,... 124 are in a high impedance state.

When the bus drive request given from the first control logic circuit 151 via the line 81 is invalidated, the collision-free switching element 111 of # 1 sends the invalidated bus drive instruction to the line 191. Output. In response to the invalidation of the bus drive instruction, the first buffer 121 enters a high impedance state. As a result, there is no transmission source for driving the bus. Therefore, the non-collision switching element means 112 of # 2... #I... #N, for which the validity of the bus driving instruction has been suppressed by the valid bus driving instruction given via the line 191.
, 113,... 114 are requested to drive the bus, and when enabled, the bus drive instruction is enabled.

Next, the operation when the bus drive request of the first buffer 121 becomes ineffective after the bus drive request to the second buffer 122 is validated will be described in detail with reference to FIGS. 1 and 3B. I do.

Referring to FIG. 1 and FIG. 3B, when the bus drive request given from the second control logic circuit 152 to the line 82 is validated, the collisionless switching element means 112 of # 2
Outputs a valid bus drive instruction on line 192. In response to a valid bus drive instruction on line 192, second buffer 122 is driven and the bus is driven again.

Since the bus drive instruction given via lines 192 and 102 is valid, # 1, #
3 to #n collision-free switching element means 111, 113 and 1
14 invalidates the bus drive instruction output to the lines 191, 193 and 194. In response to this invalidation, the first, i-th and n-th buffers 121, 123 and 124 maintain a high impedance state.

The embodiment of the present invention works effectively for hazards and spikes. FIG. 12A, FIG. 12B and FIG. 12C show the operation of the embodiment of the present invention when a bus drive request is given under the same condition as that for switching the transmission source from buffer 1 to buffer 2 described with reference to FIG. It is shown.

The reason why FIGS. 12B and 12C are divided is as follows.

Referring to FIG. 12A, a bus drive request from control logic circuits other than the i-th control logic circuit 153 via lines 181, 182 and 184 indicates low level invalid and high level valid. First, the state on the line 181 indicates the invalidation of the transmission source by a change from the high level to the low level, and the state on the line 182 indicates the activation of the transmission source by the change from the low level to the high level. doing. Here, attention is paid to the invalidation time point C of the bus drive request from the second control logic circuit 152. At this point C, line 1
The bus drive instruction on 92 is invalidated. Along with this disabling, the suppression of the collision-free switching element means that has suppressed the generation of the bus drive instruction on the lines 191 and 194 while the bus drive request on the lines 181 and 184 has been enabled is released. You.
By this release, the collisionless switching element means 111 of # 1 and #n
Both of the non-collision switching element means 114 attempt to validate the bus drive instruction. However, here, there is a delicate signal transmission on the circuit that is early and late, so that the own bus drive instruction is enabled earlier, the side that has transmitted to the other party continues to enable the bus drive instruction, and the transmitted side is the bus drive instruction. Validation of the instruction is suppressed. FIG. 12b shows # 1 collision-free switching element 1
11 shows an operation state in a case where the bus drive instruction from # 11 is validated and the bus drive instruction from the collision-free switching element means 114 of #n is suppressed.

Referring to FIG. 12B, at time C, the bus drive instruction from the collision-free switching element 111 of # 1 is validated, and the bus drive instruction from the collision-free switching element 114 of #n is suppressed. Control logic circuits 152,.
, Only the first buffer 121 is driven. After that, in response to the reduction of the bus drive request given from the first control logic circuit 151 via the line 181, the # 1 non-collision switching element 111 to the line 191
Are also invalidated. In response to this invalidation and a valid bus drive request from the nth control logic circuit 154 via line 184, the #n collision free switching element 114 of #n validates the bus drive instruction provided on line 194. . As a result, only the n-th buffer 124 is driven.

Next, the operation in the case where the bus drive instruction from the collision-free switching element 114 of #n is validated at time C and the bus drive instruction from the collision-free switching element 111 of # 1 is suppressed. explain.

Referring to FIG. 12C, at time C, the bus drive instruction from the collision-free switching element 114 of #n is validated, and the bus drive instruction from the collision-free switching element 111 of # 1 is suppressed. Control logic circuits 152,.
Since there is no bus drive request from the fourth buffer 124,
Only are driven.

As a result, in one embodiment of the present invention, the time C
Thus, even if a plurality of bus drive requests are made, a bus collision can be avoided.

A configuration including a configuration example of the collisionless switching element which is one of the features of one embodiment of the present invention will be described.

Referring to FIG. 2A, four collision-free switching element means corresponding to the four control logic circuits are NAND (NAN).
D) shows an example composed of gates.

The non-collision switching element means is valid when all bus drive instructions are "1" and invalid when "0". The non-collision switching element means is valid when the bus drive request from the corresponding control logic circuit is "1" and invalid when it is "0". The non-collision switching element means that satisfies these requirements is constituted by another input NAND (NAND) gate. A bus drive instruction from one or more other non-collision switching element means is input as one input of the NAND gate, and a bus drive request from a corresponding control logic circuit is input as the other input. The output of the NAND gate obtained by performing a NAND operation on these inputs is used as a bus drive instruction signal.

Referring to FIG. 2B, four collision-free switching element means corresponding to the four control logic circuits are NOR.
An example composed of gates is shown.

This non-collision switching element means is valid when all bus drive instructions are "1" and invalid when "0". The non-collision switching element means is valid when the bus drive request from the corresponding control logic circuit is "1" and invalid when it is "0". The non-collision switching element means that satisfies these requirements is constituted by another input NOR (NOR) gate. A bus drive instruction from one or more other collision-free switching element means is input as one input of the NOR gate, and a bus drive request from a corresponding control logic circuit is input as the other input.
The output of the NOR gate obtained by ANDing these inputs is used as a bus drive instruction signal.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 4, a feature of the second embodiment of the present invention is that each of the collision-free switching element means 111, 112,.
, 373,... Between the lines 102, 192,.
That you have. This delay element means is connected to line 191,1
92,... 193,... 194, the same value after delaying the time d by lines 331, 332,.
... 333, ... 334. The other components are the same as the corresponding components of the first embodiment of the present invention.

A preferred example in which the second embodiment is effective will be described with reference to FIG.

Referring to FIG. 6, a feature of the preferred example is that a distribution gate 903 is interposed between the collision-free switching element means 113 and the i-th buffer 123. In the second embodiment, buffers 121, 122,... 123,.
124 has a certain data width, and lines 191 and 19
193,... 194 are distributed to the respective buffers by the distribution gates. The dispersion of the signal transmission delay of the distribution gate 903 is not guaranteed by the collisionless switching element means. In such a case, the second embodiment employs delay element means 371, 372,.
The delay at 4 can also avoid signal collision.

The operation of the second embodiment will be described with reference to FIG.

Referring to FIGS. 4 and 5, the first control logic circuit 151 in the second embodiment nullifies a bus drive request provided via line 181. In response to this invalidation, the bus drive instruction given via line 191 is invalidated. As a result, the first buffer 121 enters a high impedance state. The invalidation phenomenon of the bus drive instruction given via the line 191 is caused by the delay element
Each of the collision-free switching element means 11
1, 112,... 113,. The bus drive request from the second control logic circuit 152 via the line 182 is given to the # 2 collisionless switching element means 112 before the invalidation phenomenon of the bus drive instruction is given via the line 102. In response to the invalidation phenomenon of the bus driving instruction given via the line 102, the # 2 collision-free switching element means 112
Sends a bus drive instruction to the second buffer 122 on line 19.
Output to 2. Second buffer 122 is driven in response to a bus drive instruction provided via line 192. The change of the first buffer 121 to the high impedance state and the driving state of the second buffer 121 are not continuous, and the sense of the delay time d is provided. This feeling is used to adjust the margin period to ensure no collision.

The frame 100 shown by a broken line in the first embodiment of the present invention shown in FIG. 1 or the frame 200 shown by a broken line in the second embodiment of the present invention shown in FIG. Can also be configured.

The present invention is characterized in that at most one input of each bus drive request given in one embodiment of the present invention is enabled in a steady state.

Another feature of the present invention is that when the input of the bus drive request is changed and a transition from one steady state to the next steady state is made, at most one input is newly activated.

One of the other features of the present invention is that when the input of the bus drive request is changed and a transition from one steady state to another steady state is made, there is an input that has already been validated, and When the input is validated, the validation of the already validated input is canceled.

The bus driving buffers 121, 122, 123 and 124 used in one embodiment of the present invention
A tri-state type buffer having a control input, wherein the output of the buffer is driven when the control input is valid, and the output of the buffer is set to a high impedance state when the control input is invalid. The bus driving instruction from the collisionless switching element means 111, 112, 113 and 114 is input.

[0054]

According to the present invention, even if the bus drive requests from various types of control logic circuits are switched, a very small amount of hardware is used, and the signal on the bus is minimized while minimizing the effect on performance. This has the effect of avoiding contention.

The present invention has an effect that the outputs of a plurality of buffers are independently generated, and even if the outputs of the buffers are quickly switched, contention of the buffer outputs can be prevented.

According to the present invention, the enable instruction can be output so as not to be asynchronously duplicated by utilizing the circuit delay, thereby achieving both quick switching and non-collision of signals.

Further, according to the present invention, even if a collision occurs due to a variation in the distribution process of the enable instruction, the period of the collision can be shortened, and the reliability can be improved in long-term use.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2A is a diagram showing an example in which the non-collision switching element means in FIG. 1 is constituted by a NAND gate;
FIG. 2B is a diagram illustrating an example in which the collision-free switching element means in FIG. 1 is configured by a NOR gate.

FIG. 3A shows a state after a bus drive request to a first buffer is invalidated in the first embodiment of the present invention.
FIG. 3B is a diagram for explaining the operation when the bus drive request to the second buffer is valid, and FIG. 3B shows that the bus drive request to the second buffer is invalidated in the first embodiment of the present invention. FIG. 10 is a diagram for explaining an operation when a bus drive request to the first buffer becomes valid after the request is made;

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 6 is a diagram for explaining an example in which the second embodiment of the present invention is improved.

FIG. 7 is a diagram illustrating an example of a conventional technique.

FIG. 8 is a diagram for explaining a difference between buses on a circuit.

FIG. 9 is a diagram for explaining the breakdown of output irregularities that occur cumulatively.

FIG. 10 is a diagram showing a concept for solving a signal conflict on a bus in the related art.

FIG. 11 is a diagram for explaining the operation of the related art.

FIG. 12 is a diagram for explaining the operation of the embodiment of the present invention under the same conditions as the operation shown in FIG. 11;

[Explanation of symbols]

111, 112, 113, 114 Collision-free switching element means 121, 122, 123, 124 Buffer 151, 152, 153, 154 Control logic circuit 221, 222, 223, 224 NAND gate 231, 232, 233, 234 NOR gate 371, 372 373, 374 Delay element means 903 Distribution gate

Claims (2)

(57) [Claims] A plurality of collision-free switching element means for outputting a valid bus driving instruction in response to a valid bus driving request to the self and an invalid bus driving instruction supplied from other than the self; A bus signal collisionless switching system comprising: a plurality of bus driving buffers for driving a corresponding output in response to a valid bus driving instruction from the collisionless switching element means. 2. A bus drive from the certain collision-free switching element connected between the output of one collision-free switching element and the input of another collision-free switching element of the plurality of swing collision switching elements. 2. The bus signal collisionless switching system according to claim 1, further comprising delay means for delaying the instruction for a predetermined time.