JP2655048B2 - DRAM cell transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a memory cell transistor of a dynamic random access memory (DRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 5 is a diagram showing a structure of a conventional DRAM memory cell transistor.

In the figure, reference numeral 21 denotes a P-type silicon substrate;
3 is a field oxide film and a gate oxide film formed on a P-type silicon substrate 21, 24 is a gate electrode, 25 is a mask silicon oxide film formed by photolithography using a mask, and 26 is an N ⁻ type diffusion. layer,
27 is a side wall silicon oxide film serving as a side wall of the gate electrode 24, 28 is a first interlayer insulating film, 29 is a charge storage electrode, 30 is an N ⁺ type diffusion layer, 31 is a capacitance insulating film, and 32 is a capacitance counter electrode. Reference numeral 33 denotes a second interlayer insulating film, reference numeral 34 denotes a polycrystalline silicon layer, and reference numeral 35 denotes a tungsten silicide layer.

In a stacked capacitance type DRAM, the source and drain diffusion layers of a memory cell transistor have a charge storage electrode 29 for forming a capacitance, and a polycrystalline silicon layer 3 made of tungsten polycide wiring for forming a bit line.
4. The tungsten silicide layer 35 is connected. Of these, the source diffusion layer, for example, a charge storage electrode is formed so that a good diffusion layer is formed between the source diffusion layer and the substrate even if the contact hole deviates from the N ⁻ type diffusion layer 26 due to misalignment or the like. An N ⁺ type diffusion layer 30 is formed by means such as phosphorus diffusion through crystalline silicon. Also, regarding the drain diffusion layer, tungsten polycide wiring and N ⁻
In order to reduce the contact resistance between the diffusion layers 26, an N ⁺ diffusion layer 30 is formed by means such as phosphorus implantation into tungsten silicide.

When the margin between these contacts and the gate electrode decreases with miniaturization of the memory cell, the phosphorus forming these N ⁺ diffusion layers 30 diffuses in the channel direction, and the short channel effect of the memory cell transistor is reduced. problems such as reduction in the threshold voltage V _T is generated by.

As a countermeasure against this problem, there has been proposed a transistor structure as shown in FIG.
-50452).

In FIG. 6, 41 is a P-type silicon substrate, 42 is a field oxide film, 43 is a gate oxide film, 44 is a gate electrode, 46 is an N-type diffusion layer, 48 is a PSG film, and 55 is doped polycrystalline silicon. is there.

In the present structure, as a measure against the short channel effect, an N-type diffusion layer 46 is provided at the source and drain of the transistor.
Is formed in the N-type diffusion layer 46 by using a photolithography technique, a low-resistance doped polycrystalline silicon layer 55 is formed inside the groove, and this is used as a wiring layer. It is intended to use the diffusion layer as a conductive layer while suppressing the short channel effect of the transistor.

[0009]

In this conventional transistor structure, since a groove is formed in a diffusion layer using a photolithography technique, the size of the groove and the alignment margin between the groove and the diffusion layer are reduced by the fine processing technique. It was not possible to reduce the size below the limit, making it difficult to reduce the size of the memory cell. In a DRAM memory cell, the source and drain diffusion layers of each transistor are arranged at a minimum distance from each other. Therefore, in the conventional transistor structure shown in FIG. Diffusion also occurs in the direction of the oxide film, and there is a problem that punch-through occurs with the diffusion layer of the adjacent transistor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and is directed to a DRAM cell transistor capable of miniaturizing a memory cell while suppressing a short channel effect of the transistor. And a method for manufacturing the same.

[0011]

According to the present invention, there is provided a DRAM cell transistor comprising: a second conductivity type source diffusion layer and a drain diffusion layer provided on a surface of a first conductivity type semiconductor substrate;
A gate electrode provided between the source diffusion layer and the drain diffusion layer and on an insulating film serving as an element isolation region; an insulating film provided on an upper surface of the gate electrode; and an insulating film provided on a side wall of the gate electrode. A film, a concave portion formed on the side wall in a self-aligned manner with respect to an insulating film serving as an element isolation region, an insulating film provided on an inner wall of the concave portion, the source diffusion layer and the drain. impurity concentration than the diffusion layer is rather high, characterized in that it comprises a <br/> diffusion layer formed on the bottom lower portion of the recess.

In this case, the conductive material may be polycrystalline silicon.

According to the method of manufacturing a DRAM cell transistor of the present invention, a low-concentration second
A first step of forming an insulating film serving as an element isolation region with a source diffusion layer and a drain diffusion layer of a conductivity type; and insulating the upper surface between the source diffusion layer and the drain diffusion layer and over the insulating film serving as an element isolation region. A second step of providing a gate electrode having a film, a third step of forming an insulating film on a side wall of the gate electrode formed in the second step, and an insulating film formed on a side wall of the gate electrode A fourth step of forming a recess in a self-aligned manner with respect to an insulating film to be an element isolation region; and a fifth step of forming an insulating film on the surface of the semiconductor substrate after the fourth step. A sixth step of forming a contact hole reaching at least one bottom surface of the concave portion and forming an insulating film on an inner wall of the concave portion, and a seventh step of forming a conductive material connected to the bottom surface of the concave portion. And contacting the bottom surface with a conductive material. The portion, and a eighth step of forming the source, a high concentration of the diffusion layer than the drain diffusion layer.

[0014]

In the DRAM cell transistor of the present invention,
Since the concave portions formed with respect to the gate electrode and the source diffusion layer and the drain diffusion layer are formed in a self-aligning manner, the processing can be performed with high precision not depending on the precision of the fine processing technology. .

Further, since an insulating film is formed on the inner wall of the above-mentioned concave portion, it is possible to prevent punch-through from occurring between the transistor and a diffusion layer of an adjacent transistor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a DRAM cell transistor according to one embodiment of the present invention, and FIGS. 2 and 3 are views showing a method of manufacturing the cell transistor of this embodiment.

In FIG. 1, 1 is a P-type silicon substrate, 2 is a field oxide film serving as an element isolation region, 3 is a gate oxide film,
4 is a gate electrode, 5 is a mask silicon oxide film, 6 is an N ⁻ type diffusion layer to be a source diffusion layer or a drain diffusion layer, 7
Is a side wall silicon oxide film, 8 is an interlayer insulating film, 9 is a charge storage electrode, 10 is an N ⁺ type diffusion layer, 11 is a capacitive insulating film, and 12 is a capacitive counter electrode.

The manufacturing method of the embodiment shown in FIG. 1 will be described below with reference to FIGS.

In the element isolation region on the P-type silicon substrate 1,
A field oxide film 2 having a thickness of about 500 nm is formed by using a known selective oxidation technique, and ion implantation for adjusting a threshold voltage of a transistor is performed.
A gate oxide film 3 of about 5 nm was grown. Thereafter, a polycrystalline silicon film having a thickness of about 250 nm is grown on the entire surface, and a desired resistance value is obtained by phosphorus diffusion.
A silicon oxide film of about nm is grown.

Next, after processing the mask oxide film 5 and the gate electrode 4 into a desired pattern using a photolithography technique, phosphorous is applied to the N-channel transistor region at 40 keV.
The degree of about 1 × 10 ¹³ cm ^-2 implanted to form a ^N-type diffusion layer 6 in energy to obtain the shape shown in FIG. 2 (a).

Next, a silicon oxide film having a good step coverage with a thickness of about 200 nm was grown on the entire surface, and etched back to form a sidewall oxide film 7. Subsequently, the shape shown in FIG. 2B was obtained by etching the silicon substrate by about 150 to 200 nm.

The recess formed at this time is the gate electrode 4
In addition, since the memory cell is formed in a self-aligned manner with respect to the field oxide film 2 and is not formed using a mask as in the conventional example, the memory cell can be miniaturized without being restricted by the fine processing technology. It is possible to do.

Subsequently, after a silicon oxide film 8 having a good step coverage with a thickness of about 200 nm is grown on the entire surface, a photoresist 13 is applied and holes are formed in a desired pattern by using a photolithography technique. The shape shown in (c) was obtained.

Next, when the oxide film is etched using the photoresist as a mask, a sidewall silicon oxide film 7 is formed on the inner wall of the recess because the recess is formed in the substrate. Subsequently, an N ⁺ -type diffusion layer 10 is formed by growing a polycrystalline silicon film 14 having a thickness of about 200 nm and performing phosphorus diffusion so as to have a desired resistance value. Since the silicon film 7 ensures a sufficient distance between the channel of the transistor and the field oxide film 2, it is possible to suppress the narrow channel effect of the transistor due to the diffusion of phosphorus forming the N ⁺ type diffusion layer 10 and the influence on the element isolation. Can be.

In the above embodiment, as shown in FIG. 2B, the depth of the concave portion formed in the diffusion layer is equal to that of the N ⁻ type diffusion layer 6.
However, this depth can be made deeper than the depth of the N ⁻ type diffusion layer 6.

FIG. 4 shows an embodiment in which the depth of the concave portion is made larger than the depth of the N ⁻ type diffusion layer.

After the structure shown in FIG. 2A is obtained in the same manner as in the above-described embodiment, a sidewall silicon oxide film 7 is formed, and the P-type silicon substrate 1 is subsequently etched by about 300 to 400 nm. Since the depth of the N ⁻ type diffusion layer 6 is about 250 nm, the depth of the recess at this time is deeper than the depth of the N ⁻ type diffusion layer 6.

Next, phosphorous is added at 1 × 10 ¹³ cm at 40 keV.
By rotating tilted implantation at an angle of incidence ^-2 degree 30 °, the following N depth 0.1 nm ^- -type diffusion layer 15 is formed on the side wall of the recess, to obtain the shape shown in Figure 4 (a).

After the interlayer insulating film 8 and the contact hole between the charge storage electrode and the diffusion layer are formed in the same manner as in the above-described embodiment, a polycrystalline silicon film 14 having a thickness of about 200 nm is grown. The N ⁺ -type diffusion layer 10 is formed by performing phosphorus diffusion so as to have a phosphorus concentration.

In this embodiment, since the depth of the concave portion can be increased, the step of the charge storage electrode can be increased, the surface area can be increased, and the value of the cell capacitance can be increased. Has advantages.

[0032]

Since the present invention is configured as described above, it has the following effects.

In the DRAM cell transistor of the present invention, a recess is formed in a self-aligned manner with respect to the gate electrode and the source and drain diffusion layers, and a side wall silicon oxide film is formed on the inner wall of the recess to form a channel and a field oxide film of the transistor. Is formed after securing a sufficient distance, it is possible to miniaturize the memory cell while suppressing the reduction in the isolation voltage of the memory cell and the short channel effect of the transistor. There is an effect that there is.

The manufacturing method of the present invention has an effect that a DRAM cell transistor having the above effects can be manufactured.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of one embodiment of the present invention.

FIG. 2 is a view showing a manufacturing method of the embodiment shown in FIG. 1;

FIG. 3 is a view showing a manufacturing method of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing a manufacturing method according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a structure of a conventional DRAM cell transistor.

FIG. 6 is a diagram showing a conventional example of a transistor structure for suppressing a short channel effect.

[Explanation of symbols]

1 P-type silicon substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 mask oxide film 6 N ^- -type diffusion layer 7 side wall oxide films 8 interlayer insulating film 9 charge storing electrode 10 N ⁺ -type diffusion layer 11 capacitive insulating film 12 capacity Counter electrode

Claims (3)

(57) [Claims] 1. A source diffusion layer and a drain diffusion layer of a second conductivity type provided on a surface of a semiconductor substrate of a first conductivity type, and an upper portion of an insulating film serving as an element isolation region between the source diffusion layer and the drain diffusion layer. A gate electrode provided on the gate electrode; an insulating film provided on an upper surface of the gate electrode; an insulating film provided on a sidewall of the gate electrode; an insulating film provided on the sidewall and an insulating film serving as an element isolation region a recess formed in self-alignment with, an insulating film provided on an inner wall of the recess, the source diffusion layer and the impurity concentration than the drain diffusion layer rather high, which is formed on the bottom lower portion of the recess A DRAM cell transistor comprising a diffusion layer. 2. The DRAM cell transistor according to claim 1, wherein the conductive material is polycrystalline silicon. 3. A first step of forming a low-concentration second-conductivity-type source diffusion layer and drain-diffusion layer and an insulating film to be an element isolation region on the surface of the first-conductivity-type semiconductor substrate; A second step of providing a gate electrode having an insulating film on an upper surface between the layer and the drain diffusion layer and above the insulating film serving as an element isolation region; and an insulating film on a side wall of the gate electrode formed in the second step. A fourth step of forming a recess in a self-aligned manner with an insulating film formed on a side wall of the gate electrode and an insulating film serving as an element isolation region; A fifth step of forming an insulating film on the surface of the semiconductor substrate after the step of forming the insulating film; and a sixth step of forming a contact hole reaching at least one bottom surface of the concave portion and forming an insulating film on the inner wall of the concave portion. The step of connecting to the bottom of the recess Seventh forming conductive material
And a eighth step of forming a diffusion layer having a higher concentration than the source and drain diffusion layers at a connection portion between the bottom surface and the conductive material.