JP2653935B2 - Coordinate input device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coordinate input device such as a tablet used for inputting characters, figures, and the like to a personal computer or a word processor.

[0002]

2. Description of the Related Art As means for inputting handwritten characters and figures to a computer or a word processor, for example, a liquid crystal display and an electrostatic induction type tablet are combined.
2. Description of the Related Art An input device has been put to practical use in which characters and figures input to an electrostatic induction type tablet are input as if an operator wrote on paper with a writing instrument and displayed on a liquid crystal display.

Conventionally, as an electrostatic induction type tablet used for such an application, a transparent electrode such as indium oxide is formed on a transparent glass or plastic film, and a pulse voltage is sequentially applied to this electrode. The structure is generally used, and for example, there is a structure as shown in FIG.

The coordinate input unit 3 of this electrostatic induction type tablet
1 is a glass substrate 32 on which transparent electrodes X1, X2,..., Xm (collectively indicated by X) are formed;
A glass substrate 33 on which 1, Y2,..., Yn (collectively indicated by Y) are formed is disposed at a small interval so that the electrode forming surfaces face each other. It is placed on the display.

The transparent electrodes X and Y are connected to a column electrode shift register 34 and a row electrode shift register 35, respectively.
Is connected to the timing generation circuit 36. From the timing generation circuit 36, the shift register 34,
The shift data and the clock signal are sent to 35, and the electrodes X 1, X 2,.
In addition, from the row electrode shift register 35, the electrodes Y1, Y2,
, Yn are sequentially applied with a pulse voltage.

When a position detecting pen (hereinafter simply referred to as a detecting pen) 37 is brought close to the surface of the coordinate input section 31, a stray capacitance between the electrodes provided at the tip of the detecting pen 37 and the electrodes X and Y causes the stray capacitance. Then, a voltage is induced on the electrode at the tip of the detection pen 37. The voltage induced in the detection pen 37 is amplified by the amplifier 38, and the X coordinate detection circuit 39 and the Y coordinate
It is input to the coordinate detection circuit 40.

The X coordinate detection circuit 39 and the Y coordinate detection circuit 40 detect the X coordinate and the Y coordinate based on the output from the amplifier 38 and the timing signal from the timing generation circuit 36, respectively. The non-displayed liquid crystal display displays the position indicated by the detection pen 37 on the display based on the coordinate signal from the electrostatic induction type tablet.

However, in the case of this electrostatic induction type tablet, since the reflectance and the transmittance are different between the portion having the transparent electrodes X and Y of the coordinate input section 31 and the portion having no transparent electrodes X and Y, the electrodes are arranged in a grid on the display screen. Is seen, which causes the quality of the liquid crystal display to deteriorate.

In view of the above, a display integrated tablet as shown in FIG. 12 has recently been proposed as a tablet that eliminates such disadvantages.

In this display-integrated tablet, the display electrodes of the liquid crystal display also serve as position detection electrodes, and position detection and display are performed in a time-division manner.

In FIG. 12, a liquid crystal panel 501 includes common electrodes Y1 to Yn (indicated by Y when collectively referred to) and segment electrodes X1 to Xm arranged in directions crossing each other.
(Generally indicated by X) with a liquid crystal layer interposed therebetween, and each common electrode Y and segment electrode X
The liquid crystal layer at the intersection of is the pixel. That is, here, pixels of nxm dots are arranged in a matrix.

[0012] This display-integrated tablet has the advantage that the grid-like electrode pattern is not seen and the screen is easy to see, as compared with the above-mentioned tablet on a liquid crystal display. Also, there is an advantage that the cost can be reduced and the size and weight can be easily reduced.

A common drive circuit 502 for driving the common electrode Y and a segment drive circuit 503 for driving the segment electrode X are connected to a display control circuit 505 and a position detection control circuit 506 via a switching circuit 504. It is connected to the. The switching circuit 504 is switch-controlled by the control circuit 507, and during the display period, the display control circuit 505
Are output to the drive circuits 502 and 503, and the output from the position detection control circuit 506 is output to the drive circuits 502 and 503 during the position detection period.

In the display period, the display control circuit 505
Are shift data S, inverted signal FR, clock CP1,
CP2 and display data D0 to D3 are output.

The clock CP1 is a clock having a cycle of a scanning period for scanning one row of pixels.
4 is input to the clock input terminal CK of the common drive circuit 502 and the latch pulse input terminal LP of the segment drive circuit 503 from the output terminal CP10. The shift data S is a pulse signal for specifying each common electrode Y, is output from the output terminal S0 of the switching circuit 504, and is synchronized with the clock CP1 from the shift data input terminal D101 of the common drive circuit 502. Is entered.

In accordance with the shift of the shift data S, a drive signal is output from the output terminal of the common drive circuit 502 corresponding to the shift position to the common electrode Y. This drive signal is generated based on bias voltages V0 to V5 supplied from DC power supply circuit 512. Clock CP2
Is a clock whose period is a period obtained by dividing a scanning period for scanning pixels of one column into a plurality of periods. The clock is output from the output terminal CP20 of the switching circuit 504, and the segment driving circuit 5
03 clock input terminal XCK.

The display data D0 to D3 are supplied to the switching circuit 504.
Is output from the output terminal Dout of the segment drive circuit 503, is input to the input terminals D0 to D3 of the segment drive circuit 503, and is sequentially taken into a register inside the segment drive circuit 503. When the display data corresponding to the pixels of one row is taken in, the display data is latched at the timing of the clock CP1 input to the latch pulse input terminal LP, and the drive signal corresponding to each display data is driven by the segment drive. The signal is output from the output terminal of the circuit 503 to the segment electrode X. This drive signal is also generated based on the bias voltages V0 to V5 supplied from the DC power supply circuit 512. The inversion signal FR is a signal for periodically inverting the polarity of the voltage applied to the liquid crystal layer to prevent the liquid crystal from being deteriorated by electrolysis.

By the operation of the common drive circuit 502 and the segment drive circuit 503, the pixels of the liquid crystal panel 501 are driven according to the row order, and an image corresponding to the display data is displayed on the liquid crystal panel 501.

On the other hand, during the position detection period, the position detection control circuit 506 controls the shift data Sd, the inverted signal FRd, the clocks CP1d and CP2d, and the drive data D0d to D0d.
3d is output.

The clock CP1d is a clock having a cycle of a scanning period for scanning the common electrodes for one row, and is output from the output terminal CP10 of the switching circuit 504 to the common driving circuit 50.
2 clock input terminal CK and the segment drive circuit 50
3 and a latch pulse input terminal LP. Also,
The shift data Sd is a pulse signal for specifying each common electrode Y, is output from the output terminal S0 of the switching circuit 504, and is input from the shift data input terminal D101 of the common drive circuit 502 in synchronization with the clock CP1d. You.

According to the shift of the shift data Sd,
A drive signal is output to the common electrode Y from an output terminal of the common drive circuit 502 corresponding to the shift position. This drive signal is generated based on bias voltages V0 to V5 supplied from DC power supply circuit 512. Clock CP2
d is a clock having a cycle of a scanning period for scanning the segment electrodes X for one column, and is output from the output terminal CP20d of the switching circuit 504 and input to the clock input terminal XCK of the segment driving circuit 503.

The drive data D0d to D3d are supplied to the switching circuit 5
The signal is output from the output terminal Dout of the segment driving circuit 503, input to the input terminals D0 to D3 of the segment driving circuit 503, and sequentially taken into the register inside the segment driving circuit 503. 1
When drive data corresponding to the segment electrodes X for a row is taken in, these drive data are latched at the timing of the clock CP1d input to the latch pulse input terminal LP, and drive signals corresponding to each drive data are output. The signal is output from the output terminal of the segment drive circuit 503 to the segment electrode X. This drive signal is also created based on the bias voltages V0 to V5 supplied from the DC power supply circuit 512. The inversion signal FRd is a signal for periodically inverting the polarity of the voltage applied to the liquid crystal layer to prevent the liquid crystal from being deteriorated by electrolysis.

FIG. 2 is a timing chart showing the drive timing of the display-integrated tablet during the position detection period. As shown in FIG. 2, the position detection period is X
It is divided into a coordinate detection period and a subsequent Y coordinate detection period. In the X coordinate detection period, the segment electrodes X are sequentially driven by a lines, and in the Y coordinate detection period, the common electrodes Y are sequentially driven by b lines.

The reason why the pulse voltage is applied simultaneously for each of the plurality of detection pens is to improve the detection accuracy by increasing the induced voltage of the detection pen 508 and to shorten the detection period. The induced voltage of the detection pen 508 is amplified by the amplifier 509, and based on the output of the amplifier 509 and the timing signal from the control circuit 507, the X coordinate detection circuit 51
0 detects the X coordinate, and the Y coordinate detection circuit 511 detects the Y coordinate.

[0025]

In a display-integrated tablet using a liquid crystal panel as described above, the accuracy of coordinate detection may be reduced in the following cases.

When the detection pen 508 is separated from the liquid crystal panel 501 as a detection surface by several mm. When the contrast of the liquid crystal panel 501 is adjusted.

The reason will be described below. First, in FIG. 3, when the detection pen 508 is separated from the liquid crystal panel 501, the stray capacitance C between the scanning electrodes X and Y and the electrodes included in the detection pen 508 decreases according to the separation distance. Therefore, in the coordinate detection scanning as shown in FIG. 2, the voltage induced in the detection pen 508 decreases as the distance from the liquid crystal panel 501 increases.

Usually, the tip of the detection pen 508 is an electrode for detecting coordinates, and often has a mechanism linked to a switch for instructing an input mode. That is, when the tip of the detection pen 508 is lightly pressed against the liquid crystal panel surface (several tens of g), the switch is turned on, and the coordinates indicated by the detection pen 508 are taken into the host side, for example, a microcomputer. I have. Therefore, if the function is limited to the function as the coordinate input device, the coordinate detection need not be performed when the detection pen 508 is separated from the detection surface (the liquid crystal panel 501).

However, considering the operability (ease of use) of the tablet, the approximate position can be detected simply by moving the detection pen 508 to a distance of several mm from the detection surface.
Although no coordinates are input to the host, it may be easier to use, for example, to display a "+" mark only on the liquid crystal panel position directly below the detection pen 508. In addition,
As can be understood from the application, the case where the detection pen 508 comes into contact with the detection surface has priority as the coordinate detection accuracy.

FIG. 5 is a waveform diagram showing a waveform of a voltage induced in the detection pen 508. FIG. 5A shows the detection pen 508.
FIG. 5B is a voltage waveform diagram when the detection pen 508 is in contact with the liquid crystal panel 501, and FIG. 5B is a voltage waveform diagram when the detection pen 508 is slightly separated from the liquid crystal panel 501.

FIG. 14A is a graph in which the voltage shown in the graph of FIG. 7 is amplified by an operational amplifier 509, which will be described later, and a signal waveform only during the coordinate detection period is extracted and overwritten. That is, in FIG. 14A, the voltages Vx1 and Vy1
Is an output VOP obtained by amplifying the induced voltage when the detection pen 508 approaches the liquid crystal panel 501 by the operational amplifier 509, and the voltages Vx2 and Vy2 are the induced voltages when the detection pen 508 is separated from the liquid crystal panel 501.
9 are the voltages of the amplified output VOP at the time of detecting the X coordinate and at the time of detecting the Y coordinate.

On the other hand, a tablet using a liquid crystal panel is characterized in that a segment drive circuit and a common drive circuit are used not only for display but also for coordinate detection. Therefore, in order to reduce the size and cost of the tablet. Similarly, the bias voltages V0 to V5 are similarly used for both display and coordinate detection.

However, the bias voltages V0 to V5
Are obtained by resistance division as shown in FIG. 10, and all the bias voltages are adjusted by the contrast adjustment volume VR.
Are divided by a ratio to obtain the best image quality. Therefore, if the volume VR is adjusted to adjust the display contrast, the bias voltages V0 to V5
All change at the same rate. Therefore, if these bias voltages V0 to V5 are used as scanning voltages for coordinate detection, the detection pen 3 is adjusted every time display contrast is adjusted.
The value of the induced voltage to 7 also changes.

In FIG. 10, when the contrast of the liquid crystal display is changed by adjusting the contrast adjustment volume VR, for example, the position of the detection pen 508 is changed to the liquid crystal panel 50.
1, the voltage induced in the detection pen 508 changes as shown in FIGS. 5 (1) and 5 (2).
The output VOP amplified by the operational amplifier 509 is shown in FIG.
As shown in (1), voltages Vx1, Vx2; Vy1, V
It changes like y2.

As described above, when the detection pen 508 is separated from the liquid crystal panel 501 and when the contrast is adjusted, the induced voltage of the electrodes included in the detection pen 508 changes, and this change affects the coordinate detection accuracy. .

The coordinate detection processing will be described with reference to FIG. First, the output voltage VOP of the operational amplifier 509 is binarized. The detection voltage electrostatically induced by the detection pen 508 is
Amplified by the operational amplifier 509, the analog gate circuit 5
The signals are supplied to comparators 53 and 54 via the respective comparators 1 and 52, and are binarized in the comparators. In addition,
Here, when the analog gate circuit is on, the input voltage of the + input terminal of each of the comparators 53 and 54 has the same voltage as the output voltage of the operational amplifier 509 without a voltage drop due to the electric resistance of the circuit wiring or the like. I do.

Each of the analog gate circuits 51 and 52 outputs a control signal g which is set to a high level during the X coordinate detection period.
In response to the control signal gy which is set to the high level during the x and Y coordinate detection periods, the output of the operational amplifier 509 is supplied to the comparators 53 and 54 for the periods necessary for detection, respectively. The analog gate circuits 51 and 52 are provided between the operational amplifier 509 and the comparators 53 and 54, not between the operational amplifier 509 and the comparators 53 and 54.
3, 54 may be provided on the output side. In this case, after the input voltages in the X coordinate detection period and the Y coordinate detection period are binarized by the comparators 53 and 54, the control signal g
Only necessary signals are extracted by x and gy.

The volumes 55 and 56 are
The reference voltages Vsx and Vsy are supplied to the comparators 53 and 54, respectively, for adjusting the threshold voltage levels of the comparators 53 and 54. The reason why the volumes 55 and 56 are separately provided for the comparators 53 and 54 is that the induction between the electrode X and the detection pen 508 is caused by the arrangement of the electrodes X and Y, the scanning voltage at the time of coordinate detection scanning, and the like. This is because the voltage and the induced voltage between the electrode Y and the detection pen 508 often do not match.

FIG. 14 is a waveform diagram for explaining the operation of comparators 53 and 54. FIG. 14A shows the output VOP of the operational amplifier 509, and FIG. 14B shows the gate signal gx of the analog gate circuit 51. During the X-coordinate detection period, the gate signal gx is at a high level, whereby the analog gate circuit 51 becomes conductive, and
Select the voltage in the coordinate detection period. FIG.
(3) shows a gate signal gx of the analog gate circuit 52, which becomes high level during the Y coordinate detection period. As a result, the analog gate circuit 52 becomes conductive, and selects a voltage during the Y coordinate detection period.

FIGS. 14 (4) and 14 (5) are output signals binarized by the comparators 53 and 54, and represent the time Tsx from the reference time (the start time of the X coordinate and Y coordinate detection period). , Tsy, for example, by a counter or the like, the X coordinate and the Y coordinate can be detected.

In the actual operation, the peak value of the output VOP of the operational amplifier 509 changes during the X coordinate detection period and the Y coordinate detection period due to the above-described factors. Therefore, as shown in FIG. 13, when the binarization process is performed with the threshold voltage level of the comparator fixed at, for example, the reference voltage Vsx = Vsx1, the output VOP of the operational amplifier 509 becomes the voltage Vx
If 1, the output from the comparator 53 is as shown in FIG.
And outputs a binary signal as shown in FIG.

However, as described above, when the induced voltage drops to the potential Vx2, it is lower than the threshold voltage level Vsx of the comparator 53.
3 does not output a binary signal. Therefore, in order to operate the comparator 53 even when the induced voltage is the potential Vx2, the threshold voltage level Vsx is set to the potential Vsx2.
Must be lowered to Thus, by lowering the threshold voltage level Vsx, the comparator 53
Outputs a binary signal as shown in FIG. However, when the output VOP of the operational amplifier 509 rises to the potential Vx1 with the reference voltage Vsx fixed to the potential Vsx2, the binary signal from the comparator 53 is
As shown in FIG. 4 (6), the pulse width increases to tWL.

As described above, the coordinate detection is performed during the period Tsx,
Since the detection is performed by detecting Tsy, it is desirable that the pulse width tW of the binary signal output from the comparators 53 and 54 is as small and constant as possible. However, as shown in FIG.
Is fixed, for example, when the reference voltage Vsx is fixed to Vsx1, and when the output VOP is the voltage VX1, coordinate detection is executed with high accuracy.
When the output VOP is Vx2 lower than the potential Vsx2,
No coordinates can be detected at all.

When the reference voltage Vsx is selected as the potential Vsx2, the accuracy is high for the output VOP having a low value such as the potential VX2, but the detection accuracy is high when the detection pen 508 contacts the detection surface. Is required, the output VOP becomes a large value like the potential VX1,
The pulse width tW increases, and the coordinate detection accuracy decreases. Therefore, the coordinate detection accuracy is further improved by selecting the threshold voltage level of the comparators 53 and 54 from the optimum value according to the induced voltage of the detection pen 508. Therefore, the output VO, which is the amplified value of the induced voltage of the detection pen 508,
When P greatly changes, it is not appropriate to request a high coordinate detection accuracy while keeping the threshold voltage levels of the comparators 53 and 54 fixed. As described above, the induced voltage of the detection pen changes in the following cases, which is a problem when high coordinate detection accuracy is required.

When the detection pen 508 is separated from the liquid crystal panel 501. When the contrast of the liquid crystal panel 501 is adjusted.

Therefore, the output VOP has the potentials Vx1 to Vx
In order to perform coordinate detection with high accuracy even when the voltage fluctuates between x2, the threshold voltage level Vsx of the comparator 53 also fluctuates between the potentials Vsx1 and Vsx2 according to the output VOP, or the output VOP. Is ideal. The same applies to the comparator 54.

An object of the present invention is to solve the above problems and to provide a coordinate input device capable of detecting coordinates with high accuracy.

[0048]

According to the present invention, there is provided a liquid crystal panel in which a plurality of strip-shaped segment electrodes and a common electrode are arranged orthogonal to each other, and a segment electrode and a common electrode for driving the liquid crystal panel for display. A coordinate unit including a driving unit for sequentially applying a display voltage and performing AC driving to prevent electrolysis of the liquid crystal, and an electrode having a relatively high input impedance electrostatically coupled to the segment electrode and the common electrode. Means, during a coordinate detection period that does not contribute to display set following the liquid crystal panel display period, sequentially applying a coordinate detection voltage lower than a threshold voltage required for liquid crystal display to the common electrode and the segment electrode, The voltage induced at the electrode of the coordinate indicating means is amplified, the generation timing and waveform of the induced voltage are detected, and the timing of applying the coordinate detection voltage is adjusted. And a coordinate detecting means for calculating input coordinates based on the generation timing of the induced voltage, wherein the coordinate detecting means induces the electrode of the coordinate indicating means during a period other than the coordinate detecting period. Detecting a voltage and generating a DC voltage proportional to the detected value;
DC voltage generating means for holding the DC voltage until a coordinate detection period, and processing means for using the DC voltage as an auxiliary voltage and normalizing an analog voltage induced on an electrode of the coordinate indicating means during the coordinate detection period. A coordinate input device characterized in that:

Further, according to the present invention, the DC voltage generating means may include:
A DC voltage proportional to a peak value of a spike-like voltage induced on an electrode of the coordinate indicating means is generated, and the processing means includes a comparator for performing a binarization process of the analog voltage, and the DC voltage of the comparator It is characterized by using a reference voltage.

Further, according to the present invention, the DC voltage generating means includes:
A DC voltage proportional to the peak value of the spike-like voltage induced on the electrode of the coordinate indicating means is generated, and the processing means feeds back the DC voltage to an amplifier for amplifying the induced voltage to keep the peak value of the analog voltage constant. And performs the binarization processing of the analog voltage.

Further, according to the present invention, the DC voltage generating means includes:
The processing unit generates a DC voltage proportional to the peak value of the spike-like voltage induced on the electrode of the coordinate indicating unit, and the processing unit feeds back the DC voltage to a power supply that supplies a bias voltage to the driving unit during a position detection period. And controlling the bias voltage value to increase in accordance with the decrease in the DC voltage.

[0052]

According to the present invention, in the liquid crystal panel provided in the coordinate input device, an alternating drive unique to the liquid crystal is performed during the display period. An induced voltage such as an electrostatic spike noise is detected through a stray capacitance between the electrode provided in the indicating means and the electrode. The peak value and the waveform of the induced voltage are almost irrelevant to the display content of the liquid crystal panel, and are approximately ten times the voltage value induced on the electrode of the coordinate pointing means during the coordinate detection period, and although there is a difference in magnitude, It is almost proportional. Further, this proportional relationship holds even when the distance between the liquid crystal panel and the coordinate designating means is changed or when the display contrast on the liquid crystal panel is changed.

Therefore, the voltage (spike-like electrostatic noise) induced at the electrodes of the coordinate indicating means during the display period of the liquid crystal panel is converted into a DC voltage by rectifying and smoothing and holding the peak value, and the DC voltage value is held until the coordinate detection period. By performing the following processing, stable coordinate detection can always be performed regardless of the distance between the coordinate designating means and the electrodes of the liquid crystal panel and the adjustment of contrast in the liquid crystal panel.

The DC voltage is used as a reference voltage of a comparator for performing a binarization process of an analog voltage during a coordinate detection period. The DC voltage is fed back to an amplifier for amplifying the induced voltage to make the peak value of the analog voltage constant and to perform the analog voltage binarization process. The DC voltage is fed back to a power supply that supplies a bias voltage to the driving unit during a coordinate detection period, and the bias voltage value is controlled to increase according to the decrease in the DC voltage.

[0055]

FIG. 1 is a block diagram showing a schematic configuration of a coordinate input device according to an embodiment of the present invention. This coordinate input device is a so-called display-integrated tablet, in which display electrodes of a liquid crystal display also serve as position detection electrodes, and position detection and display are performed in a time-division manner.

In FIG. 1, a liquid crystal panel 1 has common electrodes Y (Y1 to Yn) arranged in directions intersecting each other,
A liquid crystal layer is interposed between the segment electrodes X (X1 to Xm). Each common electrode Y and segment electrode X
The liquid crystal layer at the intersection of is the pixel. That is, here, pixels of n × m dots are arranged in a matrix.

This display-integrated tablet has the advantage that the grid-like electrode pattern is not seen compared to the tablet on a liquid crystal display and is easy to see. Therefore, there is an advantage that cost reduction and reduction in size and weight are facilitated.

The common drive circuit 2 for driving the common electrode Y and the segment drive circuit 3 for driving the segment electrode X are connected to a display control circuit 5 and a position detection control circuit 6 via a switching circuit 4. And connected to. The switching circuit 4 is controlled to be switched by a control circuit 7, and outputs the output from the display control circuit 5 during the display period to the driving circuits 2, 3.
, And outputs the output from the position detection control circuit 6 to the drive circuits 2 and 3 during the position detection period.

In the display period, the display control circuit 5 outputs the shift data S, the inverted signal FR, the clocks CP1 and CP2, and the display data D0 to D3 from the respective output terminals.

The clock CP1 is a clock having a cycle of a scanning period for scanning pixels of one row. The clock CP1 is connected to the clock input terminal CK of the common drive circuit 2 from the output terminal CP10 of the switching circuit 4 and to the latch of the segment drive circuit 3. It is input to the pulse input terminal LP. The shift data S is a pulse signal for designating each common electrode Y, is output from the output terminal S0 of the switching circuit 4, and
From the shift data input terminal D101 of the clock CP
Input in synchronization with 1.

In response to the shift of the shift data S, a drive signal is output to the common electrode Y from the output terminal of the common drive circuit 2 corresponding to the shift. This drive signal is supplied with bias voltages V0 to V supplied from the DC power supply circuit 12.
5 is generated.

The clock CP2 is a clock whose period is a period obtained by dividing a scanning period for scanning pixels of one column into a plurality of periods, and is output from the output terminal CP20 of the switching circuit 4,
It is input to the clock input terminal XCK of the segment drive circuit 3.

The display data D0 to D3 are output from the output terminal Dout of the switching circuit 4, input to the input terminals D0 to D3 of the segment driving circuit 3, and output from the segment driving circuit 3.
Are sequentially taken into the registers inside. When the display data corresponding to the pixels of one row is taken in, the display data is latched at the timing of the clock CP1 input to the latch pulse input terminal LP, and the drive signal corresponding to each display data is driven by the segment drive. The signal is output from the output terminal of the circuit 3 to the segment electrode X. This drive signal is also created based on the bias voltages V0 to V5 supplied from the DC power supply circuit 12.

The inversion signal FR is a signal for periodically inverting the polarity of the voltage applied to the liquid crystal to prevent the liquid crystal from being deteriorated by electrolysis.

By the operation of the common drive circuit 2 and the segment drive circuit 3, the pixels of the liquid crystal panel 1 are driven according to the row order, and an image corresponding to the display data is displayed on the liquid crystal panel 1.

On the other hand, during the position detection period, the position detection control circuit 6 outputs the shift data Sd and the inverted signal F from each output terminal.
Rd, clocks CP1d, CP2d, drive data D0d
To D3d.

The clock CP1d is a clock for outputting a scanning period for scanning the common electrode Y for one row. The output terminal CP10 of the switching circuit 4 outputs the clock input terminal CK of the common drive circuit 2 and the latch of the segment drive circuit 3. It is input to the pulse input terminal LP.

The shift data Sd is a pulse signal for specifying each common electrode Y, is output from the output terminal S0 of the switching circuit 4, and is transmitted from the shift data input terminal D101 of the common drive circuit 2 to the clock CP1d. Input synchronously. In response to the shift of the shift data Sd, a drive signal is output from the output terminal of the common drive circuit 2 corresponding to the shift value to the common electrode Y. This drive signal is generated based on bias voltages V0 to V5 supplied from DC power supply circuit 12.

The clock CP2d is a clock having a period of a scanning period for scanning one column of the segment electrodes X, and is output from the output terminal CP20d of the switching circuit 4 and input to the clock input terminal XCK of the segment driving circuit 3. You.

The drive data D0 to D3 are output from the output terminal Dout of the switching circuit 4, input to the input terminals D0 to D3 of the segment drive circuit 3, and
Is taken into the register 20 in the register. When drive data corresponding to the segment electrodes X for one row is taken in, these drive data are latched at the timing of the clock CP1d input to the latch pulse input terminal LP, and drive signals corresponding to each drive data are output. The signal is output from the output terminal of the segment drive circuit 3 to the segment electrode X. This drive signal is also generated based on the bias voltages V0 to V5 supplied from the DC power supply circuit 12.

The inversion signal FRd is a signal for periodically inverting the polarity of the voltage applied to the liquid crystal to prevent the liquid crystal from being deteriorated by electrolysis.

FIG. 2 is a timing chart showing the drive timing of the display-integrated tablet during the position detection period. As shown in FIG. 2, the position detection period is divided into an X coordinate detection period and a subsequent Y coordinate detection period.
During the X coordinate detection period, the segment electrodes X are sequentially driven by a lines, and during the Y coordinate detection period, the common electrodes Y are sequentially driven by b lines. The reason why a plurality of pulses are simultaneously applied is to increase the detection voltage by increasing the induced voltage of the detection pen 8 and to shorten the detection period.

As shown in FIG. 3, a voltage is induced in the detection pen 8 by the electrostatic coupling between the detection pen 8 and the scanning electrodes X and Y. The induced voltage of the detection pen 8 is amplified by the amplifier 9. Based on the output of the amplifier 9 and the timing signal from the control circuit 7, the X coordinate detection circuit 10 detects the X coordinate, and the Y coordinate detection circuit 11 Detect the Y coordinate.

In general, when a DC electric field is continuously applied to the liquid crystal during the display period of the liquid crystal panel, the liquid crystal is electrolyzed and its performance is deteriorated. Is performed. This display driving process inverts the polarity of the inter-electrode voltage while maintaining the absolute values of the voltages applied to the common electrode and the segment electrode of the liquid crystal panel, so that the average value of the inter-electrode voltage becomes “0”. The switching scan is performed several tens times in the display period of one frame.

FIG. 4 is a timing chart for explaining the display operation of liquid crystal panel 1. In the liquid crystal display, as described above, a voltage necessary for displaying one row is applied to all the segment electrodes X, and at the same time, a selection voltage for display is applied to the common electrode Y corresponding to the row displaying the same. FIG.
(7) is a diagram for explaining this display operation in detail.
It shows how the polarity of the voltage applied to the common electrode Y and the segment electrode X changes when the inversion signal FR switches between high level and low level during a frame.

When the inverted signal FR is at a low level, the selection voltage of the common electrode Y is V0, which is described as "ON" in FIG. 4, and when the inversion signal FR is at a high level, the selection voltage is V5.
Similarly, it is described as “ON” in FIG. When the inversion signal FR is at a low level, the voltage of the segment electrode X is V5, which is also described as “on”. When the inversion signal FR is at a high level, the voltage is V0. It is written.

The display is performed only on the pixels whose common electrode and the segment electrode that cross each other are “ON”, and the display is not performed on the pixels where one or both of them are not “ON”. That is, only the pixel whose absolute value of the voltage between the two electrodes is V5-V0 is displayed, and the polarity thereof is determined by the inversion signal FR.

In FIG. 4, the inverted signal FR changes at time t.
At this time, the polarities of the voltages of all the common electrodes and the segment electrodes change. At this time, when the detection pen 8 is placed on the liquid crystal panel 1, the detection pen 8 A spike noise-like voltage as shown in FIG. FIG. 5 is an enlarged waveform diagram of the spike noise-like voltage.

The induced voltage Exp, Ey of the detection pen 8 during the detection period as shown in FIG.
p (indicated by Ep in FIG. 6). Further, this proportional relationship is substantially established even if the detection pen 8 is separated from the surface of the liquid crystal panel 1 or the contrast is adjusted as shown in FIG. Furthermore, this proportional relationship is established at all positions of the liquid crystal panel 1. This is a natural electrical phenomenon because the voltage applied to the same electrode is induced by the same electrode in the same drive circuit using the same power supply, although the timing is different.

Therefore, a DC voltage is generated by rectifying the induced voltage (spike-like electrostatic noise) of the detection pen 8 due to the AC drive during the display period and holding the peak value, and the DC voltage is held until the coordinate detection period. By performing a binarization process on the output (induced voltage) from the detection pen 8 based on the DC voltage, a stable and highly accurate operation can be performed regardless of the distance or contrast adjustment between the detection pen 8 and the liquid crystal panel 1. Coordinate detection processing can be performed.

FIG. 3 shows the detecting pen 8 and the coordinate detecting circuit 1.
FIG. 3 is a circuit diagram showing a configuration related to 0 and 11; In FIG. 3, the control circuit 25 is a circuit that generates a DC voltage based on the induced voltage of the detection pen 8. That is, the control circuit 2
Reference numeral 5 denotes a spike-like voltage (indicated by Ea in FIG. 5) diode 21 and a resistor 21 which take in an output VOP obtained by amplifying an induced voltage of the detection pen 8 by an operational amplifier 9 and which are detected by AC drive during a display period of the liquid crystal panel 1. After rectifying by R and generating a DC voltage proportional to the peak value,
The capacitor C is charged.

Thereafter, the DC voltage is applied to the potentiometers 27 and 2
The adjustment is made in step 8 to make the reference voltage of the comparators 23 and 24. The operational amplifier 26 converts the proportional value of the induced voltage by the AC driving, which is charged and held in the capacitor C, into a voltage required for the reference values of the comparators 23 and 24.

The analog gate circuit AGc discharges the voltage held in the capacitor C based on the control signal gc until the coordinate detection scan in the next cycle after the coordinate detection scan in the coordinate detection period is completed. In other words, it clears and provides information on the latest induced voltage of the detection pen 8 immediately before the next coordinate detection scan. Therefore, the analog gate circuit AGc is in a high impedance state during the detection period and at least immediately before the period in which the spike-like voltage is fetched by the AC conversion of a certain level or more.

It is also possible to replace the analog gate circuit AGc with a resistor Rg. In this case, the time constant C
It is appropriate to select Rg to be in the same order as the coordinate detection cycle. In this case, the voltage of the capacitor C substantially follows the situation of the detection pen 8, and in consideration of reduction in the number of parts and cost, the analog gate circuit AGc
This is more general than using.

The analog gate circuits AGx and AGy output X
Alternatively, based on the control signals gx and gy in the Y-coordinate detection period, the comparator supplies only the voltage for the period required for each coordinate detection to the comparators 23 and 24. Further, the analog gate circuits AGx and AGy may be provided at the subsequent stage of the comparators 23 and 24, and may be separated after binarizing all the detected voltages.

FIG. 9 is a circuit diagram for explaining another embodiment. In FIG. 9, an amplifier 68 is a variable gain amplifier including an operational amplifier, and supplies an external voltage to a terminal b.
To change the amplification factor. The output VOP of the amplifier 68 is converted into a DC voltage by the control circuit 25 and fed back to the amplifier 68. In the amplifier 68, the amplification factor is adjusted based on the voltage input from the terminal b so that the output voltage VOP becomes a constant value.
This constant value is adjusted by a volume inside the control circuit 25.

By such an operation, the output voltage VOP from the amplifier 68 becomes constant, and even if the distance between the detection pen 8 and the liquid crystal panel 1 changes or the display contrast of the liquid crystal panel 1 is adjusted, the detection pen 8 does not change. , The peak value of the voltage induced is constant. Therefore, the comparators 23 and 24
Even if the reference voltage value is fixedly set by the potentiometers 64 and 63, stable and highly accurate operation can be performed.

Next, still another embodiment will be described. In the present embodiment, the voltage value of the scanning voltage to the common electrode and the segment electrode during the position detection period is controlled based on the DC voltage generated by the control circuit 25 in FIG.

That is, the fact that the spike-like voltage induced in the detection pen 8 during the display period is low is as shown in FIG.
This means that the detection voltage of the detection pen 8 during the position detection period is low. Therefore, when the DC voltage is low, the bias voltages V0 to V5 from the DC power supply circuit 12 are controlled so that the scanning voltage applied to the common electrode and the segment electrode during the position detection period increases. That is, in the power supply circuit 12 shown in FIG.
When the DC voltage accumulated in the DC voltage V5 decreases, the bias voltages V0 to V5 are controlled to a high voltage value by setting the contrast adjustment volume VR substantially low. The bias voltage controlled to the high voltage value is supplied to the common electrode drive circuit 2 and the segment electrode drive circuit 3,
The voltage value of the scanning voltage increases, and the voltage value induced to the detection pen 8 during the coordinate detection period always maintains a normal voltage value without lowering.

Therefore, even when the detection pen 8 is separated from the liquid crystal panel 1 as a detection surface, normal coordinate detection can be performed.
The control of the bias voltages V0 to V5 is performed only during the position detection period, and is not performed during the display period.

In each of the above embodiments, it is necessary to limit the operation area. That is, in practice, when the detection pen 8 is separated from the liquid crystal panel 1 serving as the detection surface by 5 mm or more, the spike voltage due to the AC driving during the display period also becomes small, and the binarization is performed based on the spike voltage. This is because when the process is executed, the detection pen 8 may erroneously detect low-level noise as coordinates.

Instead of using the spike-like voltage generated during the display period of the liquid crystal panel 1 as a reference, a reference voltage is simultaneously applied to both or one of all the common electrodes and all the segment electrodes between the display period and the coordinate detection period. This may be detected by the detection pen 8 and the detected value may be used as a reference value.

As described above, according to the present embodiment, even if the distance between the detection pen 8 and the liquid crystal panel 1 fluctuates or the contrast of the liquid crystal panel 1 is adjusted, the coordinate detection operation can be realized with high accuracy. can do.

[0094]

As described above, according to the present invention, the coordinate designating means in the coordinate detection period can be obtained by separating the coordinate designating means from the liquid crystal panel which is the detection surface by several mm or adjusting the contrast of the liquid crystal panel. Even if the induced voltage fluctuates, at the stage of binarizing the induced voltage, the reference voltage of the comparator performing the binarizing process is automatically changed and set, or the amplification factor of the amplifier is automatically adjusted. Thus, coordinate detection can always be performed with high accuracy.

When the DC voltage is lower than the predetermined reference voltage, the voltage value induced in the coordinate indicating means during the coordinate detection period is also low. Therefore, when the DC voltage is low, the bias voltage supplied to the driving means is increased. As a result, the scanning voltage applied to the electrodes of the liquid crystal panel also increases, and a normal voltage value can be maintained without lowering the voltage value induced in the coordinate indicating means during the coordinate detection period. Also in this case, similarly high coordinate detection accuracy can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a coordinate input device according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the coordinate input device during a position detection period.

FIG. 3 is a diagram showing an electrical connection between the liquid crystal panel 1 and a detection pen 8;

FIG. 4 is a timing chart for explaining the operation of the coordinate input device shown in FIG. 1 during a display period.

FIG. 5 is a waveform diagram showing a voltage induced in a detection pen 8;

FIG. 6 shows an alternating-current induced voltage EA induced in the detection pen 8;
It is a graph which shows the relationship with coordinate detection induction voltage EP.

FIG. 7 is a graph showing a relationship between a distance h between the detection pen 8 and the liquid crystal panel 1 and an AC induction voltage EA.

8 is a circuit diagram showing a configuration related to a detection pen 8 and detection circuits 10 and 11 in the coordinate input device shown in FIG.

FIG. 9 is a circuit diagram for explaining another embodiment of the present invention.

FIG. 10 is a circuit diagram showing a basic configuration of a DC power supply circuit 12 used in the coordinate input device shown in FIG.

FIG. 11 is a block diagram showing a configuration of a coordinate input device as a conventional example.

FIG. 12 is a block diagram showing a basic configuration of another conventional coordinate input device.

FIG. 13 is a circuit diagram showing a configuration related to a detection pen 508 and a coordinate detection circuit in a conventional coordinate input device.

FIG. 14 is a timing chart showing the operation of a coordinate input device as a conventional example.

[Explanation of symbols]

 Reference Signs List 1 liquid crystal panel 2 common drive circuit 3 segment drive circuit 4 switching circuit 5 display control circuit 6 position detection control circuit 7 control circuit 8 detection pen 9 amplifier 10 X coordinate detection circuit 11 Y coordinate detection circuit 12 DC power supply circuit 23, 24 comparator 25 Control circuit 26 Operational amplifier 27, 28 Volume

Claims (4)

(57) [Claims] 1. A liquid crystal panel in which a plurality of strip-shaped segment electrodes and a common electrode are arranged orthogonal to each other; and a display voltage is sequentially applied to the segment electrodes and the common electrode for driving the liquid crystal panel for display; Driving means for performing AC drive to prevent electrolysis of liquid crystal, coordinate indicating means having relatively high input impedance electrodes electrostatically coupled to the segment electrodes and the common electrode, and a liquid crystal panel display period. Subsequently, during a coordinate detection period which does not contribute to the display to be set, a voltage for coordinate detection lower than a threshold voltage required for liquid crystal display is sequentially applied to the common electrode and the segment electrode, and the voltage is induced to the electrode of the coordinate indicating means. Amplifying the voltage, detecting the generation timing and waveform of the induced voltage, and applying the coordinate detection voltage and the generation timing of the induced voltage. And a coordinate detection unit that calculates input coordinates based on the timing and the coordinate detection unit, wherein the coordinate detection unit detects a voltage induced on the electrode of the coordinate instruction unit during a period other than the coordinate detection period, DC voltage generating means for generating a DC voltage proportional to the detected value and holding the DC voltage until the coordinate detection period, and an analog voltage induced on the electrode of the coordinate indicating means during the coordinate detection period using the DC voltage as an auxiliary voltage And a processing means for performing a normalization process. 2. The DC voltage generating means generates a DC voltage proportional to a peak value of a spike-like voltage induced on an electrode of a coordinate indicating means, and the processing means performs a binarization process of the analog voltage. 2. The coordinate input device according to claim 1, further comprising a comparator for setting the DC voltage as a reference voltage of the comparator. 3. The DC voltage generating means generates a DC voltage proportional to a peak value of a spike-like voltage induced on an electrode of the coordinate indicating means, and the processing means amplifies the DC voltage by an induced voltage. 2. The coordinate input device according to claim 1, wherein the analog input is binarized by feeding back to an amplifier to make the peak value of the analog voltage constant. 4. The DC voltage generating means generates a DC voltage proportional to a peak value of a spike-like voltage induced on an electrode of the coordinate indicating means, and the processing means applies a bias to the driving means during a position detection period. 2. The coordinate input device according to claim 1, wherein the DC voltage is fed back to a power supply for supplying a voltage, and the bias voltage value is controlled to increase according to the decrease in the DC voltage.