JP2652976B2 - Exclusive control method of shared memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an exclusive control method of a shared memory in a multiprocessor device in which a plurality of processors communicating via a shared memory operate simultaneously.

(Prior Art) Conventionally, mechanisms for implementing exclusive control of a shared memory in a multiprocessor device in which a plurality of processors communicating via the shared memory operate simultaneously are roughly classified into two mechanisms. This is shown below.

1.Test and Set, Read Modify Write, Fetch and Add, Com
Provide machine instructions, such as pare and Swap, that implement read, value manipulation, and rewrite as inseparable operations on memory.

2. A hardware memory having control for exclusive control is provided, and exclusive control is realized by accessing the memory with a normal instruction. For example, Atomic Lock Memory
Read access to a specific memory address (read
(Access), the contents of the memory are passed to the CPU, and at the same time, the contents of the address are set to 1 (lock state) by hardware in the memory. The read access to the locked memory is delayed until the content of the address becomes 0 (unlock). The contents of the address are reset to 0 by the write access. Thereby, exclusive control is realized. This is equivalent to hardware implementation of Test and Set.

(Problems to be Solved by the Invention) In recent years, RISC processors have become widespread. In RISC processors, one memory access or one operation is basically used for one instruction in order to minimize the disturbance of the pipeline. As described in 1 above, those that execute two memory accesses inseparably fall outside the scope of RISC and are difficult to realize.

On the other hand, in the atomic lock memory, exclusive control resources for the memory address can be realized, but the hardware becomes complicated.

When the number of processors is small and the contention ratio of exclusive resources is small, only one exclusive control resource is required, and a hardware system that is easier to realize is desired.

In the conventional exclusive control method of the shared memory, a storage area for locking is prepared in addition to the storage area to be operated, and a lock operation and an unlock operation instruction for the storage area are added to the program. In a RISC processor whose calculation speed is extremely fast with respect to the memory access time, such an increase in the number of memory access operations is not desirable.

Therefore, an object of the present invention is to use simple hardware,
Another object of the present invention is to provide a shared memory exclusive control method that does not increase the number of memory accesses for exclusive control.

(Means for Solving the Problems) An exclusive control method of a shared memory according to the present invention is a multi-processor device in which a plurality of processors that communicate via the shared memory operate simultaneously. A shared memory exclusive control system that prohibits another processor from accessing the shared memory by using a normal access space, a first exclusive control access space, and a second exclusive control access space in the address space of the shared memory. And the exclusive control access space of the plurality of processors is accessed three times. The plurality of processors access to the shared memory includes a normal access through the normal access space and a first exclusion through the first exclusive control access space. A control access and a second exclusive control access through the second exclusive control access space. The processor occupies the shared memory when the shared memory is accessed by the first exclusive control access, and the shared memory when the shared memory is accessed by the second exclusive control access. Is released.

(Operation) In the present invention, when starting exclusive control, an operation on data on the shared memory is performed as the first exclusive control access through the exclusive control access space, and the data operation at the end of the exclusive control is performed by the exclusive control access. By performing the second exclusive control access through the space, it is possible to realize the exclusive control without increasing the number of memory accesses, in the case of the access without the exclusive control.

The present invention can be realized by making some improvements to the arbitration circuit indispensable for the shared memory mechanism, and the device scale can be reduced.

(Embodiment) An exclusive control method for a shared memory according to the present invention
This will be described with reference to FIGS. FIG. 1 is a diagram showing a memory map according to one embodiment of the present invention.

The processor 16 can perform writing and reading operations on the shared memory 11 from either of the exclusive control access space 12 and the normal access space 13. An access via the exclusive control access space 12 is an exclusive access 14, and an access via the normal access space 13 is a normal access 15.

1. Read operation via exclusive control access space 12
This lock operates as a lock for the shared memory 11,
After the operation, access (14, 15) to the shared memory 11 other than the processor that performed the reading operation is completely prohibited until there is an unlock operation of the shared memory 11.

2. Write operations via the exclusive control access space 12
It operates as an unlocking of the shared memory 11, and after this unlocking operation, any processor can access the shared memory 11 (14, 15).

3. The normal access 15 does not affect the state of the access right determined by the lock operation and the unlock operation in the exclusive access 14 at all.

The above three are control methods for realizing the present embodiment, and are permitted to be performed only by the processor permitted to access the shared memory.

FIG. 2 shows the configuration of this embodiment in which the number of processors is two as shown in FIG. 11 is a shared memory, 16 is a processor, 23 is an address decoder, 24 is an arbitration circuit, and 25 is a buffer. If the access to the shared memory 11 is to the exclusive control access space 12 in FIG. 1, the address decoder N (N = 0 or 1)
selNx is asserted, and if the signal is for the normal access space 13, the signal selNn is asserted.

The arbitration circuit 24 arbitrates access to the shared memory 11,
Assert a signal to open buffer 0 or buffer 1 according to the result of the arbitration. The arbitration circuit 24 includes a processor 0
Or access from processor 1 to shared memory 11
Signals rd0 and rd1 are input from each processor to determine whether the access is read access or write access.

Further, when the processor 0 or the processor 1 accesses the shared memory 11, the processor 0 or the processor 1 samples the en0 and en1 signals, respectively. If the signals are not asserted,
Assuming that shared memory access was not obtained,
Idle until the signal is asserted.

FIG. 3 shows a state transition diagram of the arbitration circuit 24. Fig. 3 shows mo
It is a transition diagram of an or type, and a state name is in a bracket. The state of the signals en0 and en1 when the atoto is set to 1 is shown in a circle.
In each state transition, the condition is not satisfied (negated state) is indicated by an overline, or is indicated by “+”, and and is indicated by “•”. The rd0 and rd1 signals are asserted at the time of read access and negated at the time of write access.

 The arbitration circuit 24 transitions between the following states.

1. No processor is accessing shared memory 11 [idle] 2. Processor N is accessing shared memory 11, but
The status returns to [idle] as soon as access is completed. [AccN] 3. A state in which the processor N exclusively accesses the shared memory 11, and occupies the shared memory 11 even after the access is completed unless an unlook operation is performed. [ExN].

The exclusive control operation and the state of the arbitration circuit 24 in this embodiment are described below.

1. Processor N has exclusive control access space in FIG.
By write access to 12, the state of the arbitration circuit 24 becomes exN
To prohibit any access to the shared memory 11 by processors other than the processor N (14 and 15 in FIG. 1).

2. Thereafter, in the normal access 15 shown in FIG. 1, the arbitration circuit 24 does not transit in the lock state of exN.

3. Further, when the processor N makes a read access to the exclusive control access space 12 in FIG. 1, the state is changed to AccN, and as soon as the read access is completed, the state is changed to the idle state and the shared memory other than the processor N is returned again. Access to 11 becomes possible.

In the present embodiment, it is only necessary to extract an extra signal selNx from the address decoder 23 of FIG. 2 with respect to the ordinary shared memory device, and to the arbitration circuit 24, the state transition diagram of FIG. It is only necessary to add one state of enN for each processor (referred to as processor N), and the device scale can be reduced.

 Next, the programming of this embodiment will be described.

When the value of a certain variable A is read out, the value of the variable A becomes 1
Test and set an instruction to execute the operation inseparably
Call. This can be implemented as follows using this embodiment.

1. Variable A via exclusive control access space 12 in FIG.
Read the value of. At the same time, the shared memory 11 is locked.

2. 1 is assigned to the variable A via the exclusive control access space 12 in FIG.
To unlock the shared memory 11.

Linked list operations are one of the exclusion processes frequently used in the OS. FIG. 4 shows a state before the operation of inserting the cell k41 between the cell i42 and the cell j43. 44 is a pointer pointing to the forward (rear) cell, and 45 is a pointer pointing to the backward cell. After the operation, the state is as shown in FIG.

FIG. 6 shows a programming example of this operation. In FIG. 6, reg indicates the register in the CPU, (Fj) indicates the value stored in the variable Fj, and reg ← (Fj) indicates that the value stored in the variable Fj is transferred to the register.

(Effect of the Invention) The present invention can be realized by adding a slight improvement to the arbitration circuit indispensable for the shared memory mechanism, and can be realized with a small amount of hardware.

In addition to the two programming examples described in the embodiments, ordinary exclusive operations such as Compare and Swap and Fetch and Add start with read access and end with write access. Therefore, in the present invention, by performing the lock operation and the unlock operation of the shared memory for the first transfer operation and the last transfer operation, exclusive processing is performed with the same number of instructions as in the case where this operation is implemented without performing exclusive control. Can be described.

Further, considering that the instruction of the RISC processor corresponds to the micro instruction of the CISC, in the present invention, any high-performance instruction of the CISC can be implemented in software on the RISC processor with the same overhead as the CISC.

[Brief description of the drawings]

FIG. 1 is a diagram showing a memory map of one embodiment of the present invention, FIG. 2 is a diagram showing the configuration of this embodiment, FIG. 3 is a diagram showing a state transition of an arbitration circuit 24, and FIG. FIG. 5 is a diagram showing a state before operation of a double linked list according to an example, FIG. 5 is a diagram showing a state after operation of a double linked list according to the present embodiment, and FIG.
The figure shows a programming example of the linked list operation. 11 ... shared memory, 12 ... exclusive control access space, 13 ...
... normal access space, 14 ... exclusive access, 15 ... normal access, 16 ... processor, 23 ... address decoder, 24 ... arbitration circuit, 25 ... buffer, 41 ... cell k,
42 ... cell i, 43 ... cell j, 44 ... forward pointer,
45 ... Reverse direction pointer.

Claims (2)

(57) [Claims] 1. A multiprocessor device in which a plurality of processors communicating via a shared memory operate simultaneously.
An exclusive control method of a shared memory in which a certain processor occupies the shared memory for a certain time and prohibits another processor from accessing the shared memory, wherein an address space of the shared memory includes a normal access space, A first exclusive control access space and a second exclusive control access space are assigned in triple, and the plurality of processors access to the shared memory includes a normal access via the normal access space and a first access to the shared memory. There are a first exclusive control access via the exclusive control access space and a second exclusive control access via the second exclusive control access space, and the plurality of processors are configured to execute the shared memory by the first exclusive control access. When the shared memory is accessed, the shared memory is occupied and the shared memory is accessed by the second exclusive control access. When accessing the exclusive control method of shared memory, characterized in that to release the dedicated of the shared memory. 2. The shared memory exclusive control method according to claim 1, wherein said first exclusive control access is a read access, and said second exclusive control access is a write access.