JP2652974B2 - Field effect transistor - Google Patents

Description

The present invention relates to a Schottky junction field effect transistor (ME).
SFET).

[Conventional technology]

In a high-speed integrated circuit using a III-V compound semiconductor such as gallium arsenide (GaAs), a transistor is directly formed on a semi-insulating substrate.

[Problems to be solved by the invention]

However, the insulating properties of these compound semiconductor semi-insulating substrates depend on fixing the Fermi level to a deep level near the center of the forbidden band. It is called a flexible substrate. In these semi-insulating substrates, when an external electric field is applied, for example, electric charges enter and exit deep levels in the semi-insulating substrate to generate space charges. This space charge has a significant effect on the characteristics of the device fabricated on the substrate.

It has long been known that integrated circuits using FET devices such as GaAs-MESFETs have a characteristic interference effect between elements called a side gate effect. As shown in FIG. 4, when attention is paid to the n-channel FET 2 on the semi-insulating substrate 1, the adjacent element 3 (adjacent FE)
When a negative potential is applied to the n-layer of T or the like, which is called a side gate), there is a phenomenon that the drain current of the FET2 decreases. This phenomenon is typical of the side gate effect. The source of the side gate effect is due to the space charge at the interface with the substrate 1.

Here, let us consider a little more specific situation when an n-channel FET is directly formed on a semi-insulating substrate. Normally, if an n-type channel and a semi-insulating substrate are joined (n
-I junction) and an energy band structure as shown in FIG. 5 similar to the np junction. The n-channel Fermi level is just below the bottom of the conduction band, and the Fermi level of the semi-insulating substrate is near the center of the forbidden band. On the semi-insulating substrate side, negative space charges are accumulated with a width of W, and on the n-channel side, electrons are depleted with a width of d in order to cancel them, and are accumulated as positive space charges.

When a negative potential is applied to the semi-insulating base side in such a state, the ni-junction becomes more like a reverse bias of the pn junction when the portion having space charge spreads further on both sides of the junction. become. When viewed from the n-channel side, the channel is depleted and narrowed by the n-layer due to the ni interface. Assuming that the n-channel is the operation channel of the FET, the narrowing of the channel means a decrease in the drain current of the FET, which explains the situation where the side gate effect occurs.

However, in an MESFET integrated circuit, adjacent elements (side gates) actually exist at a distance of several μm or more. Therefore, a special mechanism is required for the voltage applied to the side gate to affect the ni junction of the FET of interest and cause the side gate effect. In the case of an n-channel FET, one of the functions is a deep level acting as a hole trap existing in a semi-insulating substrate. When a negative voltage is applied to the side gate, the ni junction interface in the channel region of the FET becomes reverse-biased, and the holes are depleted. If the deep level in the semi-insulating substrate works as a hole trap, it is sufficient. Deep levels emit holes and become negatively charged, resulting in extra negative charge accumulation near the ni interface. The charging continues until the reverse bias potential of the ni junction becomes equal to the side gate voltage, and as a result, the side gate voltage directly reaches the ni junction (FIG. 6). Conventionally, in a FET formed on a semi-insulating substrate, the deep level acting as a hole trap has caused a side gate effect.

An object of the present invention is to provide a MESFET having a structure capable of suppressing a side gate effect generated when a MESFET is manufactured on a semi-insulating substrate.

[Means for solving the problem]

The field-effect transistor according to the present invention is an n-type field-effect transistor formed on a semi-insulating substrate, wherein a deep level inherent in the semi-insulating substrate is provided in the semi-insulating substrate region near a conductive type impurity doped region. It has a donor-type deep level with a larger amount and an energy level closer to the conduction band.

[Action]

In the case of an n-channel FET, a deep level acting as a hole trap in a semi-insulating substrate is used as a mechanism for causing the voltage of the side gate to reach the ni junction of the FET channel of interest as described above. There is. As shown in FIG. 1 (a), the deep level acting as a hole trap releases holes to the valence band on the semi-insulating substrate side (i side) of the n-i junction of the FET channel (electrons). Is captured from the valence band) and negatively charged, thereby causing a side gate effect.

However, if there is a donor-type level having a larger amount than the hole trap and having an energy near the conduction band, the Fermi level in the substrate rises to the energy position of the donor, and FIG. ), The level that acts as a hole trap, as described above, should be filled with electrons (since the holes are fully depleted), so that they can no longer emit holes. Therefore, if such a donor type level near the conduction band exists, the occurrence of the side gate effect is suppressed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 2 is a sectional view for explaining an embodiment of the present invention. Regions 6 and 7 in which donor levels near the conduction band are formed by ion implantation of oxygen are formed on a semi-insulating substrate 1 made of GaAs, and an n-type conductive layer is formed by ion implantation of silicon.
By forming the gate electrode with tungsten,
Adjacent n-channel FETs 4 and 5 are formed.

With the configuration shown in FIG. 2, when the adjacent FET 5 is set to a negative potential with respect to the FET 4 by paying attention to the FET 4, the donor near the conduction band is placed in the semi-insulating region near the n-type conductive layer of the FET 4. By disposing the region 6 in which the level is formed, the generation of negative charges at the ni interface on the side of the FET 4 is suppressed, so that the generation of the side gate effect is suppressed.

For the time being, when FET4 is set to a negative potential with respect to FET5 to form a side gate, a region 7 in which a donor level near the conduction band is formed in a semi-insulating region around FET5 is provided.
The occurrence of the side gate effect due to the presence of T4 is suppressed.

As described above, it is effective to arrange the region where the donor level near the conduction band is formed around all the FETs.

Next, the drain currents (I _dss ) of the MESFET of this embodiment and the MESFET of the conventional structure are shown in FIGS. 3 (a) and 3 (b).
In the case of the conventional structure in which the region having the donor level near the conduction band is not arranged, as shown in FIG. 3 (b), when the side gate voltage becomes lower than a certain voltage (-3V in this case), the drain voltage becomes lower. The current (I _dss ) begins to decrease. On the other hand, in the structure of the present embodiment, as shown in FIG. 3 (a), even if the side gate voltage is lowered, the drain current (I _dss )
No decrease is seen.

In this embodiment, the region where the donor level closer to the conduction band is formed by ion implantation of oxygen is formed. However, even if the region where the donor level closer to the conduction band is formed by ion implantation of boron is formed, FIG. As shown in (a), no decrease in drain current ( _Idss ) is observed.

In this embodiment, the GaAs-MESFET is used. However, if the field effect transistor is a field effect transistor using a semi-insulating substrate, the present invention can be applied. A III-V compound semiconductor, for example, InP or the like may be used.

〔The invention's effect〕

As described above, according to the present invention, by arranging a region in which a donor level near a conduction band is formed in a semi-insulating region near an impurity conductive layer of an FET, an adjacent FET is negative with respect to one of the other. When applied to the potential, as shown in FIG. 1 (b), the emission of holes from the hole trap is suppressed by the presence of the donor level at the Fermi level, and as a result, the side gate The effect can be suppressed.

[Brief description of the drawings]

FIGS. 1 (a) and 1 (b) are energy band diagrams showing the energy of a deep level in a semi-insulating substrate according to an embodiment of the present invention, and FIG. 2 is an illustration of an embodiment of the present invention. 3 (a) and 3 (b) are characteristic diagrams of drain current with respect to side gate voltage in the FET of one embodiment of the present invention and the FET of the conventional structure, and FIG. 4 is a side view of the conventional FET. FIG. 5 is a schematic view for explaining the gate effect, FIG. 5 is an energy band diagram of the ni junction of the conventional FET, and FIG. 6 is an energy band showing the potential energy between the FET and the side gate in the conventional structure FIG. 1 ... semi-insulating substrate, 2,4,5 ... n-channel FET, 3 ...
Side gates, 6, 7: regions where donor-type levels are formed.

Claims (1)

(57) [Claims] 1. An n-type field effect transistor formed on a semi-insulating substrate, wherein the semi-insulating substrate region near a conductive type impurity doped region has a larger amount than a deep level inherent in the semi-insulating substrate. And a donor-type deep level having an energy level close to the conduction band.