JP2518381B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is found in field effect transistors (FETs), such as Schottky junction field effect transistors (MESFETs) made using semi-insulating semiconductor substrates. , A FET structure capable of suppressing an interference effect between FETs.

[Prior Art] In a high-speed integrated circuit using a III-V group compound semiconductor such as gallium arsenide (GaAs), a transistor is directly manufactured on a semi-insulating substrate.

However, the insulating properties of these compound semiconductor semi-insulating substrates depend on fixing the Fermi level to a deep level near the center of the forbidden band, and in that sense, they are distinguished from perfect insulators. It is called a semi-insulating substrate. In these semi-insulating substrates, when an external electric field is applied, for example, electric charges enter and exit deep levels in the semi-insulating substrate to generate space charges. This space charge has a great influence on the characteristics of the device formed on the substrate.

It has long been known that an integrated circuit using an FET device such as a GaAs-MESFET has a characteristic interference effect between elements called a side gate effect. An n-channel F having a gate electrode 3, a source region 10 and a drain region 11 on a semi-insulating substrate 9 as shown in FIG.
When attention is paid to ET5, a typical phenomenon is that the drain current of the FET5 decreases as a negative potential is applied to the adjacent n region (side gate 6).
The cause of this side gate effect is due to the space charge at the interface with the substrate.

Here, let us consider a little more specific situation when an n-channel FET is directly formed on a semi-insulating substrate. Normally, if an n-type channel and a semi-insulating substrate are joined (n
-I junction) and np junction have similar band diagrams as in FIG. The n-channel Fermi level is just below the bottom of the conduction band and the semi-insulating substrate Fermi level is near the center of the forbidden band. The negative space charge is W on the semi-insulating substrate side.
, The electrons are depleted in the width of d to cancel it, and positive space charges are accumulated on the n-channel side.

If a negative potential is applied to the semi-insulating substrate side, a space-charged portion of this ni junction will spread further on both sides of the junction, just like a reverse bias of a pn junction. . When viewed from the n-channel side, the n-layer of the channel is further depleted by the n-i interface and narrowed. Assuming that the n-channel is the operation channel of the FET, the narrowing of the channel means a decrease in the drain current of the FET, which explains the situation where the side gate effect occurs.

As described above, it is understood that if a voltage is directly applied to the ni junction, the drain current of the n-channel FET is affected.

However, in an MESFET integrated circuit, adjacent elements (side gates) are actually separated by several μm or more. Therefore, a special mechanism is required for the voltage applied to the side gate to reach the ni junction of the FET of interest and cause the side gate effect, which is inter-element interference. In the case of an n-channel FET, one of the mechanisms is injection of holes from the Schottky junction metal used as the gate electrode. The injection of holes causes a double injection of carriers into the semi-insulating substrate together with the injection of electrons from the side gate, resulting in the accumulation of negative charges near the ni interface, resulting in the ni junction. The side gate voltage reaches directly to. Conventionally, in a FET fabricated on a semi-insulating substrate, the hole injection has caused a side gate effect.

In addition, the above description is the same in the case of the p-channel MESFET if the roles of electrons and holes are exchanged.

[Problems to be Solved by the Invention]

It is an object of the present invention to provide a field effect transistor having a shape capable of suppressing the side gate effect when manufactured on a semi-insulating substrate as described above.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a semi-insulating semiconductor substrate having a surface on which an active region of one conductivity type is formed, and a metal material forming a Schottky barrier and a constituent material of the semi-insulating semiconductor substrate. In a field effect transistor using an electrode, a level that acts as a charge trap for carriers of opposite conductivity type is formed in a semi-insulating region on the surface of a semi-insulating semiconductor substrate in contact with a gate metal.

[Action]

In the case of an n-channel FET, there is a hole injection from a Schottky junction metal as a mechanism for making the side gate voltage as described above reach the ni junction of the FET of interest. FIGS. 4 (a) and 4 (b) show energy bands when the Schottky junction metal and the semi-insulating substrate or the n substrate are in contact with each other in the case of GaAs. In the case of GaAs, the energy position of the Schottky junction is almost determined by the surface level density of GaAs, which is about 0.9 eV from the conduction band, which is slightly closer to the valence band. Therefore, when the deep level contacts the semi-insulating substrate near the center of the forbidden band, the potential energy has a shape slightly higher in the vicinity of the Schottky junction metal as shown in FIG. 4 (a). On the other hand, if it comes in contact with n-type metal,
As shown in FIG. 3B, the shape is largely curved near the Schottky junction metal. Therefore, from the viewpoint of injecting holes into the GaAs from the Schottky junction metal side, the barrier against holes is lower when contacting the semi-insulating substrate than when contacting the n-type substrate. The holes are likely to be injected.

Generally, MESFET has a gate shape as shown in FIG. 5 (a) is a plan view and FIG. 5 (b) is a sectional view taken along the line AA of FIG. 5 (a). In these figures, 1 is a source electrode, 2 is a drain electrode, Reference numeral 3 is a gate electrode, 4 is an n-type conductive layer, and 9 is a semi-insulating substrate.
In this shape, in order to cut off the FET by the gate voltage, as shown by hatching in FIG. 5 (a), the Schottky junction metal (gate electrode 3) is formed even on the semi-insulating substrate. It needs to be projected. Therefore,
The hole injection from the protruding region directly contributed to the generation of the side gate effect.

However, as shown in FIG. 1, when a level functioning as a hole trap is arranged in the semi-insulating regions 7 and 8 in contact with the Schottky metal (gate electrode 3), when the Schottky metal side is biased to a positive potential. , Holes injected from the Schottky junction metal are captured, and the hole trap is positively charged. Then, the curvature of the potential due to the positive charges in the regions 7 and 8 is increased to eventually form the potential as shown in FIG. When there is no hole trap, the Schottky metal side is biased to the same voltage, as shown in FIG. 6 (b). By comparing the two, it can be seen that the case (a) in which the hole trap exists has a higher barrier against holes. The injection of holes over the potential barrier is approximately proportional to exp (-qΔV-kT), as in the case of thermionic emission. Here, ΔV is the height of the potential barrier, q is the elementary charge, k is the Boltzmann constant, and T is the temperature. At room temperature, (kT / q) × log _e 10
Since it is 60 mV, even if the potential barrier is increased by 60 mV, the hole injection amount is reduced to 1/10. Due to this effect, the injection of holes is significantly reduced, and the occurrence of the side gate effect is significantly suppressed.

In the case of a p-channel FET as well, the side gate effect can be suppressed by the same effect based on the argument that the roles of holes and electrons are exchanged in the above discussion.

〔Example〕

An embodiment of the present invention will be described with reference to FIG. 1 (a) is a plan view and FIG. 1 (b) is a sectional view taken along the line AA of FIG. 1 (a).

In this embodiment, n formed on a GaAs semi-insulating substrate 9 is used.
In the field effect transistor of the channel, in the semi-insulating regions 7 and 8 in contact with the gate electrode 3 on the surface of the semi-insulating substrate 9,
A level that acts as a hole trap is formed. In the figure,
Reference numeral 1 is a source electrode, 2 is a drain electrode, and 4 is an n-type conductive layer. The n-type conductive layer 4 is formed by ion implantation of silicon, and the gate electrode 3 is tungsten. The deep level to be the hole trap was formed by ion implantation of chromium.

FIG. 7A shows a change in drain current of the n-channel field effect transistor of GaAs having such a structure depending on the side gate voltage. For comparison, FIG. 7B shows changes in the drain current of the conventional FET shown in FIG. As shown in FIG. 7 (b), in the case of the conventional FET, the side gate voltage has a certain voltage (−3 in this case).
V) or less, the drain current starts to decrease. However, in the case of FIG. 7 (a) using the structure of the present invention, even if the side gate voltage is further decreased, the drain current does not decrease. I can't.

Although the above is an example of the n-channel field effect transistor, the p-channel field effect transistor was manufactured by ion-implanting oxygen in order to form a deep level serving as an electron trap. In this case, the effect of the invention was recognized as in the case of the n-channel field effect transistor described above.

The field effect transistor of the present invention is applicable to any field effect transistor other than MESFET as long as it is a field effect transistor using a semi-insulating substrate. The semiconductor material of the substrate may be a III-V group compound semiconductor other than GaAs, such as InP.

〔The invention's effect〕

As described above, the structure of the field-effect transistor of the present invention is an n-channel (p-channel) field-effect transistor formed on a semi-insulating substrate, and the semi-insulating region on the surface of the semi-insulating substrate is in contact with the gate metal. In addition, since the level that functions as a hole trap (electron trap) is formed, it is very effective in suppressing the side gate effect.

[Brief description of drawings]

FIG. 1 is a view showing the structure of an n-channel field effect transistor which is an embodiment of the present invention, (a) is a plan view,
(B) is a sectional view, FIG. 2 is a sectional view showing the positional relationship between the FET and the side gate, FIG. 3 is a band diagram for explaining the ni junction, and FIG. 4 (a) is a Schottky junction metal. FIG. 4 (b) is a band diagram for explaining the junction between a Schottky junction metal and an n-type substrate, and FIG. 5 is a diagram for explaining the conventional MESFET shape. It is a figure showing (a)
Is a plan view, (b) is a cross-sectional view, FIG. 6 is a band diagram for explaining a potential barrier against hole injection, (a) is a band diagram in the presence of hole traps, (b) is the existence of hole traps. FIG. 7 is a band diagram in the case of not performing, and FIG. 7 is a diagram showing the fluctuation of the FET characteristics due to the side gate voltage. (A) is the case of the structure of the present invention, and (b) is the case of the conventional structure. 1 ... Source electrode 2 ... Drain electrode 3 ... Gate electrode 4 ... N-type conductive layer 5 ... N-channel FET 6 ... Side gate 7,8 ... Region where hole trap is formed 9 ... Semi-insulation Substrate 10 …… Source region 11 …… Drain region

Claims (1)

(57) [Claims] 1. A field effect transistor comprising a semi-insulating semiconductor substrate having an active region of one conductivity type formed on one surface thereof, the gate electrode being a constituent material of the semi-insulating semiconductor substrate and a metal material forming a Schottky barrier. A field effect transistor, wherein a level that acts as a charge trap for carriers of opposite conductivity type is formed in a semi-insulating region on the surface of a semi-insulating semiconductor substrate in contact with a gate metal.