JP2638830B2 - Frequency synthesizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit system for preventing a double PLL frequency synthesizer from being erroneously locked due to an image frequency.

2. Description of the Related Art In recent years, a phase-locked loop (Phase-locked loop) has been used to select a transmission / reception channel in various fields of communication and broadcasting, including wireless communication such as satellite communication, automobile telephones, and personal wireless communication. Locked Loop: PL
A frequency synthesizer using a circuit (referred to as L) is indispensable. In order to cope with the increasing demand for radio waves in the future, it is necessary to increase the frequency band allocated to one channel, and to shift to higher frequencies, and to increase the frequency of frequency synthesizers. In addition, higher resolution is required.

Hereinafter, a conventional technique will be described. FIG. 5 is a block diagram of a conventional frequency synthesizer. 1 in the figure is VCO1
(VCO is an abbreviation of Voltage Controlled Oscillator) 2 is an output frequency signal of VCO 1.1, that is, _OUT which is an output frequency signal of this frequency synthesizer.
It is. 3 is a second PLL circuit corresponding to the local oscillator (operation discussed later), the local oscillation frequency signal _LOCAL · 4
Is output. Reference numeral 5 denotes a frequency mixer (hereinafter, referred to as a mixer), which performs frequency mixing of _OUT · 2 and _LOCAL · 4 to obtain a mixed frequency signal _IF =
( _IF = | _OUT - _LOCAL |) 6. 7
In the divider 1, it is producing a _IF · 6 N ₁ by dividing by the divided frequency signal _V1 8. Where N ₁ is varied by the control data from the outside a positive integer. Reference numeral 9 denotes a reference oscillator 1 having a frequency divider therein as necessary. Reference _numeral 10 denotes the output of the reference frequency signal _re1 . Numeral 11 denotes a phase comparator 1, which receives two input signals _V1.8.
re1 · 10 compares the phases of the outputs of the error signal e _r1 · 12. _{Reference numeral} 13 denotes a low-pass filter 1, which forms a closed circuit by lowering the frequency of the error signal _er1 · 12 to obtain a control signal _VT1 · 14 as a DC signal and feeding it back to the VCO1 · 1.
In such a frequency synthesizer, _V1 =
_re1 Since VCO 1 · 1 is controlled to be, _IF = N ₁
× _re1 and _OUT = _LOCAL + N ₁ ×
It becomes _re1 . Thus, the first PLL circuit 15 is formed.

Next, the second PLL circuit 3 will be described. The local oscillation frequency signal _LOCAL · 4 output from VCO2 · 21 is divided by the frequency divider 2
- 22 to N ₂ divided (N ₂ in still positive integer, is varied by the control data from the outside), to give the N ₂ divided frequency signal _V2-23, it phase comparator 2・ Input to one end of 24. At the other end, a reference frequency signal 2 which is an output of a reference oscillator 2.25 (with a frequency divider therein as necessary)
Enter the _re2 · 26, and outputs an error signal 2e _r2 · 27. The low-pass filter 2 · 28 converts the low-pass wave to the control signal 2
And V _T2 · 29 is to form a closed circuit by return to VCO2 · 21. Since it is controlled to again become _re2 = _V2, the _LOCAL = N ₂ × _re2.

_{Accordingly, OUT = LOCAL + N 1 ×} re1 = N 1 × re1 + N 2 × re2 therefore do it by changing the N ₁ or N ₂ from the outside,
_OUT can be varied using _re1 or _re2 as a step. Note that, in general, 2.
25, that is, _re1 · 10 and _re2 · 26 use the same thing. At that time becomes _{OUT = (N 1 + N 2} ) re1.

Such a frequency synthesizer is referred to as a dual PLL frequency synthesizer. The double configuration is taken for the following reason. In the second PLL circuit 3,
Divider 2.22 is a relatively high frequency of VCO 2.21
Since must deal with _LOCAL · 4, of the fixed frequency division at the preceding stage, for example, because from the provided 1/8 Toka 1/64 Toka said prescaler to variable frequency division is common, N ₂ step increases Would. On the other hand, in the first PLL circuit 15, the frequency dividers 1 and 7 handle the low-frequency _IF 6 that has been frequency-converted by the mixer 5, so that the variable frequency division can be directly performed, and therefore N ₁ is normally It can be changed for each step. In other words, the aim set in N _2, by performing the detailed settings in N _1, while received high frequency output can be realized frequency synthesizer capable of varying the frequency in small steps. The second PLL circuit operates as a coarse (COARSE) synthesizer, and the first PLL circuit operates as a fine (FINE) synthesizer.

Here is an example. Step a N ₁ in 8 to 15 1, N ₂ and 28
Step 8 from 8 to ₃₈₄ , _re1 = _re2 = 5 [MHz]
Then, _OUT (min) = 5.times. (288 + 8) = 1480 [MHz] _OUT (max) = 5.times. (384 + 15) = 1995 [MHz].

Problems to be Solved by the Invention However, in such a dual PLL-type frequency synthesizer, there is a problem that lock occurs at an incorrect frequency due to an image frequency depending on the combination.

This will be specifically described with reference to the above-described example. First, the second
It is assumed that N ₂ = 288 for the PLL circuit of FIG. _{Since re2} is also 5 [MHz], _LOCAL = 1440 [MHz]. Next, it is assumed that N ₁ = 8. _re1 is also 5 [MHz]
Therefore, control is performed so that _V1 = 5 [MHz] and _IF = 40 [MHz]. However, there is a case where a frequency signal of a sum of a difference between two input frequency signals _OUT and _LOCAL is output as a property of the mixer. At this time,
There is no _{OUT where LOCAL} = 1440 [MHz] and _IF = 40 [MHz], but the difference is _OUT = 1480 [MHz] and _OUT
= 1400 [MHz]. In this frequency synthesizer, 1480 [MHz] is an image frequency because 1480 [MHz] is a regular frequency. Therefore, if VCO1 becomes 1400 [MHz] for some reason, the lock will be applied and this frequency synthesizer will continue to output the wrong frequency, and the receiving system will select an unusual channel. To be broadcast. For this reason, there may occur for each setting of each N ₂ and N _1. For example, 1395 if N ₁ = 9 in the case of N ₂ = 288 was the [MHz], N ₁ = 10 if 1390 [M
Hz] As such ......, In the case of N ₂ = 296 N ₁ = 8
Then, there is a frequency that locks erroneously for each channel, such as 1440 [MHz], 1435 [MHz] if N ₁ = 9, and so on.

Means for Solving the Problems In the present invention, it is intended to determine whether the output frequency of the voltage controlled oscillator of the first PLL circuit is the originally desired frequency or the image frequency by looking at the control voltage. A first phase-locked oscillator which returns the output of the first voltage-controlled oscillator having a frequency of f _O to the first voltage-controlled oscillator via a mixer, a frequency divider, a phase comparator, and a low-pass filter. A second phase-locked loop having a frequency f _L and including a second voltage-controlled oscillator for supplying a local oscillation frequency signal to the mixer, wherein the f _O is compared to the f _L When f _O > f _L is normal, when the frequency f _O falls below the predetermined frequency width by more than the frequency f _L , the signal from the first voltage controlled oscillator to the phase comparator becomes Block or turn off at least one signal It is configured to lose or significantly attenuate.

Effects By such means, it is possible to provide a dual PLL frequency synthesizer that does not lock erroneously at the image frequency.

Embodiment FIG. 1 is a block diagram of a dual PLL frequency synthesizer according to an embodiment of the present invention. In the figure, 1 is VCO1, 2
Is an output frequency signal ( _OUT ), 3 is a second PLL circuit, 4 is a local oscillation frequency signal ( _LOCAL ), 5 is a mixer, 6 is a mixed frequency signal ( _IF ), 7 is dividers 1 and 8
N ₁ divided frequency signal _(V1), the reference oscillator 1, 10 9 reference frequency signal 1 _(re1, 11 is a phase comparator 1 and 12 error signal 1 (e _r1), 13 is a low-pass filter 1 , 14 are control signals 1 (V _T1 ), 15 is the first PLL circuit, 21 is
VCO2 and 22 are frequency dividers ₂ and 23 are frequency signals divided by N2 (
_V2), 24 is a phase comparator 2, 25 is a reference oscillator 2, 26 is the reference frequency signal 2 _(re2, 27 is an error signal 2 (e _r2), 28
Is a low-pass filter 2; 29 is a control signal 2 (V _T2 ); 31 is a comparator whose input terminal is connected to V _T1 and its input terminal is connected to V _T2, so that the comparator output voltage V _COMP 32 becomes V if V _T1 > V _{T2.
If COMP} = “Low” and V _T1 <V _T2 , V _COMP = “High”.
33 is an OR gate, and the opening and closing of the gate is controlled by V _COMP 32. If V _COMP is “Low”,
The gated frequency signal _G 34 has _G = _V1 , V _COMP
Is “High”, _G is always at “High” level, so _G =
It becomes 0.

The dual PLL frequency synthesizer having the above configuration will be described with a specific example. Now, N ₁ = 8, N ₂
= 288, _re1 = _re2 = 5 [MHz]. The second PLL circuit 3 has _LOCAL = N ₁ × _re1 = 1440
Lock at [MHz]. Figure 2 is a control voltage versus frequency characteristic diagram of a VCO is used in an embodiment of the present invention, thereby controlling the voltage V _T2 of VCO2 · 21 it can be seen that a 3.8 [V]. Now, the control voltage V _T1 of VCO 1.1 is V _T1 > 3.8
[V]. At this time, since V _COMP = “Low”, _G
= _V1 . The first PLL circuit also has _G = _re1
The loop is controlled so that _IF = N ₁ ×
_re1 = 40 [MHz], so _OUT = _LOCAL +
_IF = 1480 [MHz]. V _T1 at this time is 4.0 from Fig. 2.
[V], and the above assumption V _T1 > 3.8 [V] holds, so that the state is stable in this state. Next, tentatively, V _T1 <3.8 [V]
Assume that Then, at this time, since V _COMP = “High”, _G = 0. From the PLL control function, _re > _G
So to operate so as to raise the V _T1. Eventually V _T1 is 3.8
When [V] is exceeded, V _{COMP changes} to “Low” and _G = _V1
become. However, for example, when V _T1 = 3.8 [V], as shown in FIG. 2, _OUT = 1460 [MHz], so that _IF = 1460-1440 = 20.
[MHz], _G = _V1 = 20/8 = 2.5 [MHz]
_re > _G. Furthermore V _T1 therefore Yuki rises, eventually _OUT = 1480 [MHz] That _IF = 40 [MH
z], _G = 5 [MHz] = _re1 , lock is _activated . Since V _T1 at this time is 4.0 [V] from FIG.
_T1 < _VT2 , and the state of V _COMP = "Low" and _G = _V1 is maintained.

As shown in FIG. 2, a relationship of _OUT > _LOCAL holds between the two VCOs at the same control voltage. Otherwise, the comparator V
An offset means such as connecting a diode in series to the _T2 input terminal may be inserted. Then, the control voltage vs. frequency characteristic of the VCO 2 is effectively equivalent to having been translated to the right in FIG. 2, and the same control voltage is used as described above.
_OUT > _LOCAL can be satisfied. Two
Since the required bandwidth of the VCO is almost the same, naturally the same type is used. Therefore, the characteristics are similar and the variation can be relatively small, so that such an operation is easy.

The channel is then switched, for example, N ₁ = 10,
Suppose N ₂ = 320. The second PLL circuit 3 _outputs VCO2 · 21 so that _V2 = _re2 once the lock is _{released.
LOCAL} = 1600 [MHz], V _T2 = 5.5
Lock with [V]. On the other hand, the control voltage V _T1 of VCO 1.1
・ 14 rises following, but if the following is delayed, V _T1 <V _T2
, The same process as described above is followed, and finally
Lock at _OUT = 1650 [MHz] and V _T1 = 6.0 [V].

Even in this case, it can be seen that the frequency converges to the originally desired frequency and stabilizes without erroneously locking at the image frequency both at the time of startup and at the time of channel switching.

FIG. 3 is a block diagram of a part of a frequency synthesizer according to a second embodiment of the present invention, which has the same function as the OR gate in FIG. Reference numeral 35 denotes a comparator, which differs from the case of FIG. 1 in that _VT2 • 29 is input to its input terminal and _VT1 • 14 is input to its input terminal. 32 is a comparator output voltage V _COMP and 36 is an AND gate. Now, V _T1 > V _T2
When, V _COMP = “High”, so _G = _V1 or V
_{When T1} < _VT2 , V _COMP = “Low”, so _G is always “Lo”
w ", _G = 0, and it can be seen that the same function as described with reference to FIG. 1 can be realized.

FIG. 4 is a partial block diagram of a frequency synthesizer according to a third embodiment of the present invention, which also has the same function as the OR gate in FIG. And 37 are analog switches, and 38 is a DC cut capacitor. Now V _T1
V when the> V V _COMP = "Low" because the analog switch 37 when the _T2 is "OFF" and therefore _G = _V1, also V _T1 <V _{T2
Since COMP} = “High”, the analog switch 37 is turned “ON”, and the gated frequency signal 34 is grounded via an extremely small ON resistance, so that it is greatly attenuated to a level at which the next-stage phase comparator cannot be driven. Therefore, it is equal to _G = 0. Therefore, it can be seen that the same function as described with reference to FIG. 1 can be realized.

In the above description, the signal is blocked using a gate such as AND or OR. And an example in which a signal is grounded using an analog switch. Of course, any other gate, such as a NAND / NOR / transfer gate (analog switch) / FET, may be used as long as it has a function of blocking a signal. Also, a mechanical switch such as a reed relay can be used. In addition to the grounding method, it is also possible to use other means such as grounding to a low impedance device such as another power supply, or attenuating the signal itself using a PIN attenuator or the like. The connection point of such a means can be connected to any appropriate point on the path from the VCO to the phase comparator, regardless of the mixed frequency signal and the divided frequency signal. As the control voltage detecting means, a comparator is used as the most versatile method, but it goes without saying that other detecting means may be used.

Further, in this embodiment, a method of detecting the control voltage is used as a means for determining the frequency of the VCO. This is because the control voltage vs. frequency characteristic of the VCO is always monotonically increasing (or monotonically decreasing) and the correlation between the two is uniquely determined, so that it is most suitable as a means for judging the frequency.
Since the two VCOs have almost the same required frequency band, the same type is usually used. Therefore, the control voltage versus frequency characteristic and its temperature characteristic are similar,
If only the difference between the two is detected by the comparator, the fluctuation component due to temperature or the like is canceled. However, of course, another method may be used. In short, any means can be used as long as it can determine the difference and magnitude of the two frequencies.

Effect of the Invention With the simple configuration as described above, in the double PLL frequency synthesizer, the side having the mixer in the loop
Even if the VCO oscillates at the image frequency, it can prevent erroneous locking. Further, since the control voltage of the VCO is configured to be automatically controlled so that its frequency deviates from the image frequency to a frequency originally desired, such as a sweep oscillator for sweeping the control voltage, No special measures need to be taken.

Furthermore, since the image frequency and the originally desired frequency may be close to each other, the frequency ( _IF ) mixed by the mixer can be set to be low, so that the design and selection of the frequency divider become easy and the low frequency can be obtained. Priced ones can be used.

In addition, in the present invention, since there may be a response delay of the control voltage of the first PLL circuit, it is possible to add a large time constant to the low-pass filter and the control voltage signal line.
Therefore, it is possible to improve the high-frequency removal characteristics of the low-pass filter and the stability of the control signal line, and also obtain a ripple effect that the spurious removal performance and the noise resistance performance can be improved.

As described above, an excellent effect can be obtained by adding a simple circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frequency synthesizer according to one embodiment of the present invention, and FIG. 2 is used in one embodiment of the present invention.
FIG. 3 shows a control voltage vs. frequency characteristic of the VCO, and FIG.
FIG. 4 is a block diagram of a part of a frequency synthesizer according to a third embodiment of the present invention, and FIG. 5 is a block diagram of a conventional frequency synthesizer. 1 ... VCO1, 2 ... Output frequency signal ( _OUT ), 3 ...
The second PLL circuit, 4 ...... local oscillation frequency signal _(LOCAL), 5 ...... mixer, 6 ...... mixing frequency signal _(IF), 7 ...... divider 1,8 is ...... N ₁ divided Frequency signal ( _V1 ), 9 ... Reference oscillator 1, 10 ...
Reference frequency signal 1 ( _re1 ), 11 ... phase comparator 1,
12 ...... error signal 1 (e _r1), 13 ...... low pass filter 1, 14 ...... control signal 1 (V _T1), 15 ...... first PLL circuit,
21 VCO2, 22 Frequency divider ₂ , 23 Frequency signal ( _V2 ) divided by N2, 24 Phase comparator 2, 25 Reference oscillator 2, 26 Reference frequency signal ( _re2), 27 ...... error signal 2 (e _r2), 28 ...... lowpass filter 2,29 ...... control signal _{2 (V T2), 31 ·} 35 ...... comparator 32 ...... comparator output voltage (V _COMP), 33 …… OR gate, 34…
... gated frequency signal ( _G ), 36 ... AND gate, 37 ... analog switch, 38 ... capacitor.

Claims (1)

(57) [Claims] An output of a first voltage controlled oscillator having a frequency of f _O is fed back to the first voltage controlled oscillator via a mixer, a frequency divider, a phase comparator, and a low-pass filter. And a second phase-locked loop having a frequency f _L and including a second voltage-controlled oscillator for supplying a local oscillation frequency signal to the mixer, wherein f _O is the f _L When f _O > f _L is normal, when f _O falls below f _L by a predetermined frequency width or more, the signal from the first voltage controlled oscillator to the phase comparator A frequency synthesizer configured to block, eliminate, or significantly attenuate at least one of the signals.