JP2634680B2 - Dot matrix display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot matrix display device, and more particularly to a dot matrix display device that can use a low-voltage segment driver.

[Related Art] Hereinafter, a conventional dot matrix liquid crystal display device (LCD) will be described in different sections.

Conventional Addressing Mode In a dot matrix LCD, the row side is driven by a common (common) driver, and the column side is driven by a segment (individual) driver. In other words, a plurality of pixels arranged in one direction provided with one set of display data form a row. The direction of the row may be the x direction or the y direction, but will be described below as the x direction (horizontal direction). FIGS. 2A and 2B show signals supplied from the common driver and the segment driver to the matrix in the conventional addressing mode.

FIG. 2C shows the combined effective voltage received by the pixels of the LCD at the intersections of the matrix.

Common driver, as shown in FIG. 2 (A), the potential V ₁ of the 4-level to the matrix in each row, V _2, V _5, and supplies a voltage waveform signal formed by using a -VEE. Maximum voltage difference
V ₁ + VEE is about 25~40V position.

Segment driver to a column of the matrix, as shown in FIG. 2 (B), 4-level potential _{V 1, V 3, V 4} , -V
Provides a signal formed using EE. The voltage difference in each field, for example, V ₁ -V ₃ is about 3V. The cross hatched area indicates that any voltage in that area may be used. The voltage at which the field changes varies, for example, by about 25-40V.

Between line of the first field V _2, voltage -VEE, the column
The voltages V ₁ and V ₃ are applied, and the row is
The voltages of V ₁ and V ₅ are applied to the columns, and the voltages of V ₄ and −VEE are applied to the columns.

The composite signal VPIXEL received by the pixel has a peak amplitude during the selection time τR. This peak amplitude is (VSCAN + εVDATA) in the first field and − (VSCAN + εVDATA) in the second field. Where ε is a coefficient that is 1 when the pixel is on and −1 when the pixel is off. The corresponding on-state peak amplitude (VSCAN + εVDATA) equals the maximum voltage difference of the power supply.

_{VSCAN + εVDATA = V 1 - (} VEE) + = V 1 + VEE composite signal pixel receives a non-selection frame τR is VDATA or -Vdata, an absolute value constant.

The absolute value VDATA of the amplitude other than the selection time is V ₁ −V ₂ , V ₂ −
_{V 3, V 4 -V 5,} V 5 - (- VEE) equal.

The dot matrix display device is driven by the six potentials described above.

Driver conditions Both the common driver and the segment driver must supply signals with high peak amplitude. That is, the peak amplitude of the common driver is V ₁ (−VEE), and the peak amplitude of the segment driver is also V ₁ (−VEE). Therefore, each common driver and each segment driver should have the maximum operating voltage of the above all V ₁ (-VEE). For a highly multiplexed dot matrix, V ₁ (−VEE) is on the order of 25V to 40V.

Both the common driver and the segment driver generate four potentials. Each output stage uses one switch for each domain level and includes a total of four high voltage, high current switches.

Power requirements The power supply is simple and the six levels to be supplied are V ₁ (typically + 5V) to -VEE (typically 20 to 35 volts)
Is fixed within an appropriate range.

However, the power supply is _{V 1, V 2, V 3} , V 4, V 5, high peak current at each potential of -VEE (typically 10 inches display in
1A) and the stabilization for each potential must be less than 1%.

The cost of the driver is an important part of the total cost of the display.

Since both segment drivers and common drivers require high operating voltages, it is not easy to use low-cost conventional CMOS circuits for dot-matrix LCDs.

In the case of a color display, the number of drivers is tripled on the segment side. Therefore, especially in the case of a color dot matrix, the conventional circuit becomes expensive.

An object of the present invention is to provide a dot matrix display device with low manufacturing cost.

[Means for Solving the Problems] A normal low voltage (about ± 3 V, etc.)
Use CMOS driver.

In order to make the segment driver or the like a low-voltage circuit and the common driver a high-voltage circuit, they are logically coupled by optical coupling means and are separated from each other in terms of DC.

[Operation] The following configuration reduces the cost of the circuit.

The cost is reduced by using ordinary CMOS for the segment side.

In addition, some performance is improved. For example, low on-resistance RON reduces crosstalk. The high cutoff frequency allows serial access of data to the driver line memory.

The number of output transistors in both the common driver and the segment driver can be reduced by half. For example, the number of transistors required to generate a one-way output voltage is reduced from four to two.

By reducing the number of output transistors by half, the chip size can be significantly reduced. Not only can the cost be reduced, but mounting using TAB or COG can be facilitated.

Additionally, according to the present invention, some specifications of the power supply
More easily satisfied. Typically, only a low voltage level between + 5V and -5V must supply a fairly large current and be precisely controlled, while a high voltage level is a low voltage and requires a coarse stability factor.

Embodiment FIG. 1 shows a schematic diagram of a circuit according to the general concept of the present invention.

The rows of the dot matrix type liquid crystal display device 1 are driven by command drivers 2a and 2b, and the columns thereof are driven by segment drivers 3a and 3b. Common driver
2a and 2b receive a voltage signal from the level converter 5 and a control signal from the LCD controller 4 via the optical coupling stage 6. The optical coupling stage 6 separates the LCD controller 4 from the common drivers 2a and 2b in a direct current manner and theoretically couples them.
The level converter 5 is connected via a bridge and a buffer stage 8 to a conventional six-level voltage source 11. The bridge and buffer stage 8 are from the 6-level voltage source 11 to + VSCAN, ground -VSC
The three potentials of AN are input, and five potentials of VSCAN, VSCAN-VLOGIC, ground, -VLOGIC, and VSCAN are output. The control signals from the LCD controller 4 are segment drivers 3a, 3b,
It is also supplied to the level converter 5.

LCD controller 4 as segment driver 3a, 3b
Is a low-voltage circuit, which can be configured using an inexpensive low-voltage semiconductor circuit. The supply voltage to these circuits is VDATA,-
There are four levels: VDATA, -VLOGIC, and ground. All of these levels fall between + 5V and -5V.

Only the common drivers 2a and 2b operate at a high voltage. As described later, the potential of the power supply changes in accordance with the phase shift timing. As the power supply voltage, the common driver is F
It receives three signals called "1", F0 LOGIC, and F "0". The voltage difference between these three signals is constant, but mainly
The signal is periodically and entirely converted by a level conversion stage constituted by a high voltage gate having a VMOS or DMOS structure.

Supplied by LCD controller and the voltage is -VLOGIC
Or some logic signals to change from -VLOGIC (data input DATA IN, common clock CLOCK, phase shift PHASE
SHIFT, enable ENABLU) are all signals DATA for changing the potential from F "1" to F0 LOGIC by the optical coupling means 6.
The level is converted to IN * CLOCK * PHASE SHIFT * ENABLE *. An optical coupling stage 6 is used to perform level conversion of these theoretical signals sent to the common drivers 2a and 2b without noise.

With the configuration described above, the voltages to be handled by the segment drivers 3a and 3b are only two low voltage levels of VDATA-VDATA, and the LCD controller 4 can also operate at a low voltage.

The common drivers 2a and 2b have a "floating" power supply and receive the level-converted logic signal at the same time. By the way, the common drivers 2a and 2b have only two voltage levels to be handled, F "1" and F "0".

Although the outline of the present invention has been described above, the present invention will be described below in more detail along each component.

1. Power supply The power supply corresponds to the combination of the 6-level power supply 11, the bridge and the buffer stage 8, and the level converter 5 in the configuration of FIG.
And supply current to the LCD controller.

 The structure is shown in FIG.

First stage: A power supply 11 similar to the conventional one has six constant potentials VSCAN, VDATA,
Supply ground (VG), -VDATA, -VLOGIC, -VSCAN.

The four low voltages VDATA, VG-VDATA, and -VLOGIC are taken out as low voltage levels, and the segment driver 3a,
3b and supplied directly to the LCD controller 4.

Second stage: A bridge composed of a conventional resistive bridge and an associated buffer and a buffer stage 8 have two intermediate levels V
Supply SCAN-VLOGIC, -VLOGIC. Only the logic of the common driver uses these intermediate voltages. Therefore, these levels do not need to be adjusted precisely, and the required current is very low (several mA).

Third stage: A set of level conversion elements (VMOS or
The DMOS switch 13 is connected to the P
(Activated periodically by the HASE SHIFT signal)
Two signals.

F "1" = VSCAN or VG (depending on the PHASES SHIFT signal) F0 LOGIC = VSCAN-VLOGIC or -VLOGIC F "0" = VG or -VSCAN These voltage waveforms are shown in FIG. 3 (B).

The potential difference between F "1", F0 LOGIC, and F "0" is determined by a set of capacitors CF (for a 10 inch LCD, typically CF = 10n
F) keeps it constant during the level transition.

Common Driver FIGS. 4A, 4B and 4C show a common driver circuit.

As an example, a driver for driving six rows is shown. 4 (A) shows a schematic configuration, FIG. 4 (B) shows a control signal, and FIG. 4 (C) shows an enlargement of a broken line portion in FIG. 4 (B).

 The common driver has three stages.

The first stage is a normal shift register operated by two signal data inputs DATA IN * and a common clock COMMON CLCOK * (the waveform before the level conversion is shown in FIG. 5).

The second stage is an inversion stage controlled by a phase shift signal PHASE SHIFT * (FIG. 5 shows a waveform before level conversion). This stage is the six signal Gate used in the third stage
rowi * (i is 1 to 6).

The third stage is composed of six output blocks as shown in FIG. 4 (C).

When the enable signal ENABLE * (the waveform before the level conversion is shown in FIG. 5) is 1, the transistor T1 connected to F “1” and the transistor T0 connected to F “0”
Are driven by the GATEROW signal and its inverted signal, respectively, to generate a common driver output of F "1" or F "0". When the enable signal ENABLE * is 0, both the transistors 1 and T0 are open. Therefore,
When ENABLE * is 0, the common driver has high impedance.

FIG. 5 shows the general relationship of all the signals used above.

The PHASE SHIFT (or PHASE SHIFT *) signal is shown at the top. During the first field, PHASE SHIFT is "1", and during the second field, PHASE SHIFT is "0".

In the next stage, DATA IN indicates a DATA IN *) signal. DATA IN is a single pulse at the beginning of each field. This initializes the shift register with a single one as the first data.

 The third stage shows the ENABLE (or ENABLE *) signal.

ENABLE is a state of “0” from the (N + 1) th pulse of the COMMON CLOCK to the first pulse of the next COMMON CLOCK (corresponding to high impedance of all common drivers).

The fourth row shows a COMMON CLOCK (or COMMON CLOCK *) signal. COMMON CLOCK pushes the signal in the shift register. Assuming that the number of rows to be scanned is N, COMMON CLOCK is
N + 1 pulses. After the final pulse, a single one is pushed out and all data in the shift register becomes zero.

5 shows common driver outputs for two rows (for example, a first row and a second row) that are continuous in the fifth and sixth rows. In the first field, F is "1" during the selection time, and F is
It becomes “0”. In the second field, F becomes "0" at the selection time and F "1" at the non-selection time.

The lower table shows “level of shift register” and shows each state of the Gate Row signal sent to the output stage. All Gart
When the row signals are in the same state (all 0s or all 1s), ENABL
E is "0". Therefore, the phase shift signal PHASE SHIFT switches from 0 to 1 or from 1 to 0, and the common power supply F
When the batch change of “1”, F0 LOGIC, F “0” signal is started,
All common drivers have other impedance. Therefore, the common driver is protected from polarity reversal. That is, we can see the important fact that no current is supplied when level translation is performed.

The effective voltage applied to the cells remains the same, level translation requires no current and there is no risk of driver polarity reversal.

Segment driver FIG. 6 shows the configuration of a segment driver. The segment drivers are all of the blackout voltage. First stage: shift register 15 (data is serial) Second stage: line memory 16 (parallel access) Third stage: polarity inversion stage 17 controlled by phase shift signal PHASEH SHIFT fourth Stage: Including output driver 18.

The block of output driver 18 for each segment is
It is made by a pair of CMOS driven directly by the signal GATE SEGMENT provided by the stage.

Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[Effect of the Invention] As described above, according to the present invention, the manufacturing cost of the dot matrix display device can be reduced.

Since the high voltage side and the low voltage side are electrically separated by the optical coupling stage and are logically coupled, the low voltage side circuit does not require a high withstand voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an LCD driven by a power supply whose potential changes according to timing. FIGS. 2A, 2B, and 2C are addressing modes of a conventional dot matrix LCD using a 6-level power supply. FIGS. 3A and 3B are a waveform diagram and a circuit diagram showing a power source whose potential changes according to the timing of the dot matrix LCD. FIGS. 4A, 4B and 4C are FIG. 5 is a circuit diagram illustrating a common driver, FIG. 5 is a waveform diagram illustrating the operation of the common driver, and FIG. 6 is a circuit diagram illustrating a segment driver.

Claims (2)

(57) [Claims] 1. A voltage F "1" is applied to each row during its selection time, a voltage F "0" is applied to each row during its non-selection time, and all non-selections are always connected to ground. And a common driver for driving a row line of a dot matrix display, and three kinds of signals of the voltage F "1", the voltage F "0", and a voltage F0 LOGIC used for logic operation of the common driver are supplied to the common driver. Power supply
The levels of the three types of signals are the voltage F “1” and the voltage F
The period driven by the phase shift signal PHASE SHIFT that changes at the end of each field while keeping the voltage difference between F0 LOGIC and the potential difference between the voltage F “1” and the voltage F “0” constant. And the power supply in which the voltage F "0" and the voltage F "1" are alternately grounded, and the rows of the dot matrix display are so arranged that all unselected rows are always connected to ground. A set of common drivers for changing between the level of the voltage F “1” and the level of the voltage F “0”; and the voltage F for controlling the logic operation of the common driver.
A conversion stage using an optical coupler for supplying a logic signal that changes between a level of “1” and the level of the voltage F0 LOGIC to a common driver. 2. The power supply according to claim 1, wherein the voltage VSCAN is a voltage F "1" when the voltage F "0" is a ground voltage, and a voltage F "0" when the voltage F "1" is a ground voltage. The voltage -VSCAN, the voltage -VLOGIC corresponding to the potential difference between the voltage F0 LOGIC and the voltage F "1", and the voltage VSCAN
VSCA corresponding to the potential difference between the
N-VLOGIC, a five-level power supply of ground voltage, and three gates driven by a phase shift signal PHASE SHIFT, wherein voltage F “1” = VSCAN or ground, voltage F0 LOGIC = VSC
AN-VLOGIC or -VLOGIC, and three gates for supplying a signal of voltage F "0" = ground or -VSCAN, wherein the common driver comprises a voltage F "1", a voltage F0L
2. The dot matrix display device according to claim 1, further comprising an enable function for setting all output drivers to a high impedance state while the signal level of the OGIC and the voltage F "0" changes.