JP2629558B2 - Test pattern generation system for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the generation of a test pattern for an integrated circuit, and more particularly to a test pattern generation system for generating a test pattern having a high failure rate.

[0002]

2. Description of the Related Art Conventionally, a test pattern of a test program has been manually created by a designer.
Automatic test pattern generation using data (ATPG)
It is created by The ATPG includes a D algorithm, a PODEM algorithm, a FAN algorithm, and the like, which generate a test pattern from a circuit when creating a test program in an integrated circuit design stage. The ATPG includes a multi-stage combination circuit having many reconvergent branches and a switch. For a sequential circuit having no campus, it takes a very long time to generate a test pattern, and in many cases, a test pattern having a sufficient failure detection rate cannot be generated.

On the other hand, in order to easily create a test pattern having a high failure detection rate, there is a testability design technique, and an ad hoc technique, a scan design technique, a cross-check technique, or the like is used. Each of these methods is a method in which the potential state inside the integrated circuit is connected to an external terminal in a circuit by adding an additional circuit so that the state can be observed. FIG. 5 shows an integrated circuit to which the cross-check method is applied as an example of such a conventional technique. As shown in FIG. 5, a switch transistor 502 is added to the output of each gate 501 in the integrated circuit, and a probe line 505 and a sense line 506 connected to a gate electrode 503 and a drain electrode 504 of the transistor 502 are read out to the output. Register 50 for compressing the output value of the gate
7 and their control circuits 508.

[0004]

One of the conventional test pattern generation methods, automatic test pattern generation (AT
PG) is performed using CAD data, so if the circuit becomes complicated, it takes a very long time to generate a test pattern,
It has a drawback that a test pattern with a high failure detection rate cannot often be generated. In particular, in recent years, in an integrated circuit that is increasing in scale, it is said that the time required to create a test pattern with a high fault detection rate is proportional to the square of the circuit scale. It's even getting harder.

Further, in an integrated circuit designed by the design method for testability, an additional circuit is basically provided to improve the observability and controllability of the potential state of the internal node from the external terminal. Has the drawback that the shape and size of the element become large, and further has the drawback that the characteristics change due to the additional circuit occurs.

[0006]

According to the present invention, there is provided an integrated circuit test pattern generation system, comprising: an electron beam tester capable of observing a potential state of a wiring inside an integrated circuit as a contrast image or a waveform; a node of the integrated circuit; It is characterized by comprising a storage device for storing states in a time series, a test pattern generation device for generating a test vector from CAD information, and a control device for controlling these devices.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an integrated circuit test pattern generation system according to one embodiment of the present invention. An electron beam tester 101 capable of observing a potential state of wiring inside an integrated circuit, a node of an integrated circuit 105 and a potential state thereof It comprises a storage device 102 for storing as time-series information, a test pattern generating device 103 for generating a test vector from CAD information, and a control device 104 for controlling these devices and processing data. FIG. 2 is a flow chart of the test vector generation of the integrated circuit test pattern generation system of the present invention shown in FIG.

The potential states of all the nodes of the integrated circuit driven by the LSI tester are the ones in the test pattern.
The electron beam tester sequentially acquires the data for all the cycles and stores the acquired data in the storage device. Next, information on the potential state of each node is taken out from the storage device to the control device, the presence or absence of a change in the state is identified, and a node whose potential state has never changed during one cycle of the test pattern is extracted.
For each node, the circuit from the node to the input terminal and the circuit from the output terminal to the CA
Extracted from the D data, by the test pattern generator,
An input test vector for changing the potential state of the node and an observable output vector generated by the change in the potential state of the node are generated.

Next, input / output terminals irrelevant to this node are used as final test vector values, and test vectors corresponding to all input / output terminals are created by adding these test vectors. A new test pattern can be created by applying the test pattern generation flow shown in FIG. 2 to all nodes having no potential state change.

Since the test pattern created by the present invention includes a test vector that changes a node having no potential state change by the first test pattern,
The potential state of all internal nodes of the integrated circuit is at least 1
The degree is changed, resulting in a test pattern with a high failure detection rate.

FIG. 3 is a block diagram showing another embodiment of the present invention, in which an electron beam tester 301 and a storage device 30 are provided.
2, test pattern generation device 303, control device 304,
1 shows an integrated circuit test pattern generation system including an arithmetic unit 306 for identifying a change in a potential state.
The method of extracting a node having no change in the potential state of the internal node of the integrated circuit by the electron beam tester 301 is the same as that of the integrated circuit test pattern generation system shown in FIG. Determining the presence or absence by the arithmetic unit 306 has the effects of reducing the memory capacity of the storage device 302 and shortening the processing time.

FIG. 4 is a block diagram showing another embodiment of the present invention, in which an electron beam tester 401 and a storage device 40 are provided.
2, test pattern generation device 403, control device 404,
It comprises an integrated circuit 405, an arithmetic unit 406, and a drive unit 407. 1 illustrates an integrated circuit test pattern generation system including a driving device 407 that operates an integrated circuit 405. Since the driving device 407 is included in the system, it is possible to perform the extraction of the node having no potential change in the integrated circuit and the verification of the created test vector in parallel, thereby reducing the time required to create a test pattern with a high fault detection rate. It has the effect of shortening.

[0013]

As described above, the present invention has an electron beam tester and a test pattern generator capable of observing the potential state of the wiring inside the integrated circuit in the system. In the test pattern, a potential state of a node inside the integrated circuit which cannot be observed can be observed, and a node having no change in the potential state can be extracted. In addition, because the system has a test pattern generator,
An input test vector for changing the potential state of a node using CAD data and an observable output test vector generated by a change in the potential state of the node can be easily generated in a short time. . In particular, as shown in the graph of FIG. 6 showing the relationship between the test pattern design man-hours and the failure detection rate according to the conventional method, making the failure detection rate 80% or more in the conventional method requires twice or more the test pattern design time. However, since the test is performed in a short time and a test pattern capable of detecting a fault other than the functional operation is created, a test pattern having a high fault detection rate is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a flowchart illustrating a procedure for generating a test vector in the integrated circuit test pattern generation system according to the present invention.

FIG. 3 is a block diagram of another embodiment of the present invention.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 5 is a diagram showing a structure of an integrated circuit designed by a cross-check method, which is one of conventional test-easy design techniques.

FIG. 6 is a graph showing a relationship between a test pattern design man-hour and a failure detection rate according to a conventional method.

[Explanation of symbols]

 101, 301, 401 Electron beam tester 102, 302, 402 Storage device 103, 303, 403 Test pattern generator 104, 304, 404 Controller 105, 305, 405 Integrated circuit 306, 406 Arithmetic device 407 Driving device 501 Gate 502 Switching Transistor 503 gate electrode 504 drain electrode 505 probe line 506 sense line 507 register 508 control circuit

 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-63-124438 (JP, A) JP-A-4-142475 (JP, A) JP-A-4-344571 (JP, A)

Claims (4)

(57) [Claims] 1. An electron beam tester capable of observing a potential state of a wiring inside an integrated circuit as a contrast image or a waveform, a storage device for storing the nodes of the integrated circuit and their potential states in time series, and a test vector based on CAD information. generating a test pattern generator is composed of a control unit for controlling these devices, it is measured by an electron beam tester
All tests of all nodes of the integrated circuit stored in the storage device
Retrieve the potential state of the pattern and call each node
Control of potential state change for all test patterns
By using the calculation function of the control device,
An integrated circuit test pattern generation system having a function of extracting a node having no state change and generating a test pattern for changing a potential state of the node. 2. A collection operated by an electron beam tester.
Measure the node of the integrated circuit and its potential state,
By successively comparing each pattern with the previous pattern,
2. The integrated circuit test pattern generation system according to claim 1, further comprising a function of identifying and storing a change in the potential state of the circuit. 3. The integrated circuit test pattern generation system according to claim 1, further comprising a driving device for logically driving the integrated circuit. 4. The integrated circuit test pattern generation system according to claim 3, having a function of verifying the created test pattern.