JP2627367B2 - Y / C separation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Y / C separation circuit, and more particularly to a Y / C separation circuit for separating a composite video signal into a luminance signal and a chrominance signal using, for example, a 1H (line) glass delay line. .

[0002]

2. Description of the Related Art FIG. 7 shows a general Y / C comb of this kind.
1 shows a separation circuit 1. This Y / C separation circuit 1 separates a luminance signal and a chrominance signal by utilizing the inversion of the phase of a chrominance signal for each line. For that purpose, the delay time of the glass delay line 2 must be exactly 1H. However, the glass delay line 2 is generally provided with a pair of ultrasonic transducers at opposite corners of a rectangular glass substrate, and delays an electric signal input to one of the ultrasonic transducers by 1H depending on the surface shape of the glass substrate therebetween. The signal is extracted from the other ultrasonic transducer as a signal, and the delay time varies due to the variation in processing of the glass substrate and the like. Therefore, as shown in FIG. 7, the glass delay line 2 is terminated using the variable coil L,
By adjusting the inductance value, the variation in the delay time of the glass delay line 2 is corrected.

[0003]

However, in the conventional Y / C separation circuit 1 shown in FIG. 7, since the variable coil L is manually adjusted, not only takes a long time for adjustment, but also requires a long time for each product. Had variations in performance. Therefore, a main object of the present invention is to provide a Y / C separation circuit that can easily and accurately correct a delay time of a glass delay line.

[0004]

SUMMARY OF THE INVENTION The present invention relates to an input signal
Output input terminal for receiving a composite video signal, a glass delay line for receiving an input signal from a and the input terminal of the delay time of one line from the input signal and the glass delay line as
An adder circuit for obtaining a luminance signal based on the input signal,
And a color signal based on the output signal from the glass delay line.
Subtraction circuit, a semiconductor variable inductance circuit that terminates at least one of the input side and the output side of the glass delay line,
And a control unit for controlling an inductance value of the semiconductor variable inductance circuit based on the input signal and the output signal.

[0005]

When the composite video signal (burst signal) input to the input terminal and the signal (burst signal) output from the glass delay line are input to the control means, when the phase difference between the two signals is exactly 180 ° Is given as a reference, a control signal corresponding to a shift amount of the phase difference from the reference is supplied from the control means to the semiconductor variable inductance circuit. In the semiconductor variable inductance circuit, the inductance value is changed in accordance with the control signal, so that the terminal inductance of the glass delay line is automatically controlled, and the burst signal of the composite video signal from the input terminal and output from the glass delay line. The phase difference with the signal (burst signal) is exactly 18
It is adjusted by 0 °. Therefore, the addition circuit and the subtraction circuit
And accurately separate and extract the Y and C signals
Can be

[0006]

According to the present invention, the terminating inductance is automatically adjusted by the semiconductor variable inductance circuit and the control means, so that the delay time of the glass delay line can be accurately corrected without manual operation, and therefore, the manufacturing cost is reduced. Is reduced, and performance does not vary from product to product.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the accompanying drawings.

[0008]

Referring to FIG. 1, a Y / C separation circuit 10 of this embodiment is configured as an IC (integrated circuit) 12,
It includes an addition circuit 14 and a subtraction circuit 16 built in C12. The IC 12 has an IC terminal 18 serving as an input terminal for a composite video signal, and includes an addition circuit 14 and a subtraction circuit 1.
6, a composite video signal from the IC terminal 18 is input. The composite video signal from the IC terminal 18 is supplied to the input terminal 24 of the glass delay line 26 via the amplifier 20, the IC terminal 22, and the resistor R1.
The amplifier 20 is for compensating for the insertion loss in the glass delay line 26, and need not be provided.
The input terminal 28 and the output terminal 30 of the glass delay line 26 are grounded, and a resistor R2 is interposed between the output terminals 30 and 32. The glass delay line 26 is configured as described above, has a delay time of 1H, and
And outputs as output Film image signal by H delay. The output Film image signal is input from the IC terminal 34 to the addition circuit 14 and subtraction circuit 16 through an amplifier 36. This amplifier 36
Is an amplifier for amplitude adjustment. The adder circuit 14 calculates “previous line + current line” and outputs the remaining luminance signal, and the subtraction circuit 16 calculates “previous line−current line” and outputs the remaining color signal.

Gyrators 40 and 42 as semiconductor variable inductance circuits are connected to input terminal 24 and output terminal 32 of glass delay line 26 via IC terminals 38 and 34, respectively. The gyrators 40 and 42 function as input and output terminal inductances of the glass delay line 26, respectively, and their inductance values are low-pass filters (hereinafter, referred to as “LPFs”) 4.
4 is controlled by the output. However, glass delay line 2
It is not necessary to terminate both the input and the output of No. 6; Then, the LPF 44, the error signal corresponding to the phase difference between the burst signal included in the output movies image signal from the burst signal and the glass delay line 26 included in the composite video signal from the IC terminal 18 is input. In this embodiment, the output movies image signal from the glass delay line 26 is 90 ° phase advance with 90 ° phase shift circuit 46, also I
The composite video signal from the C terminal 18 is directly supplied to a multiplier 48 forming a phase comparison. Therefore, the multiplier 48 supplies an error signal to the LPF 44 in accordance with the amount of deviation of the phase difference between the two signals from 90 ° with reference to the time when the two signals have a phase difference of 90 °. Therefore, L
The PF 44 outputs a control voltage corresponding to the phase difference shift amount, and outputs the control voltage to the gyrators 40 and 4.
2 given.

The above-mentioned 90 ° phase shift circuit 46 is disclosed in Japanese Patent Application No. Hei 3-8585 filed on Jan. 28, 1991 filed by the present applicant, as shown in FIG. Is available. In the 90 ° phase shift circuit 46 of FIG. 2, the output eo ′ from the terminal 50 is

[0011]

(Equation 1)

Thus, an output eo 'having a 90 ° phase shift is obtained regardless of the values of the resistor R0, the capacitor C0 and the signal angular frequency ω. Further, a phase comparator, ie, a multiplier 4
8 is configured as shown in FIG. 3 and operates as shown in FIG. That is, signals as shown in FIG. 4A are input from the IC terminal 18 to the input terminals 52 and 54, and signals from the glass delay line 26 are input to the input terminals 56 and 58 from the glass delay line 26.
A signal as shown in FIG.

When both signals are in phase, the transistors Tr1 and Tr5 are turned on in a positive cycle, and the transistors Tr3 and Tr6 are turned on in a negative cycle. Therefore, the voltage at the output A pulsates every half cycle in the negative direction as shown in FIG.
The voltage becomes constant as shown in FIG. Therefore, the current I1 (that is, I4) flowing through the transistor A is as shown in FIG.
As shown in FIG. 4E, the current I2 pulsates in the positive direction, and the current I2 flowing through the transistor B becomes constant as shown in FIG. Therefore, the current I3 flowing through the LPF 44, which is I2-I4, pulsates in the negative direction as shown in FIG.
This current I3 is smoothed (integrated) by the LPF 44,
Therefore, as shown in FIG. 4H, the output of the LPF 44 outputs a negative control voltage when both signals are in phase.

When both signals have opposite phases, the transistors Tr4 and Tr6 turn on when the signal from the IC terminal 18 has a positive cycle, and the transistors Tr2 and Tr5 turn on when the signal from the IC terminal 18 has a negative cycle. Therefore,
The voltage at the output A becomes constant as shown in FIG. 4C, and the voltage at the output B pulsates in the negative direction every half cycle as shown in FIG. 4D. Therefore, the current I1 flowing through the transistor A (that is, I4) becomes a constant current as shown in FIG. 4E, and the current I2 flowing through the transistor B pulsates in the positive direction as shown in FIG. Therefore, the current I3 flowing through the LPF 44 that is I2-I4
Pulsates in the positive direction as shown in FIG. This current I3 is smoothed (integrated) by the LPF 44, so that the output of the LPF 44 outputs a positive control voltage when both signals are out of phase as shown in FIG.

When both signals have a phase difference of 90 °, transistors Tr1 and Tr5 are turned on in the first half of the first half cycle of the signal from IC terminal 18 in FIG. 4A, and transistors Tr4 and Tr6 are turned on in the second half. . Also, I
In the first half of the second half cycle of the signal from the C terminal 18, the transistors Tr3 and Tr6 are turned on, and in the second half, the transistors Tr2 and Tr5 are turned on. Therefore, the voltage at the output A becomes a negative direction voltage only in the first half of each half cycle as shown in FIG.
As shown in (D), it appears as a negative voltage only in the latter half of each half cycle. Therefore, the current I1 flowing through the transistor A (that is, I4) flows in the positive direction only in the first half of each half cycle as shown in FIG. 4E, and the current I2 flowing through the transistor B as shown in FIG. It flows in the positive direction only in the second half of each half cycle. Therefore, LP which is I2-I4
The current I3 flowing through the FF 44 has a substantially sinusoidal waveform as shown in FIG. 4 (G).
As shown in (H), when both signals have a 90 ° phase difference, a control voltage of almost 0 is output.

As described above, when the phase difference between the two signals input to the phase comparator, that is, the multiplier 48 is 90 °, the LPF 44 outputs a control voltage of almost 0.
If the phase difference between the two signals deviates from 90 °,
The positive or negative control voltage corresponding to the amount of the shift is
Output from The inductance values of the gyrators 40 and 42 are adjusted according to the control voltage from the LPF 44.

One example of gyrators 40 and 42 that can be used in the embodiment of FIG. 1 is shown in FIG. Signal V _c generated between AC ground and capacitor C in FIG. 5,

[0018]

(Equation 2)

## EQU1 ## The voltage V2 generated between the bases of the transistors Q3 and Q4 forming the second differential pair is

[0020]

(Equation 3)

Is represented by Therefore, from the above equation, the first
By adjusting the differential resistance re0 of the transistors Q1 and Q2 or the differential resistance re1 of the transistors Q3 and Q4 constituting the differential pair by the control voltage from the low-pass filter 44, the gyrators 40 and 4
It can be seen that the inductance value of No. 2 can be controlled. That is, if the currents I6 and / or I7 of the variable constant current source in FIG. 5 are controlled by the control voltage from the LPF 44, the differential resistances re0 and / or re1 change,
The equivalent inductance values of the gyrators 40 and 42 are changed.

FIG. 6 shows an equivalent circuit diagram of the glass delay line 26, and gyrators 40 and 42 are respectively shown in FIG.
Correspond to the terminal inductances L1 and L2 shown in FIG.
Therefore, if the inductance values of the gyrators 40 and 42, that is, the terminal inductances L1 and L2 are adjusted, the inductance L3 and the capacitances C1 and C2 are adjusted.
2, the tuning frequency of the tuning circuit formed by the inductance L4 and the capacitors C3 and C4 changes, and the group delay characteristic of 3.58 MHz also changes. Therefore, the delay time of the signal in the glass delay line 26 changes. The resistors R1 and R2 are matching resistors with R7 and R8, respectively.

In the above-described embodiment, the two input signals are supplied to the multiplier 48 by the 90.degree.
° Detects whether there is a phase difference, but 90
Instead of using the phase shift circuit 46, the multiplier 48 may detect how much the two input signals are shifted from each other based on the 180 ° phase difference. Also, the gyrator 40
And the control voltage for controlling the control signals 42 and 42 is supplied from the LPF 44 as a voltage corresponding to the error signal from the multiplier 48. However, the gyrators 40 and 42 may be controlled based on whether or not the amplitude difference between the input burst signal and the output burst signal of the glass delay line 26 becomes zero.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a 90 ° phase shift circuit that can be used in the embodiment of FIG.

FIG. 3 is a circuit diagram showing an example of a phase comparator, that is, a multiplier that can be used in the embodiment of FIG. 1;

FIG. 4 is a waveform chart showing an operation of the multiplier of FIG.

FIG. 5 is a circuit diagram showing an example of a gyrator used in the embodiment of FIG.

FIG. 6 is an equivalent circuit diagram showing the embodiment of FIG.

FIG. 7 is a block diagram showing a conventional technique.

[Explanation of symbols]

 Reference Signs List 10 Y / C separation circuit 14 Adder 16 Subtractor 18, 22, 34, 38 IC terminal 26 Glass delay line 40, 42 Gyrator 44 LPF 46 90-degree phase shift circuit 48 Multiplier

Claims (1)

(57) [Claims] 1. A input terminal for receiving a composite video signal as an input signal, 1 has a delay time of the line and the glass delay line for receiving an input signal from the input terminal, an output from said input signal and said glass delay line At the signal
An addition circuit that obtains a luminance signal based on the input signal and the output signal from the glass delay line.
A subtraction circuit that obtains a color signal based on the input signal; a semiconductor variable inductance circuit that terminates at least one of an input side and an output side of the glass delay line; and an inductance value of the semiconductor variable inductance circuit based on the input signal and the output signal. A Y / C separation circuit, comprising: a control unit for controlling the Y / C.