JP2626555B2 - Punctured coding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a punctured coding circuit used for a Viterbi decoder used as an error correction decoder for a satellite communication device, and more particularly, to a coding rate 3
The present invention relates to a punctured coding circuit in the case of / 4.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional punctured coding circuit. Punctured encoding circuit, convolution and P-channel data D _pc after convolutional coding with coding rate of 1/2 clock CK _1/2 and a coding rate of 3/4 clock CK _3/4 as an input signal Q channel data D _qc after encoding
And receive. The punctured coding circuit has a coding rate of 1 /
2 clock CK _1/2 and coding rate 3/4 clock CK
_{Using 3/4} , P channel data D _pc after convolutional coding and Q channel data D after convolutional coding
punctured encoding of _qc, and outputs punctured P-channel data D _ppc and punctured Q-channel data D _qpc as output signals.

The illustrated punctured encoding circuit comprises a 12-stage shift register 61 for P-channel serial / parallel conversion and a 1-stage shift register 61 for Q-channel serial / parallel conversion.
A two-stage shift register 62, a clock frequency dividing counter 63 for a coding rate of 3/4, an address decoder 64, and a P-channel parallel-serial conversion shift register 66
And a Q-channel parallel-serial conversion shift register 67.

The P-channel serial / parallel conversion 12-stage shift register 61 converts the convolutionally encoded P-channel data D _pc into a serial / parallel signal in response to a coding rate 1/2 clock CK _1/2. conversion, and outputs the 8-bit P-channel data D _pp removal of the data to be punctured among the 12-bit parallel output. Similarly, the Q-channel serial-to-parallel conversion 12-stage shift register 62 converts the Q-channel data D _pc after the convolutional coding into a serial / parallel signal in response to the coding rate 1/2 clock CK _1/2. It converts the data and outputs 8-bit Q-channel data _{Dqp from} which data to be punctured is removed from the 12-bit parallel output.

A circuit composed of a combination of the clock rate dividing counter 63 for the coding rate 3/4 and the address decoder 64 has a logic high level every 8 bits from the clock rate CK _3/4 for the coding rate 3/4. A pulse load signal LD is generated. The pulse load signal LD is supplied to the P-channel parallel / serial conversion shift register 66 and Q
It is used as a load signal for the parallel / serial conversion shift register 67 for the channel. In addition, coding rate 3
The / 4 clock CK _3/4 is supplied to the P-channel parallel / serial conversion shift register 66 and the Q-channel parallel / serial conversion shift register 67.

[0006] P-channel parallel-to-serial conversion shift register 66, the pulse load signal to load the 8 bits of the P-channel data D _pp in response to LD, clock code rate 3/4 the load signal CK _3/4
Parallel / serial conversion in synchronization with
It outputs punctured P-channel data D _ppc having a data rate equal to the clock frequency of the clock CK _3/4 for use.

Similarly, the shift register 67 for parallel / serial conversion for the Q channel outputs the pulse load signal LD.
, The 8-bit Q-channel data D _qp is loaded, and the loaded signal is subjected to parallel-to-serial conversion in synchronization with the coding rate 3/4 clock CK _3/4 to obtain the coding rate 3/4. And outputs punctured Q channel data D _qpc having a data rate equal to the clock frequency of the clock CK _3/4 for use.

As a prior art related to the present invention, a microfilm (Japanese Utility Model Application Laid-open No. Hei.
No. 118335), a control signal is unified so that the coding rate can be varied for each burst, and the final output is a clock having a coding rate of 1/2 for both the coding rate 1/2 and 3/4. "Punctured coding circuit"
Is disclosed.

[0009]

In the above-mentioned conventional punctured coding circuit, the shift register 61 for converting the data after the convolutional coding into serial / parallel data is used.
And 62 require 12 or more flip-flops connected for the P channel and the Q channel, respectively. Further, shift registers 61 and 6
After extracting necessary data from the parallel output of No. 2 and a circuit for generating pulse load signals LD for shift registers 66 and 67 for parallel-to-serial conversion,
A complicated circuit composed of a combination of the clock frequency dividing counter 63 for the coding rate 3/4 and the address decoder 64 is obtained. As described above, the conventional punctured coding circuit has a problem that the circuit scale is large and the signal delay in the punctured coding circuit is also large.

It is therefore an object of the present invention to provide a punctured coding circuit having a small circuit scale.

Another object of the present invention is to provide a punctured coding circuit having a small signal delay.

The prior art only discloses a punctured coding circuit capable of switching the coding rate for each burst, and can simplify P-channel data and Q-channel data having a coding rate of 3/4 as in the present invention. The purpose is different from that generated by a small-scale circuit.

[0013]

According to the present invention, Q channel data after convolutional coding and P channel data after convolutional coding are punctured and encoded.
In punctured coding circuit for outputting Q-channel data and puncture P-channel data after Chad after punctured, the coding rate of the clock frequency f _c 1/2
Signal generating circuit for generating an intermittent mask signal based on the clock for use, a mask circuit for masking the coding rate 1/2 clock with the intermittent mask signal and outputting an intermittent clock, and a clock frequency f in response to the double clock having twice the clock frequency 2f _c in _c, and intermittent clock retiming a clock retiming circuit for outputting the intermittent clock retiming, Q channel data after convolutional coding and A first data retiming circuit for retiming P channel data after convolutional encoding with a retimed intermittent clock and outputting first retimed Q channel data and first retimed P channel data And the first
Of the retimed Q channel data and the first retimed P channel data
(2/3) retimed to using the coding rate of 3/4 clock of f _c, and a second data retiming circuit for outputting a Q channel data and puncture P-channel data after Chad after punctured A punctured coding circuit characterized by having

[0014]

Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a punctured encoding circuit according to one embodiment of the present invention will be described. Punctured encoder shown, as an input signal, a coding rate of 1/2 clock CK _1/2 having a clock frequency f _c, the coding rate 3/4 with a clock frequency (2/3) f _c and use the clock CK _3/4, the double clock 2CK _1/2 having twice the clock frequency 2f _c of the clock frequency f _c, a counter load signal LD, and the P-channel data D _pc after convolutional coding, It receives the Q channel data D _qc after the convolutional coding. Punctured encoding circuit uses a coding rate of 1/2 clock CK _1/2 and a coding rate of 3/4 clock CK _3/4 and the double clock 2CK _1/2 and counter load signal LD, As described later, the P channel data D _pc after the convolutional coding and the Q channel data D _qc after the convolutional coding are punctured and the punctured P channel data D _ppc as an output signal.
And Q channel data D _qpc after puncturing.

The punctured encoding circuit includes a mask signal generation circuit 10, a mask circuit 20, a clock retiming circuit 30, a first data retiming circuit 40,
And a second data retiming circuit 50.

The mask signal generating circuit 10 generates an intermittent mask signal based on the counter load signal LD and the coding rate 1/2 clock CK _1/2 . Mask circuit 20
Masks the coding rate 1/2 clock CK _1/2 with an intermittent mask signal and outputs an intermittent clock. The clock retiming circuit 30 retiming the intermittent clock in response to the double clock 2CK1 _{/ 2} , and outputs the retimed intermittent clock. First data retiming circuit 40, a P-channel data D _pc after Q channel data D _qc and convolutional coding after convolutional coding, retiming intermittent clock retiming, first retiming The Q channel data and the first retimed P channel data are output. The second data retiming circuit 50 retimes the first retimed Q-channel data and the first retimed P-channel data using the coding rate 3/4 clock CK3 _{/ 4} and performs puncturing. It outputs Q channel data D _qpc after puncturing and P channel data D _ppc after puncturing.

The mask signal generation circuit 10 has a 1/3 frequency dividing counter 11, an inverter 12, and an AND gate 13. The 1/3 frequency dividing counter 11 has four data input terminals D ₀ , D ₁ , D ₂ , and D ₃ and a load terminal L
, A clock terminal C, and first and second data output terminals D ₀ and RCO. A clock terminal C is supplied with a coding rate 1/2 clock CK _1/2 . Of the four data input terminals D _{0 to} D ₃ , three data input terminals D ₀ , D ₂ and D ₃ have a logic high level “H”.
, And a signal of a logic low level “L” is supplied to the data input terminal D ₁ . The load terminal L is supplied with a logical product output signal from an AND gate 13 described later. The 1/3 frequency dividing counter 11 synchronizes with the coding rate 1/2 clock CK _1/2 and outputs the coding rate 1/2 clock C
A first and a second pulse having a pulse period three times the clock period of K _1/2 and having pulse widths twice and one times the clock period of the clock CK _1/2 for the coding rate 1/2, respectively.
Are output from the first and second data output terminals D ₀ and RCO. The second counter output signal is supplied to the inverter 12. Inverter 12
Inverts the second counter output signal and outputs an inverted counter output signal. The counter load signal LD is
Only when the load is instructed, the logic level is at the logic low level "L" for a predetermined period. The AND gate 13 calculates the logical product of the counter load signal and the inverted counter output signal, and supplies the logical product output signal to the load terminal L of the 1/3 frequency dividing counter 11. The mask signal generation circuit 10 outputs a Q-channel mask signal as a first counter output signal and a P-channel mask signal as an inverted counter output signal as intermittent mask signals.

The mask circuit 20 includes a mask signal generation circuit 1
It receives the Q-channel mask signal and the P-channel mask signal from 0 and outputs the Q-channel intermittent clock and the P-channel intermittent clock as the intermittent clock. The mask circuit 20 includes a clock C for coding rate 1/2.
AND gate 21 that masks K _1/2 with a Q channel mask signal and outputs a Q channel intermittent clock
And an AND gate 22 that masks the coding rate 1/2 clock CK _1/2 with a P channel mask signal and outputs a P channel intermittent clock.

The clock retiming circuit 30 receives the intermittent clock for the Q channel and the intermittent clock for the P channel as the intermittent clocks from the mask circuit 20, and receives the retimed clock for the Q channel and the retimed P channel. Output clock. Clock retiming circuit 30
Has two flip-flops 31 and 32 and an inverter 33. Inverter 33 is double clock 2
CK _1/2 is inverted and an inverted double clock is output. The flip-flop 31 performs retiming with the doubled clock obtained by inverting the intermittent clock for Q channel, and outputs the retimed clock for Q channel. The flip-flop 32 performs retiming with the doubled clock obtained by inverting the intermittent clock for the P channel, and outputs the retimed clock for the P channel.

The first data retiming circuit 40 receives the retimed Q channel clock and the retimed P channel clock as the retimed clock from the clock retiming circuit 30. The first data retiming circuit 40 retiming the convolutionally encoded Q channel data D _qc with the _retimed Q channel clock and outputs the first _retimed Q channel data And a flip-flop 42 for retiming the convolutionally encoded P-channel data D _pc with the re-timed P-channel clock and outputting the first re-timed P-channel data.

The second data retiming circuit 50 has a flip-flop 51, an inverter 52, and flip-flops 53 and 54. Flip-flop 5
1 retiming the first retimed Q channel data with a coding rate 3/4 clock CK _3/4 and outputs punctured Q channel data D _qpc .
The inverter 52 has a coding rate 3/4 clock CK _3/4
And outputs an inverted coding rate 3/4 clock. The flip-flop 53 retimed the first retimed P-channel data with the inverted coding rate 3/4 clock, and outputs additional retimed P-channel data. The flip-flop 54 converts the added retimed P-channel data into a code rate of 3 /
_{Retiming is performed} with the 4 clock CK _3/4 , and the punctured P-channel data D _PPC is output.

FIG. 2 is a timing chart for explaining the operation of the punctured encoding circuit shown in FIG.
Clock CK _1/2 for coding rate 1/2 and clock CK for coding rate 3/4 in the first and second rows, respectively.
Indicates _3/4 . The third and fourth rows show the double clock 2CK _1/2 and the counter load signal LD, respectively. Each fifth line and the sixth line indicating the first and second counter output signal that is output from the first and second data output terminal D ₀ and RCO 1/3 frequency-dividing counter 11. The seventh line shows the retimed Q-channel clock output from the flip-flop 31 of the clock retiming circuit 30. The eighth line shows the Q channel data D _qc after the convolutional coding. The ninth row shows the first retimed Q channel data output from the flip-flop 41 of the first data retiming circuit 40. The tenth row shows the punctured Q channel data D _qpc output from the flip-flop 51 of the second data retiming circuit 50. The eleventh row shows the retimed P-channel clock output from the flip-flop 32 of the clock retiming circuit 30. The twelfth line shows the P-channel data _Dpc after the convolutional coding. The thirteenth row shows the first retimed P-channel data output from the flip-flop 42 of the first data retiming circuit 40. The fourteenth row shows the additional retimed P-channel data output from the flip-flop 53 of the second data retiming circuit 50. On the fifteenth row, the punctured P-channel data D _ppc output from the flip-flop 54 of the second data retiming circuit 50
Is shown.

When a counter load signal LC of a logic low level "L" is supplied to the load terminal L of the 1/3 frequency dividing counter 11 via the AND gate 13, the 1/3 frequency dividing counter 11 receives the signal shown in FIG. As shown in the fifth and sixth rows, first and second data output terminals D ₀ and RC
O outputs first and second counter output signals, respectively. Inverter 12 inverts the second counter output signal and outputs the inverted counter output signal. The mask signal generation circuit 10 outputs the first counter output signal and the inverted counter output signal as a Q-channel mask signal and a P-channel mask signal, respectively.

First, the Q channel data will be described. AND gate 21 is a clock C for coding rate 1/2
K _1/2 is masked by a Q channel mask signal,
Outputs intermittent clock for Q channel. The flip-flop 31 is, as shown in the seventh row of FIG. 2, a 2 × 2 clock _1/2 inverted by the inverter 33.
The intermittent clock for the Q channel is retimed by the double clock, and the retimed clock for the Q channel is output. As shown in the eighth and ninth rows of FIG. 2, the flip-flop 41 re- _times the Q-channel data D _qc after the convolutional encoding with the re-timed Q-channel clock, and The re-timed Q channel data is output. As shown in the tenth row of FIG. 2, the flip-flop 51 re-times the first re-timed Q channel data with the coding rate 3/4 clock CK _3/4 and outputs the punctured Q channel data. The data D _qpc is output.

Next, the P channel data will be described. AND gate 22 is a clock CK for coding rate 1/2
Masking _1/2 by the mask signal for P channel,
Outputs the intermittent clock for the channel. As shown in the eleventh row of FIG. 2, the flip-flop 32 inverts the double clock 2CK _1/2 by the inverter 33,
The intermittent clock for P channel is retimed by the double clock, and the retimed clock for P channel is output. As shown in the twelfth and thirteenth rows in FIG. 2, the flip-flop 42
The channel data D _pc is _retimed by the _retimed P channel clock, and the first retimed P channel data is output. As shown in the fourteenth row of FIG.
2, the first retimed P-channel data is retimed with the coding rate 3/4 clock obtained by inverting the coding rate 3/4 clock CK _3/4 , and the additional retimed P-channel data is output. . As shown in the fifteenth row of FIG. 2, the flip-flop 54 performs retiming of the additionally retimed P-channel data with the coding rate 3/4 clock CK _3/4 ,
The channel data D _ppc is output.

The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

[0028]

As described above, the punctured encoding circuit according to the present invention retiming data after convolutional encoding by an intermittent clock generated by using an intermittent mask signal. Since puncturing is performed by further retiming the obtained data using a coding rate 3/4 clock, the circuit configuration is simplified and the circuit scale is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a punctured encoding circuit according to one embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the punctured encoding circuit shown in FIG.

FIG. 3 is a block diagram showing a conventional punctured encoding circuit.

[Explanation of symbols]

 Reference Signs List 10 mask signal generation circuit 20 mask circuit 30 clock retiming circuit 40 first data retiming circuit 50 second data retiming circuit

Claims (6)

(57) [Claims] 1. A punctured encoder for puncturing Q channel data after convolutional encoding and P channel data after convolutional encoding and outputting punctured Q channel data and punctured P channel data. in the encoding circuit, and the mask signal generating circuit for generating a intermittent masking signal based on a coding rate of 1/2 clock of the clock frequency f _c, the coding rate of ½ clock the intermittent masking masked by the signal, and a mask circuit that outputs the intermittent clock twice the clock frequency 2f _c of the clock frequency f _c
A clock retiming circuit for retiming the intermittent clock in response to a double clock having the following, and outputting the retimed intermittent clock; and Q channel data after the convolutional encoding and after the convolutional encoding. A first data retiming circuit for retiming P-channel data with the retimed intermittent clock and outputting first retimed Q-channel data and first retimed P-channel data; the Q-channel data and said second 1 P-channel data retiming that retiming retime using a clock frequency (2/3) coding rate 3/4 clock of f _c, Q channel after said punctured A second output of the data and the punctured P-channel data. A punctured encoding circuit comprising: a data retiming circuit. 2. The mask signal generating circuit according to claim 1, wherein the intermittent mask signal includes a Q-channel mask signal and a P-channel mask signal.
Outputting a channel mask signal, wherein the mask signal generation circuit receives the coding rate 1/2 clock at a clock terminal,
First and second pulses having a pulse period three times the clock period of the coding rate 1/2 clock and having pulse widths twice and one times the clock period of the coding rate 1/2 clock, respectively. A 1/3 divider counter that outputs the counter output signal of the above, an inverter that inverts the second counter output signal and outputs the inverted counter output signal, and a logic low for a predetermined period only when the load is instructed. An AND gate for obtaining a logical product of a counter load signal serving as a level and the inverted counter output signal and supplying a logical product output signal to a load terminal of the １ ／ frequency dividing counter; The output signal and the inverted counter output signal are output as a mask signal for a Q channel and a mask signal for a P channel, respectively. It punctured encoding circuit as claimed. 3. The mask circuit receives a Q-channel mask signal and a P-channel mask signal as the intermittent mask signal, and outputs a Q-channel intermittent clock and a P-channel intermittent clock as the intermittent clock. A mask circuit for masking the coding rate 1/2 clock with the Q channel mask signal to output the Q channel intermittent clock; and a first AND gate for outputting the Q rate intermittent clock. 2. The punctured encoding circuit according to claim 1, further comprising: a second AND gate that masks a clock with the P-channel mask signal and outputs the P-channel intermittent clock. 4. The clock retiming circuit receives a Q-channel intermittent clock and a P-channel intermittent clock as the intermittent clock, and re-timed the Q-channel clock and the re-timed P-channel clock as the retimed clock. A clock, and the clock retiming circuit inverts the double clock and outputs an inverted double clock; and retiming the intermittent clock for Q channel with the inverted double clock, A first flip-flop that outputs the retimed Q-channel clock; and a second flip-flop that retimed the P-channel intermittent clock with the inverted double clock and outputs the retimed P-channel clock. Flip-flops and 2. The punctured encoding circuit according to claim 1, comprising: 5. The first data retiming circuit,
Upon receiving the retimed Q-channel clock and the retimed P-channel clock as the retimed clock, the first data retiming circuit generates the retimed Q channel data after the convolutional encoding. A first flip-flop for retiming with the channel clock and outputting the first retimed Q channel data; and retiming the convolutionally encoded P channel data with the retimed P channel clock. 2. The punctured encoding circuit according to claim 1, further comprising: a second flip-flop that outputs the first retimed P-channel data. 6. The second data retiming circuit retiming the first retimed Q channel data with the coding rate 3/4 clock, and outputs the punctured Q channel data. A first flip-flop that inverts the coding rate 3/4 clock and outputs an inverted coding rate 3/4 clock; and inverts the first retimed P-channel data. With the coding rate 3/4 clock,
A second flip-flop for outputting additional retimed P-channel data, and retiming the additional retimed P-channel data with the coding rate 3/4 clock, 2. The punctured encoding circuit according to claim 1, further comprising a third flip-flop for outputting channel data.