JP2616720B2 - Test method for semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor memory device, and more particularly to a method for testing a low power supply voltage data retention characteristic of an SRAM.

[0002]

2. Description of the Related Art In an SRAM, in order to reduce power consumption, it is general to lower a power supply voltage to a level at which stored data is not destroyed when data other than read and write operations is held, and to hold data in that state. It is being done. The present invention relates to a test method for ensuring data retention at such a low power supply voltage. In this test, data is usually written to a memory cell with a high power supply voltage, and then data is held for a predetermined time while the power supply voltage is _lowered to a voltage V _HOLD lower than the voltage at the time of writing. Data is read with the voltage raised to the original voltage, and the quality of the memory is determined by checking whether the read data matches the write data. Here, the low power supply voltage V _HOLD at the time of data retention is a voltage obtained by subtracting a margin from the power supply voltage V _CCDR that guarantees data retention (data retention) for the user. The voltage is such that data can be held even with V _HOLD . Regarding the test method of the low power supply voltage data retention characteristic as described above,
A conventional method will be described using an SRAM having a configuration in which the memory cells shown in FIG. 3 are arranged in an array as an example.

FIG. 2 shows a node (node N or node ▽ N (▽ is a substitute for an upper bar) for inversion) in the memory cell shown in FIG. 3, whichever has a higher potential.
FIG. 7 is a diagram showing a state of a temporal change of a potential (assuming that a node N is at a high potential). Referring to FIGS. 2 and 3, in this memory cell, data writing is performed at power supply voltage V _TYP satisfying the recommended operating conditions, and the initial potential of node N is:
The potential V _TYP is equal to the power supply voltage at the time of writing.
The power supply voltage of the memory cell to which this writing has been performed is set to voltage V
FIG. 2 shows how the potential of the node N changes with time from the time when the voltage is lowered to _HOLD . The node N potential decreases with a time constant C · R determined by the product of the capacitance value C of the parasitic capacitance C ₁ between the memory cell and the substrate and the resistance value R of the high resistance load R ₁ , and finally decreases. Saturates at voltage V _HOLD . At this time, the node N potential cuts off a voltage value equal to the data retention guarantee power supply voltage V _CCDR when the time T _{2 in the} middle of the decrease has elapsed. As described above, the power supply voltage of the memory cell into which the data is written is lowered to the voltage V _HOLD , the data is held for at least the time T ₂ , and the reading is performed after it is certain that the potential of the node N has fallen below the potential V _CCDR. If the read data and the write data at that time match, it is determined that this memory cell can guarantee data retention at the power supply voltage _VCCDR .
In the low power supply voltage data retention characteristic test, pass / fail of the SRAM is determined based on the result of performing such a procedure on all the memory cells.

FIG. 4 is a flowchart showing the above-described test procedure for a conventional test method. Referring to FIG. 4, first, the power supply voltage of the SRAM to be tested is set to voltage V _TYP (step S ₁ ), and data is written to all the memory cells (step S ₂ ).

Next, the power supply voltage of the SRAM is reduced to the voltage V _HOLD to hold data for a time T ₂ (step S 2).
₃ ). In this case, the length of time T _2, as described above, by flowing current from the node N of the memory cell through the load R ₁ a high resistance to a power supply terminal, to the node N voltage becomes less than the potential V _CCDR Time is needed. This time T ₂ depends on a time constant C · R determined by the product of the resistance value R of the load resistors R ₁ and R ₂ and the value C of the parasitic capacitance generated between the memory cell nodes N and ΔN and the substrate. and, the time constant C · R must lengthen the time T ₂ the larger. The time T ₂ also depends on the difference between the power supply voltage used for writing and the power supply voltage when data is held, and the larger the potential difference, the longer the time T ₂ .

After the data is held, the power supply voltage is raised to the voltage V _TYP again, data is read from all the memory cells (step S ₄ ), and it is determined whether correct data has been read (step S ₄ ). ₅ ).

If the result of the judgment is "good" (step S
₆ ), data opposite to the write data tested first (for example, if the first data is "0", "1", "1"
If "0"), a similar test for finally determining the acceptability of the test subject SRAM (step S _8).

[0008]

In testing the low power supply voltage data holding characteristic of the SRAM, as described above, the time constant _CR or the write power supply voltage V _TYP and the power supply voltage V _HOLD for holding data are used. The test must be performed with a sufficient data retention time according to the potential difference of In particular, in the test of the data retention characteristics at low temperature, since the resistance value of the high resistance load of the memory cell is higher than normal temperature, one S
A problem arises in that the data holding time must be extended to more than ten seconds for each RAM.

Accordingly, an object of the present invention is to provide a method for testing a low power supply voltage data retention characteristic accurately in a short time.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for testing a static random access memory to be tested.
Detecting in advance a minimum power supply voltage specific to the access memory and capable of writing to all memory cells; writing data to the memory cells with the detected minimum power supply voltage; Holding the data for a predetermined period of time determined by the power supply voltage at which writing is performed in a state where the voltage is reduced to a voltage equal to or lower than the power supply voltage for guaranteeing the data holding; Performing a read operation for data confirmation in a state where the voltage is increased to a sufficient voltage. Shortening is realized.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart of a method for testing a semiconductor memory device according to one embodiment of the present invention. Referring to FIG. 1, in the present embodiment, before writing data, a test for detecting a minimum power supply voltage V _WMIN at which data can be written is performed for each SRAM. Then, the power supply voltage is set to a voltage lower than the recommended operation power supply voltage V _TYP and not lower than the power supply voltage V _CCDR which guarantees data retention (step S ₁₀ ). If this voltage is too high, V _WMIN cannot be detected;
Since it takes a long test time to detect _WMIN , it is necessary to set an appropriate voltage in consideration of the characteristics of the product.

[0012] Next, write data to all the memory cells of the SRAM to be tested in the power supply voltage set (step S _20), data is read from all the memory cells immediately after (step S _21). The time required for this process is represented by the product of the SRAM access time T _AA and the number of memory cells. For example, if the access time is 1 nanobit and the access time is 50 nanoseconds, it takes 0.05 seconds to read and write, respectively. It was right or wrong judgment of the read data (step S ₂₂₎ results, and if the read is correct data can be the voltage V _WMIN. If you can not if reading the correct data, testing the reset the power supply voltage to a voltage slightly higher than the initially set voltage (step S _25), the step S ₂₀ to step S _22. Again, if the voltage increase is too large, V _WMIN cannot be detected. If it is too small, the test time will be required _instead of V _WMIN detection, so an appropriate _voltage increase (eg, about 0.1 V to 0.2 V) Need to increase.

When the minimum power supply voltage V _{WMIN at} which all the memory cells can be written can be detected by the above process, the power supply voltage is held for the product in the same manner as in the conventional example. Power supply voltage V _CCDR that guarantees
The power supply voltage V _HOLD is set as follows and the data can be held in the test, and the data is held (step S ₃₀ ).
In this case, as described in the section of the related art, the time required for holding data is the node N of the memory cell in FIG.
Or ▽ current from the N is high-resistance load R ₁ or Time to node potential by flowing through R ₂ is below V _CCDR (shown by T ₁ in FIG. 4). That is, since the power supply voltage V _{WMIN at} which the writing is performed is lower than the power supply voltage V _TYP at the time of writing in the conventional test method, the time T ₁ can be set shorter than the time T ₂ . The time difference between the time T ₂ and the time T ₁ is equal to the time required for the node potential of the memory cell written with the power supply voltage V _TYP to attenuate along a curve determined by the time constant C · R and reach the potential V _WMIN . , Quantitatively expressed by the following equation.

T ₂ −T ₁ = C · Rlog (V _TYP −V _MIN ) This value depends on the time constant CR and the voltage V _WMIN , but is SRA
It is several seconds per M. On the other hand, the time required to detect V _WMIN is about 1 second, assuming that data is read and written 10 times. Therefore, from the time difference T ₂ −T ₁ to V
_The test time can be reduced by the difference from the time required to determine _WMIN .

[0015] After the data held in step S ₃₀ is,
As before, the power supply voltage is increased again to the voltage V _TYP ,
Reads from the data of all the memory cells (step S _4), it determines whether the correct data is read (step S _5). If the result of the judgment is “pass”, the same test is performed on the data opposite to the data that was initially tested (“1” if the first data is “0”, “0” if “1” is “1”). Whether the product is acceptable or not is determined (step S ₈ ).

[0016]

As described above, in the method of testing a semiconductor memory device of the present invention, a test for detecting the minimum power supply voltage at which data can be written for each SRAM before performing data writing. And writing is performed with the low power supply voltage obtained by the test.

Thus, according to the present invention, the time required for data retention can be shortened, and as a result, the test time for low power supply voltage data retention characteristics can be shortened.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a test procedure according to an embodiment of the present invention.

FIG. 2 is a diagram showing a temporal change of a node potential in a memory cell when a power supply voltage at the time of data holding is lower than a power supply voltage at a time of writing in an SRAM.

FIG. 3 is a circuit diagram illustrating an example of an SRAM memory cell;

FIG. 4 is a flowchart showing a conventional test procedure.

[Explanation of symbols]

R ₁ , R ₂ load resistance C ₁ , C ₂ parasitic capacitance

Claims (1)

(57) [Claims] 1. A static random access memory to be tested for a static random access memory.
The scan memory of the specific, the step of writing to all the memory cells are detected in advance the minimum supply voltage available, the step of writing data into the memory cell in the detected minimum power supply voltage, the supply voltage data Holding the data for a predetermined time determined by the power supply voltage to which writing has been performed in a state where the power supply voltage has been reduced to a voltage equal to or lower than the power supply voltage for guaranteeing the data retention; Performing a read operation for data confirmation in a state where the voltage has been increased to a sufficient voltage.