JP2615843B2 - Digital PLL circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a digital PLL circuit for converting a frequency-modulated signal into a DC signal corresponding to the frequency.

(Prior art)

Conventional PLL circuits include analog PLL circuits and their
A digital PLL circuit in which the VCO is replaced with a reference clock, a frequency divider, and a multiplexer is used. A digital PLL circuit can be easily integrated with other logic. FIG. 4 is a circuit diagram showing an example of a digital PLL circuit used to convert an input signal subjected to frequency shift keying (hereinafter referred to as FSK) into an NRZ signal. In this figure, a fixed frequency sufficiently higher than the FSK input signal, for example, a clock frequency of 2 MHz, is applied to the multiplexer 2 via the divide-by-4 circuit 1 and directly. The multiplexer 2 includes NAND circuits 2a and 2b, a NAND circuit 2c connected to an output terminal thereof, and input NAND circuits 2a and 2b.
It has an inverter 2d for switching b, selects these signals based on a selection signal given from the outside, and supplies its output to the 32 frequency dividing circuit 3. 32 frequency divider 3
Supplies a frequency divided output to an exclusive OR circuit 4 which is a phase comparator. An FSK input signal is provided to the other input terminal of the exclusive OR circuit 4, and an exclusive OR output is provided to the D flip-flop 5 and the multiplexer 2 as a control signal. The D flip-flop 5 outputs this phase comparison output as a signal synchronized with the clock signal. The output of the D flip-flop 5 is applied to a waveform shaping circuit 7 via an integrating circuit 6, and is output as an NRZ signal corresponding to the FSK input.

FIG. 5 is a time chart showing the operation of this conventional digital PLL circuit. As shown in FIGS. 5 (a) and 5 (b), the clock signal of 2 MHz is frequency-divided by the frequency dividing circuit 1 and applied to the multiplexer 2. Assuming that a frequency-divided output as shown in FIG. 5 (c) is obtained from the 32 frequency divider 3, this signal and the FSK input signal are supplied to an exclusive OR circuit 4 which is a phase comparator. A signal as shown in FIG. 5 (e) is output. When this output is at "H" level, a 2 MHz signal which is not divided by the 4 divider circuit 1 is directly supplied to the 32 divider circuit 3, and at "L" level, the signal divided by 4 is applied to the 32 divider circuit 3. Given to. Therefore, the frequency of the FSK input signal increases, and if the phase is advanced at a certain point, the period of the “H” level of the output of the EOR circuit 4 becomes longer,
Control is performed so that a clock signal that is not divided by 4 is passed for a longer time than the divided output. Accordingly, the number of clocks input to the 32 frequency dividing circuit 3 increases, so that the phase of the output signal of the 32 frequency dividing circuit 3 also follows the input signal. This signal is output as a signal synchronized with the clock via the D flip-flop 5, and its duty ratio corresponds to the FSK signal. Therefore, the integrating circuit 6 and the waveform shaping circuit 7
The original NRZ signal can be restored by identifying this signal via.

[Problems to be solved by the invention]

However, according to such a conventional digital PLL circuit, when the output of the EOR circuit 4 changes when the clock signal input to the multiplexer or its divide-by-4 output is at the “H” level, FIG. Hazard as shown occurs. A hazard also occurs when two inputs of the NAND circuits 2a and 2b of the multiplexer 2 change simultaneously. Such a hazard occurs irregularly, but if it occurs, there is a drawback that the output phase of the 32 divider circuit is not stable and jitter may occur in the output of the PLL circuit.

The present invention has been made in view of such a problem of the conventional digital PLL circuit, and has as its technical object to stabilize the output phase so as not to cause jitter.

[Structure and effect of the invention]

(Means for Solving the Problems) The present invention provides a first frequency divider for dividing a clock signal having a constant frequency higher than an input signal, a clock signal and a first frequency divider.
A multiplexer for selecting the divided output of the divider circuit, a second divider circuit for dividing the output of the multiplexer,
A phase comparison circuit that outputs a phase comparison signal by an exclusive OR of an output of the frequency divider circuit and the input signal, and provides a selection signal to the multiplexer. A flip-flop provided at one end for synchronizing an input signal with the output of the multiplexer, and a first output provided by a phase comparison circuit.
And a clear circuit for clearing the frequency divider circuit, wherein the input of the clock signal and the input of the first frequency divider circuit are switched when the respective outputs do not change.

(Operation) According to the present invention having such features, a signal obtained by synchronizing an input signal with an output of a multiplexer is provided to a phase comparison circuit, and the first frequency division circuit is cleared by the output of the phase comparison circuit. I am trying to do it. Therefore, the output of the multiplexer and the input signal are synchronized. Further, the first frequency dividing circuit is cleared by the output of the phase comparing circuit. Therefore, switching between the clock signal and its frequency-divided output by the multiplexer is always performed after these inputs have become "L" level, and no hazard is generated.

(Effects of the Invention) Therefore, according to the present invention, the operation is stable without generating an irregular hazard in the PLL circuit, so that noise larger than the quantization error due to sampling of the input signal does not appear as an output of the PLL circuit. This has the effect of stabilizing the output.

[Explanation of Example]

FIG. 1 is a block diagram showing a configuration of a digital PLL circuit according to one embodiment of the present invention. In this figure, the same parts as those of the conventional example are denoted by the same reference numerals. Now, a clock signal having a constant frequency sufficiently higher than the FSK input signal is supplied to a first frequency dividing circuit, in this embodiment, a frequency dividing circuit 1 and a multiplexer 2 via an inverter 11. The divide-by-4 circuit 1 is supplied with a clear signal from the clear circuit 12, and when this signal is at the "L" level, divides the input signal by four and supplies a divided output to the multiplexer 2. The clear circuit 12 is the NOR circuit 13
And a logical sum of the reset signal and the phase comparison signal is given to the divide-by-4 circuit 1 as a clear signal. The multiplexer 2 selects one of these inputs based on a selection signal as in the above-described conventional example.
The signals 2a and 2b and the selection input signal are supplied to the NAND circuit 2a directly or via the inverter 2d, and the outputs of the NAND circuits 2a and 2b are supplied to the NAND circuit 2c. The NAND circuit 2c uses the logical product signal as an output of the multiplexer 2 via the inverter 15 to output a second frequency dividing circuit, for example, a 32 frequency dividing circuit 3 in this embodiment.
And a clock input terminal of the flip-flop 14. 32
The frequency dividing circuit 3 divides an input signal by 32, and its output is given to an EOR circuit 4 which is a phase comparing circuit. Also FSK
The input signal is provided to the D input terminal of the D flip-flop 16. The D flip-flop 16 is a flip-flop for synchronizing an input signal with the output of the multiplexer 2, and its output is given to the EOR circuit 4. The EOR circuit 4 supplies these exclusive OR outputs to the D-type flip-flop 5 and to the multiplexer 2 as a selection signal, and further to the frequency dividing circuit 1 via the clear circuit 12 as a clear signal. The output of the D-type flip-flop 5 is supplied to the integrating circuit 6 and the waveform shaping circuit 7 in the same manner as in the above-described conventional example, and the NRZ
It is converted into a signal and output. A reset input signal is supplied to a NOR circuit 13, a 32 frequency divider 3, and a D-type flip-flop 5.

Next, the operation of this embodiment will be described with reference to a time chart. FIG. 2A shows a clock input signal having a frequency sufficiently higher than the FSK input signal, for example, 2 MHz. This signal is supplied to the multiplexer 2 via the inverter 11 and the divide-by-4 circuit 1 or directly. When the clear signal is not supplied from the clear circuit 12, the clock signal is divided by four as shown in FIG.
Is added to The multiplexer 2 selects one of the inputs according to the output of the EOR circuit 4 and supplies it to the 32 frequency dividing circuit 3 via the inverter 13. If the FSK input signal is
If it changes as shown in FIG. 2D, its input is applied to the exclusive OR circuit 4 by a flip-flop 16 as a signal synchronized with the output of the multiplexer 2 as shown in FIG. Becomes Therefore, the FSK input signal and the 32 frequency dividing circuit 3 are synchronized with the falling point of the multiplexer 2. When the output of the EOR circuit 4 becomes "H" level, the divide-by-4 circuit 1 is stopped at "L" level. Therefore, the switching of the signal by the multiplexer 2 is always performed after the two inputs have become "L" level, so that the hazard does not occur. Therefore, noise equal to or larger than the quantization error due to the FSK input signal does not appear as an output of the phase comparator 6. This signal is supplied to the integration circuit 6 via the D flip-flop 5, and further demodulated as the original NRZ signal via the waveform shaping circuit 7.

Such a digital PLL circuit is used in, for example, an ID system for identifying an article as shown in FIG. FIG. 3 is a block diagram showing the outline of the ID system. An ID unit 21 including a memory for holding its own data is attached to an article.
By performing data communication with the read control unit 22, predetermined data is written to or read from the memory in the ID unit 21. The write / read control unit 22 is connected to a controller 23, a biphase encoding circuit 24, an FSK modulation circuit 25, and an oscillator 26, and data and commands are transmitted by, for example, microwaves. The signal obtained from the ID unit 21 is received by the receiving circuit 27, and the above-described PLL circuit 2
The FSK-modulated signal is demodulated via 8 and supplied to the controller 23 via the bi-phase decoding circuit 29.

The ID unit 21 is a receiving circuit for receiving the signal of the oscillator 26.
31, if a predetermined frequency, for example, an FSK signal is a signal that alternately switches between 30 KHz and 50 KHz, it has a band-pass filter 32 that passes a signal within that range, and the output signal is given to the PLL circuit 33 described above. The FSK signal is demodulated. Then, the command and the data are decoded through the bi-phase decoding circuit 34 and provided to the memory control unit 35. The memory control unit 35 writes or reads necessary data in the memory 36 in the ID unit 21. The read data is supplied to the FSK modulation circuit 38 via the bi-phase encoding circuit 37. The FSK modulation circuit 38 FSK-modulates the signal based on the bi-phase code and transmits the signal to the write / read control unit 22 via the oscillator 39. In the ID system having such a configuration, the consumption current changes due to the start and stop of the operation of the internal circuit due to the exhaustion of the battery of the ID unit 21, and the fluctuation of the power supply voltage supplied from the power supply and the fluctuation of the ambient temperature. Although the operating conditions change, demodulation can be performed stably using the digital PLL circuit according to the present invention, so that the fluctuation of the operating distance and the data transmission range is reduced, and the effect that errors are less likely to be established is reduced. can get.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a digital PLL circuit according to one embodiment of the present invention, FIG. 2 is a time chart showing the operation thereof, and FIG. 3 is an overall configuration of an ID system using the PLL circuit according to this embodiment. FIG. 4 is a block diagram showing an example of a conventional digital PLL circuit, and FIG. 5 is a time chart showing the operation thereof. 1 divide-by-4 circuit, 2 multiplexor, 3 divide-by-32 circuit, 4 phase comparator circuit, 5, 16 flip-flop, 6 integrating circuit, 7 waveform shaping circuit, 11 , 14,15…
… Inverter, 12… Clear circuit, 13… Nor circuit

Claims (1)

(57) [Claims] 1. A first frequency divider for dividing a clock signal having a constant frequency higher than an input signal, a multiplexer for selecting the clock signal and a divided output of the first frequency divider, and the multiplexer. A second frequency divider for dividing the output of the second frequency divider; and a phase comparator for outputting a phase comparison signal by an exclusive OR of an output of the second frequency divider and an input signal, and providing a selection signal to the multiplexer. And a flip-flop wherein an output of the multiplexer is provided to a clock input terminal to synchronize the input signal with an output of the multiplexer; and a first frequency divider circuit based on an output of the phase comparison circuit. And a switching circuit for switching the input of the clock signal and the input of the first frequency dividing circuit when the respective outputs do not change. Digital PLL circuit being characterized in that the Migihitsuji.