JP2613917B2 - Circuit analysis method - Google Patents
Circuit analysis methodInfo
- Publication number
- JP2613917B2 JP2613917B2 JP63169835A JP16983588A JP2613917B2 JP 2613917 B2 JP2613917 B2 JP 2613917B2 JP 63169835 A JP63169835 A JP 63169835A JP 16983588 A JP16983588 A JP 16983588A JP 2613917 B2 JP2613917 B2 JP 2613917B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- analysis
- storage means
- terminals
- invalid
- Prior art date
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は回路解析方式に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a circuit analysis system.
従来の回路解析方式は、例えば［遅延時間解析システ
ム−NELTAS2−］（情報処理学会、設計自動化研究会資
料、設計自動化14−３、1982）に記載されているよう
に、回路の端子、端子間の接続および各接続に関する情
報により、端子間における信号の遅延時間や波形歪み等
を算出し、その結果を出力するが、そのとき、回路上で
の信号の無効な伝播経路の情報は用いられていない。As described in, for example, [Delay Time Analysis System -NELTAS2-] (Information Processing Society of Japan, Design Automation Study Group Material, Design Automation 14-3, 1982), a conventional circuit analysis Based on the connections and information on each connection, the delay time and waveform distortion of signals between terminals are calculated, and the results are output. At this time, information on invalid propagation paths of signals on the circuit is used. Absent.
上述した従来の回路解析方式は、回路上での信号の無
効な伝播経路の情報を用いずに回路の解析を行なってい
たので、実際の回路上では存在しない信号の流れをも解
析および出力の対象としてしまうという欠点がある。そ
のため、出力された解析結果のうちから、無効なものは
人手により除外するような作業を必要とするという問題
等がある。In the conventional circuit analysis method described above, since the circuit is analyzed without using information on the invalid propagation path of the signal on the circuit, the analysis and output of the signal flow that does not exist on the actual circuit are performed. There is a disadvantage that it is targeted. Therefore, there is a problem that it is necessary to manually remove an invalid analysis result from the output analysis results.
〔課題を解決するための手段〕 本発明の回路解析方式は、回路の端子、端子間の接続
および各接続に関する情報を記憶する回路記憶手段
（１）と、 回路上での信号の無効な伝播経路を複数の端子の組に
より記憶する無効点記憶手段（２）と、 前期回路記憶手段（１）が記憶する情報に基づいて回
路解析を行い、該回路解析の結果のうちから、前記無効
点記憶手段が記憶する回路上での信号の無効な伝播経路
を対象からはずして出力する回路解析手段（３）とを含
むことを特徴とする。[Means for Solving the Problems] A circuit analysis method according to the present invention comprises: a circuit storage means (1) for storing terminals of a circuit, connections between terminals, and information on each connection; and invalid propagation of a signal on the circuit. An invalid point storage means (2) for storing a path by a set of a plurality of terminals; and a circuit analysis based on the information stored in the circuit storage means (1). Circuit analysis means (3) for removing an invalid propagation path of a signal on a circuit stored in the storage means from a target and outputting the signal.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例であり、回路記憶手段1,無
効点記憶手段2,回路解析手段３および解析結果表示手段
４から成る。FIG. 1 shows an embodiment of the present invention, which comprises circuit storage means 1, invalid point storage means 2, circuit analysis means 3, and analysis result display means 4.
回路記憶手段１は、回路の端子，端子間の接続および
各接続に関する情報を記憶する。無効点記憶手段２は、
回路上での信号の無効な伝播経路を複数の端子の組によ
り記憶する。回路解析手段３は、前記回路記憶手段１の
情報に基づき解析し、前記無効点記憶手段２の情報に基
づき回路上での信号の無効な伝播経路を対象からはずし
て解析結果を解析結果表示手段４へ出力する。解析結果
表示手段４は、該回路解析手段３により解析された結果
を表示する。The circuit storage unit 1 stores the terminals of the circuit, the connections between the terminals, and information on each connection. Invalid point storage means 2
An invalid propagation path of a signal on the circuit is stored by a set of a plurality of terminals. The circuit analysis means 3 analyzes based on the information in the circuit storage means 1, removes an invalid propagation path of a signal on the circuit from the target based on the information in the invalid point storage means 2, and displays the analysis result as an analysis result display means. Output to 4. The analysis result display means 4 displays the result analyzed by the circuit analysis means 3.
第２図は、本実施例を説明するためにモデル化して示
された回路パッケージ例である。FIG. 2 is an example of a circuit package modeled and shown to explain the present embodiment.
第２図において、（１），（２），（９）および（1
0）は回路パッケージの端子、（３），（４）および
（５）は回路素子100の端子、（６），（７）および
（９）は回路素子200の端子を示す。In FIG. 2, (1), (2), (9) and (1)
0) indicates a terminal of the circuit package, (3), (4) and (5) indicate terminals of the circuit element 100, and (6), (7) and (9) indicate terminals of the circuit element 200.
いま、端子（１）→（３）→（５）→（６）→（８）
→（10）を通る信号と、端子（２）→（４）→（５）→
（６）→（７）→（９）を通る信号が存在するものとす
ると、当然これらの伝播経路も存在することになる。し
かし、回路動作上端子（１）→（３）→（５）→（６）
→（７）→（９）という信号の流れは存在しない場合に
は、無効点記憶手段２に端子（３）及び（７）を記憶す
る。Now, terminals (1) → (3) → (5) → (6) → (8)
→ Signal passing through (10) and terminal (2) → (4) → (5) →
Assuming that there is a signal passing through (6) → (7) → (9), naturally, these propagation paths also exist. However, due to circuit operation, terminals (1) → (3) → (5) → (6)
If there is no signal flow of → (7) → (9), the terminals (3) and (7) are stored in the invalid point storage means 2.
第３図は、第１図における回路解析手段３の処理手順
例である。FIG. 3 is an example of a processing procedure of the circuit analysis means 3 in FIG.
開始処理S1により処理がはじまる。終了判断処理S2で
は、出力すべき総ての経路が解析された時のみ終了処理
S5へ移り、それ以外の場合は解析処理S3へ移る。The process starts with the start process S1. In the end judgment processing S2, the end processing is performed only when all the routes to be output are analyzed.
Move to S5, otherwise proceed to analysis processing S3.
解析処理S3では１つの経路について遅延等の回路解析
を行なう。次に、限定処理S4では、解析処理S3において
解析された経路が、第１図における無効点記憶手段２に
格納された情報に該当しない場合にのみ、第１図におけ
る解析結果表示手段４へ解析結果を出力して終了判断処
理S2へ移る。第１図における無効点記憶手段２に格納さ
れた情報に該当する場合には、何も出力せずに終了判断
処理S2へ移る。終了処理S5において一連の処理が終了す
る。In the analysis process S3, circuit analysis such as delay is performed for one path. Next, in the limitation processing S4, the analysis result is displayed on the analysis result display means 4 in FIG. 1 only when the path analyzed in the analysis processing S3 does not correspond to the information stored in the invalid point storage means 2 in FIG. The result is output, and the routine proceeds to end determination processing S2. If the information corresponds to the information stored in the invalid point storage means 2 in FIG. 1, the process proceeds to the end determination processing S2 without outputting anything. A series of processes ends in the end process S5.
以上説明したように本発明は、回路上での信号の無効
な伝播経路の情報を用いて、回路上では存在しない信号
の、流れを解析結果出力の対象からはずす効果がある。As described above, the present invention has an effect of removing the flow of a signal that does not exist on a circuit from the analysis result output target by using information on an invalid propagation path of the signal on the circuit.
第１図は、本発明の一実施令のブロック図、第２図は、
本実施例を説明するためのモデル化された回路パッケー
ジ図、第３図は本実施例のフローチャートである。 （１）……回路記憶手段、（２）……無効点記憶手段、
（３）……回路解析手段、（４）……解析結果表示手
段。FIG. 1 is a block diagram of one implementation order of the present invention, and FIG.
FIG. 3 is a flow chart of the present embodiment, illustrating a modeled circuit package diagram for explaining the present embodiment. (1) ... circuit storage means, (2) ... invalid point storage means,
(3) ... circuit analysis means, (4) ... analysis result display means.
Claims (1)
関する情報を記憶する回路記憶手段（１）と、 回路上での信号の無効な伝播経路を複数の端子の組によ
り記憶する無効点記憶手段（２）と、 前期回路記憶手段（１）が記憶する情報に基づいて回路
解析を行い、該回路解析の結果のうちから、前記無効点
記憶手段が記憶する回路上での信号の無効な伝播経路を
対象からはずして出力する回路解析手段（３）とを含む
ことを特徴とする回路解析方式。A circuit storage means (1) for storing terminals of a circuit, connections between terminals and information on each connection, and an invalid point for storing an invalid propagation path of a signal on the circuit by a set of a plurality of terminals. A circuit analysis is performed based on the information stored in the storage means (2) and the circuit storage means (1), and, based on the result of the circuit analysis, a signal on the circuit stored in the invalid point storage means is invalidated. Circuit analysis means (3) for removing a propagation path from a target and outputting the result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169835A JP2613917B2 (en) | 1988-07-06 | 1988-07-06 | Circuit analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63169835A JP2613917B2 (en) | 1988-07-06 | 1988-07-06 | Circuit analysis method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0219782A JPH0219782A (en) | 1990-01-23 |
| JP2613917B2 true JP2613917B2 (en) | 1997-05-28 |
Family
ID=15893803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63169835A Expired - Lifetime JP2613917B2 (en) | 1988-07-06 | 1988-07-06 | Circuit analysis method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2613917B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3137056B2 (en) | 1997-11-19 | 2001-02-19 | 日本電気株式会社 | Fault propagation path extraction system and method, and recording medium on which control program is recorded |
-
1988
- 1988-07-06 JP JP63169835A patent/JP2613917B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0219782A (en) | 1990-01-23 |
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