JP2612213B2 - IC test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus for inspecting an electrical characteristic of an IC (integrated circuit), and particularly to an analog output signal output from an IC to be measured. The present invention relates to an IC test apparatus in which a comparison circuit for converting a digital logic signal is improved.

[Conventional technology]

In order to ship an IC with guaranteed performance and quality as a final product, it is necessary to extract all or a part of the IC product in each process of the manufacturing department and the inspection department and inspect various electrical characteristics. An IC test device is a device for inspecting such electrical characteristics.

The IC test equipment gives a predetermined test pattern signal to the IC under test, reads the output signal waveform output from the IC under test, and analyzes whether there is any problem in the basic operation and function of the IC under test Then, the electrical characteristics of the IC to be measured are inspected.

However, the output signal waveform actually output from the IC under test is an analog waveform, and the IC test apparatus must analyze the failure information based on the analog output signal waveform. Therefore, in the IC test apparatus, the output signal waveform from the IC under test is temporarily converted into a digital logic signal by a comparison circuit, and the IC under test is inspected based on the logic signal.

FIG. 2 is a diagram showing the overall configuration of such an IC test apparatus.

The IC test apparatus is roughly divided into a tester section 1 and an IC mounting apparatus 2. The tester unit 1 includes a control unit 11 and a test signal generation unit 1
2, a driver 13, a comparison circuit 14, a fail memory 15, and the like. There are various other components in the actual tester, but only the portions necessary for the description of the invention are shown in this specification.

The tester unit 1 and the IC mounting device 2 are connected by signal lines composed of a plurality of (m) coaxial cables or the like corresponding to the total number m of input / output terminals of the IC mounting device 2 to transmit various signals. It is supposed to do it. Although there are physically the same number of the signal lines as the total number m of the input / output terminals of the IC mounting device 2, the input signal lines and the output signal lines are shown separately for each function in the figure. .

One or a plurality of ICs to be measured 21 are mounted on the IC mounting device 2. The input / output terminal of the IC 21 to be measured and the input / output terminal of the IC mounting device 21 are connected in one-to-one correspondence. For example, if the number of IC21 to be measured
In the case of the IC mounting device 2 which can be mounted individually, it has 280 input / output terminals in total.

The control means 11 controls, operates and manages the entire IC test apparatus, and has a microprocessor configuration. Therefore, although not shown, the system includes a ROM for storing a system program, a RAM for storing various data, and the like.

The control means 11 performs various controls on the test signal generation means 12, reads out fail data as a test result from the fail memory 15, and performs various data processing.

The test signal generating means 12 is a predetermined test pattern signal (address signal AD1, data signal DATA, reference voltage signal Vo, etc.)
Is output to the driver 13, the comparison circuit 14, and the fail memory 15. The test signal generating means 12 outputs the same address signal AD1 to the address terminal of the IC 21 to be measured and the address terminal ADT1 of the fail memory 15 among the test pattern signals.

One driver 13 and one comparison circuit 14 are provided for each input / output terminal of the IC mounting device 2, and are connected by signal lines. Although only the operational amplifier is shown as the comparison circuit 14, the detailed configuration will be described later. When the number of input / output terminals of the IC mounting device 2 is m, the driver 13 and the comparison circuit 14 are each composed of m. However, when measuring a memory IC or the like, a comparison circuit may not be necessary for an address terminal, and thus the number of comparison circuits may be small.

The driver 13 responds to the test pattern signal from the test signal generator 12 by input / output terminals of the IC mounting device 2, that is, signal input terminals such as an address terminal, a data input terminal, a chip select terminal, and a write enable terminal of the IC 21 to be measured. A test signal is applied to the IC
Write to.

The comparison circuit 14 receives an analog output signal output from a signal output terminal such as a data output terminal of the IC under test 21 and compares it with the reference voltage Vo at the timing of the strobe signal from the control means 11. Is output to the data input terminal DI of the fail memory 15 as fail data FD.
At this time, since the same test signal as that at the time of writing the test pattern is applied to the address terminal of the IC 21 to be measured, the same test pattern as at the time of writing is output from the data output terminal, and this becomes fail data.

The fail memory 15 stores the fail data FD output from the comparison circuit 14, and is composed of a random-access RAM having a storage capacity similar to that of the IC 21 to be measured. The fail memory 15 has a data input terminal DI and a data output terminal DO fixedly corresponding to the data output terminal of the IC mounting device 2. For example, when the total number of input / output terminals of the IC mounting device 2 is 280, and 160 of them are data output terminals, the fail memory 15 stores the same or more data as the number of data output terminals. It is composed of a memory having an input terminal. The fail data stored in the fail memory 15 is read out by the control means 11 in the address order of the Tetus signal generating means 12, transferred to a data processing memory (not shown), and subjected to various data processing.

Next, FIG. 3 shows a configuration of the comparison circuit 14 corresponding to one output terminal of the IC mounting device.

The differential amplifier 31 is connected to the reference voltage Vo and the output signal of the IC 21 to be measured.
Compared with Vin, it is composed of load resistances Ra and Rb, field effect transistors (FETs) Fa and Fb, and a constant current source Iab. Measured at the gate of the field effect transistor Fa
The output signal Vin from the IC 21 is supplied as an input voltage, and the reference voltage Vo is supplied as an input voltage to the gate of the field effect transistor Fb. Load resistances Ra and Rb of the differential amplifier 31
Are output to the next-stage level shift circuit 32.

The level shift circuit 32 adjusts the output voltage of the differential amplifier 31 to the maximum input voltage of the next-stage A / D conversion circuit 33, and includes constant current sources Ic and Id, bipolar transistors Qc and Qd, and a resistor Rc. And Rd. Differential amplifier 31
The output voltage of the load resistor Ra is supplied to the base of the bipolar transistor Qc, the output voltage of the load resistor Rb is supplied to the base of the bipolar transistor Qd, and the level is shifted, and the A / D conversion is performed as the output voltage of the resistors Rc and Rd. Circuit 3
Output to 3.

The inverting input terminal of the A / D conversion circuit 33 receives the output voltage of the resistor Rc, the non-inverting input terminal receives the output voltage of the resistor Rd,
The result of comparing the two voltages is output.

Therefore, the A / D conversion circuit 33 outputs a logic signal of “1” or “0” depending on whether the output voltage Vin from the IC under test is higher or lower than the reference voltage Vo.

[Problems to be solved by the invention]

In the conventional IC test apparatus as shown in FIG. 2, since the output signal from the IC 21 to be measured is directly taken in the comparison circuit 14, the impedance as viewed from the IC 21 to be measured must be high. Therefore, as shown in FIG. 3, the comparison circuit has a high input impedance by using the field effect transistors Fa and Fb at the input terminals of the comparison circuit 14.

However, the field effect transistors Fa and Fb have a large input capacitance (capacitance). For example, assuming that the capacitance of the field effect transistors Fa and Fb is about 5 pF, the input capacitance is about 10 pF or more as a whole. Therefore, when the differential amplifier 31 is configured by the field-effect transistors Fa and Fb, the operating frequency limit is 50 MHz or less, the high-frequency characteristics are limited, and the comparator circuit cannot capture an accurate waveform. There is a problem that high-speed operation performance of 50 MHz or more cannot be tested on the IC under test.

The present invention has been made in view of the above points, and provides an IC test apparatus having a comparison circuit with a small input capacitance and excellent in high-speed response so that waveform acquisition can be accurately performed even in a high-speed operation performance test. The purpose is to:

[Means for Solving the Problems] The IC test apparatus of the present invention is configured by connecting a bipolar transistor, a resistor, and a constant current source in series, and shifts and outputs the level of the voltage input to the base of the bipolar transistor. A level shift circuit, a current amplifying circuit for changing an output voltage of a load resistor according to an output voltage of the level shift circuit, and a measurement voltage output from an IC to be measured, and a high frequency component of the measurement voltage is converted to the bipolar signal. A coupling capacitor to be supplied to the base of the transistor, the output voltage of the measurement voltage and the output voltage of the load resistor are input, and a voltage corresponding to a difference between these two voltages is output to the constant current source of the level shift circuit. An operational amplifier for controlling a current value of a current source; and an operational amplifier for changing the voltage of the operational amplifier in accordance with an output voltage of the level shift circuit. A power supply control bipolar transistor circuit for controlling a voltage, a bias resistance circuit for supplying an output voltage from the current amplifier circuit as a bias voltage to a base of the bipolar transistor of the level shift circuit, and an output voltage from the current amplifier circuit Is compared with a predetermined reference voltage to output a digital logic signal.

[Action]

Since the high-frequency component of the measured voltage of the IC under test is input to the bipolar transistor of the level shift circuit via the coupling capacitor, the level shift operation can be executed faster than the field-effect transistor. Waveform acquisition in a test can be performed accurately and easily.

Since the power supply voltage of the operational amplifier is controlled by the power supply control bipolar transistor so as to change in accordance with the output voltage of the level shift circuit, the power supply terminal and the ground terminal of the operational amplifier can be in a floating state. That is, since the power supply voltage of the operational amplifier changes following the measured voltage of the IC under test, it does not become grounded when viewed from the input side, so that the input capacitance becomes invisible and it is as if the input capacitance was reduced.

Also, the low frequency component (DC component) of the output voltage of the measured IC
Are cut off by the coupling capacitor and are not inputted to the base of the bipolar transistor of the level shift circuit, but are inputted to the operational amplifier. Therefore, during the DC test, the operational amplifier circuit compares the low-frequency component (DC component) of the output voltage of the IC under test with the output voltage from the current amplifier circuit, and adjusts the current of the constant current source so that the voltage difference between them becomes zero. Since the value is controlled, the test accuracy can be secured to the accuracy of the operational amplifier alone.

Furthermore, since the impedance viewed from the IC to be measured has a high input impedance due to the coupling capacitor and the operational amplifier, it is possible to achieve a high input impedance without using a field-effect transistor as in the related art.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing a configuration of a comparison circuit of an IC test apparatus according to one embodiment of the present invention.

This embodiment has a composite amplifier circuit configuration in which a circuit that operates with a high-frequency component in order to reduce the capacitance in a high-frequency region and a circuit that operates with a DC component in order to improve the test accuracy by the DC test are mixed. I have.

AC coupling capacitor C1 is the output voltage of IC21 to be measured
Vin is input, and only the high-frequency component is passed therethrough, and applied to the bases of the level shift transistors Q3 and Q4 of the level shift circuit 3 in the next stage.

The operational amplifier OP outputs the output voltage Vin of the IC under test 21 to the non-inverting input terminal and outputs the output voltage between the resistors R5 and R6 of the current amplifier circuit 4.
V56 is input to the inverting input terminal, and an output voltage corresponding to the voltage difference between the two terminals is supplied to the constant current sources I1 and I2 of the level shift circuit 3. The power supply voltage of the operational amplifier OP is given by the floating power supply transistors Q1 and Q2 in order to reduce the capacitance of the circuit input section.

The transistors Q1 and Q2 for the floating power supply input the voltage level-shifted by the zener diodes ZDZ and ZD2 for the operational amplifier bias of the level shift circuit 3 to drive the power supply voltage of the operational amplifier OP. That is, the floating power supply transistor Q1 applies a positive voltage + V to the power supply terminal of the operational amplifier OP, and the floating power supply transistor Q2 applies a negative voltage −V to the ground terminal of the operational amplifier OP, thereby bringing the operational amplifier OP into a floating state.

The level shift circuit 3 drives the bipolar transistors Q5 and Q6 of the current amplifier circuit 4 so that the voltage difference between the output voltage Vin and the output voltage V56 input to the operational amplifier OP becomes zero. It comprises I2, level shift transistors Q3 and Q4, resistors R3 and R4, and operational amplifier bias zener diodes ZD1 and ZD2.

The level shift transistors Q3 and Q4 input the high frequency component of the output voltage Vin passing through the AC coupling capacitor C to the base and are driven at high speed. The level shift transistors Q3 and Q4 are driven according to the output voltage V56 input via the bias resistor R1.

 The resistors R3 and R4 are level shift resistors.

The Zener diodes ZD1 and ZD2 are for further level-shifting the voltage that has been level-shifted by the resistors R3 and R4 to create a power supply for the operational amplifier OP.

The constant current sources I1 and I2 control the current value according to the output voltage of the operational amplifier OP.

The current amplifier circuit 4 includes load driving transistors Q5 and Q6,
The output voltage of the resistor R3 is supplied to the base of the load driving transistor Q5, and the output voltage of the resistor R4 is supplied to the base of the load driving transistor Q6. Therefore, the current amplifying circuit 4 amplifies the current according to the output voltages of the resistors R3 and R4 of the level shift circuit 3, and controls the output voltage V56 between the resistors R5 and R6.

The attenuator (1 / n ATT) 5 is an attenuator for adjusting the level of the output voltage V56 to the A / D conversion circuit 6 in the next stage, and is constituted by resistors R7 and R8, and according to the values of the resistors R7 and R8. 1 / n times the level conversion.

The inverting input terminal of the A / D conversion circuit 6 receives the output voltage of the attenuator 5, the non-inverting input terminal receives the reference voltage Vo, compares the two voltages, and outputs the result as a digital logic signal. . Therefore, the A / D conversion circuit 6 outputs a logic signal of "1" or "0" depending on whether the output voltage Vin from the IC under test 21 is higher or lower than the reference voltage Vo.

 Next, the circuit operation of this embodiment will be described.

First, an operation in a DC region such as a steady state of a pulse waveform will be described. When the output voltage Vin is direct current, the direct current component does not pass through the AC coupling capacitor C and is directly input to the non-inverting input terminal of the operational amplifier OP.

On the other hand, the output voltage V56 is input to the bases of the level shift transistors Q3 and Q4 of the level shift circuit 3 via the bias resistor R1, and at the same time, the output voltage V56 is also input to the inverting input terminal of the operational amplifier OP. Therefore, the operational amplifier O
P controls the current value of the constant current sources I1 and I2 according to the voltage difference between the output voltage Vin and the output voltage V56. Level shift circuit 3
Changes, the drive voltage of the load driving transistors Q5 and Q6 changes accordingly, and the output voltage V56 changes.

Further, the drive voltage of the level shift transistors Q3 and Q4 also changes according to the change of the output voltage V56. Thus, the operational amplifier OP controls the constant current sources I1 and I2 so that the voltage difference between the output voltage Vin and the output voltage V56 becomes zero.

Next, the operation in the high frequency region such as the rising and falling of the pulse waveform will be described.

The components that mainly operate with the high frequency component are the AC coupling capacitor C1 and the level shift transistors Q3 and Q4. Since the operational speed of the operational amplifier OP is low, the operational amplifier OP cannot follow the feedback operation in a high frequency region. However, the high frequency component is the AC coupling capacitor C
And are taken into the level shift transistors Q3 and Q4. The level shift transistors Q3 and Q4 perform level shift for each polarity so that the output voltage V56 becomes appropriate.

The voltage further level-shifted by the Zener diodes ZD1 and ZD2 is the floating power transistor Q1.
And Q2 to drive the floating power supply transistors Q1 and Q2, respectively. The floating power supply transistors Q1 and Q2 apply the power supply for the operational amplifier to the operational amplifier OP.

In this way, by following the waveform of the high-frequency component of the output voltage Vin, the power supply voltage of the operational amplifier OP is changed (the power supply of the operational amplifier is changed in the same manner as the change of the output voltage Vin), and the input terminal of the operational amplifier is changed. Can be reduced, and it is possible to capture the input waveform at a high frequency without adversely affecting the input waveform. The input capacitance is on the order of several pF, and waveform capture in high-speed tests is accurate.

〔The invention's effect〕

According to the present invention, it is possible to provide an IC test apparatus having a comparison circuit with a small input capacitance and excellent in high-speed response so that waveform acquisition can be accurately performed even in a high-speed operation performance test.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a detailed configuration of a comparison circuit of an IC test apparatus according to one embodiment of the present invention, FIG. 2 is a circuit diagram showing a schematic configuration of the entire IC test apparatus, and FIG. It is a block diagram showing an example of a comparison circuit of a test device. DESCRIPTION OF SYMBOLS 1 ... Tester part, 2 ... IC mounting device, 3 ... Level shift circuit, 4 ... Current amplifier circuit, 5 ... Attenuator, 6
... A / D conversion circuit, 11 ... Control means, 12 ... Test signal generation means, 13 ... Driver, 14 ... Comparison circuit, 15 ... Fail memory

Claims (3)

(57) [Claims] A level shift circuit configured by serially connecting a bipolar transistor, a resistor, and a constant current source, for shifting the level of a voltage input to the base of the bipolar transistor and outputting the output, and an output voltage of the level shift circuit A current amplifying circuit that changes the output voltage of the load resistor according to the following: a coupling capacitor that receives a measurement voltage output from the IC to be measured and supplies a high-frequency component of the measurement voltage to the base of the bipolar transistor; An operational amplifier that inputs a measurement voltage and an output voltage of the load resistor, outputs a voltage corresponding to a difference between the two voltages to the constant current source of the level shift circuit, and controls a current value of the constant current source; A power supply control bipolar for controlling a power supply voltage of the operational amplifier so as to change according to an output voltage of a level shift circuit A transistor circuit, a bias resistor circuit that supplies an output voltage from the current amplifier circuit as a bias voltage to a base of the bipolar transistor of the level shift circuit, and compares the output voltage from the current amplifier circuit with a predetermined reference voltage. And a circuit for outputting a digital logic signal. 2. A power supply control bipolar transistor circuit comprising: a zener diode for further level shifting the output voltage of the resistor of the level shift circuit; and supplying the voltage level-shifted by the zener diode to the power supply control bipolar transistor circuit. The IC test apparatus according to claim 1, wherein 3. The IC according to claim 1, wherein an output voltage from said current amplification circuit is attenuated by an attenuator.
Testing equipment.