JP2608187B2 - Pattern feature extraction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a feature pattern obtained by applying a feature extraction function to an input pattern.
The present invention relates to a pattern feature extraction device configured to extract, as a pattern feature, a feature order in which level orders of local maximum values at local maximum points are summarized and a rank sequence in which evaluation levels corresponding to the respective feature points are summarized.

The obtained pattern features are used for pattern recognition of figures.

[0003]

2. Description of the Related Art Conventionally, in a pattern recognition device,
Many inventions have been made for feature extraction. However, in the conventional case, few satisfy the following conditions.
That is,

(1) It is possible to appropriately change the value of a feature or not to change the value of a feature in response to deformation of a graphic pattern.得 る The same feature value is obtained for the deformation of the figure pattern, and the deformed figure pattern is regarded as the same figure pattern. On the contrary, the feature value is expanded for the slight deformation. It can be differentiated.

(2) A ranking is given to features that are superior as features, and selection can be made from the superior features. ──
(4) By assigning superiority to features and extracting features in order from superior features, feature extraction time can be reduced and the amount of feature information can be compressed.

(3) The relationship between features can be extracted.
(4) Using feature points as mediation elements, it is possible to extract relevance between features.

(4) The symmetry of a graphic pattern can be extracted. (4) It is relatively difficult to find the symmetry of a graphic pattern, but it is desirable to extract features that cause a unique pattern to appear when the pattern has symmetry.

(5) Various features can be easily extracted. (4) For example, various evaluation functions are prepared for a characteristic pattern obtained by applying a certain characteristic function, and various characteristics can be extracted by a combination of the characteristic function and the evaluation function.

[0009]

It is desirable to prepare various evaluation functions for a feature pattern resulting from the application of a feature function, and to extract features in a form that matches various usage modes. .

An object of the present invention is to extract features in a form suitable for various use modes in the form of a feature rank and a rank sequence.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention. Reference numeral 1 in the figure denotes a feature extraction function processing mechanism, which applies an extraction function for contour extraction to a given input pattern (same as a graphic pattern). Of course, various extraction functions can be applied.

Reference numeral 2 denotes a maximum point group feature pattern extraction mechanism, which has a maximum point extraction mechanism 3 and a feature point extraction mechanism 4.

The maximum point extracting mechanism 3 performs a process of sequentially decreasing the threshold level of the characteristic pattern obtained by applying the characteristic function, and determines one or a plurality of maximum point positions in the characteristic pattern.

The feature point extracting mechanism 4 checks a feature point value (maximum value) for each position in the feature pattern corresponding to the maximum point position determined by the maximum point extracting mechanism 3, and for example, determines the level of each maximum value. Are obtained in this order.

Reference numeral 5 denotes an evaluation extracting mechanism, which obtains an evaluation function pattern by applying an appropriately given evaluation function to an input pattern, and obtains a maximum point sequence (maximum point pattern) obtained by the maximum point extracting mechanism 3. ), An evaluation level (feature point evaluation level) of an evaluation function pattern corresponding to each local maximum point position is obtained.

Reference numeral 6 denotes a rank sequence extraction mechanism, which associates a feature point pattern with a feature point evaluation level, for example, a feature rank arranged in descending order of a feature point value (maximum value), and a feature rank of the feature rank. A rank sequence in which evaluation levels of the respective feature points arranged in order are summarized in a sequence is obtained.

[0017]

The function values obtained when the feature patterns obtained by the feature extraction function processing mechanism 1 are arranged in one dimension, for example,
It is assumed that the local maximum point extracting mechanism 3 has extracted the local maximum point position. The feature point extracting mechanism 4 extracts a feature point value (maximum value) of a feature pattern for each local maximum point, and obtains, for example, a feature point pattern arranged in descending order of local maximum value (including local maximum point position information). .

Assuming that the feature point patterns are in the order of (1,2,3,4,5,6,7), for example, in the order of the magnitude of the level, the rank sequence extracting mechanism 6 according to the present invention (1, 2, 3, 4, 5, 6, 7) is obtained as the feature ranking.

On the other hand, the evaluation extraction mechanism 5 obtains an evaluation function pattern as a result of applying an evaluation function to the input pattern, and then, based on the maximum point sequence (maximum point pattern) from the maximum point extraction mechanism 3. Then, an evaluation level for each local maximum point (evaluation level corresponding to a feature point─a feature point evaluation level) is obtained.

The feature point evaluation levels correspond to, for example, (feature ranks) 1, 2, 3, 4, 5, 6, 7, and (evaluation levels) 7, 2, 5, 3, 6, respectively. Assuming that the rank sequence is 4,1, the rank sequence extracting mechanism 6 calculates the feature rank (1,2,3,4,5,6,7) and the rank sequence (7,2,5,3,6,4,1) Are obtained as pattern features.

The feature rank at this time is obtained by calculating a feature point value (maximum value) for each local maximum point of the feature pattern as a result of applying a certain feature extraction function (for example, a contour extraction function) to the input pattern. Give ranking.

Also, the rank sequence is given by:
The evaluation level as a result of applying a certain evaluation function is given in the form of a numerical sequence as to what level value is at each local maximum point. As described above, the result of applying the feature extraction function
The dimension is different from the result of the evaluation function.
Are the two that processed the input pattern. this thing
Has the following advantages. (A) New information is obtained. That is, a feature extraction function is created.
The individual information of the result used and the result of applying the evaluation function
Not only individual information but also information combining both can be obtained.
You. (B) Information association is obtained. That is, the feature extraction function
Of the evaluation function at the point obtained by applying
And, for example, the points obtained by operating the feature extraction function
Can be evaluated. (C) The selected information is obtained. That is, the feature extraction function
Focusing on the maximum point as a result of applying
The main point is that the evaluation function
(Coordinate position) can be narrowed down to information only. (D) The number of new information increases. That is, the same as (a) above
In short, the information available for pattern recognition
The number of reports increases.

[0023]

FIG. 2 is a diagram for explaining pattern features. It is assumed that the characteristic pattern obtained in FIG. 1 has a value that changes according to the position as shown in the upper part of FIG. In the illustrated case, the feature point value has a plurality of maximum values.

The threshold value (indicated by a dotted line in the figure) is sequentially lowered for such a characteristic pattern, and a value "1" is given because only one maximum point which is equal to or higher than the threshold value first appears below the threshold value. Since there are two local maxima that appear below the next lower threshold value, a value “2” is given to the local maximal point that appears at that time, and so on. Then, the result is obtained as the feature rank (1, 2, 3, 4, 5, 6, 7).

On the other hand, the evaluation extraction mechanism 5 in FIG. 1 obtains an evaluation function pattern obtained by applying a certain evaluation function to an input pattern. The evaluation function pattern is shifted downward in FIG. It has a value that changes as shown.

The evaluation level of each of the local maximum points in the evaluation function pattern is (i) a level “3” corresponding to the local maximum point having the value “4”, and (ii) a local maximum point having the value “3”. Corresponding to the level “5”, (iii) corresponding to the local maximum having the value “6”, level “4”,..., (Vii) corresponding to the local maximum having the value “7”, the level “ 1 ”, the rank sequence is associated with the feature sequence, and the feature sequence (1,2,3,4,5,6,7) rank sequence (7,2,5,3,6,4,4) 1) is obtained.

The evaluation level value is, for example, the evaluation level corresponding to the maximum point having the value "5" in the upper drawing of FIG. 2 in the lower drawing of FIG. 2, as indicated by the dotted line in the lower drawing of FIG. , One threshold value, and is given by how many local maximum points have an evaluation level exceeding the threshold value. That is, the value "6" is given because there are six local maximum points having an evaluation level larger than the dotted line in the case of the lower diagram of FIG.

FIG. 3 is a diagram for explaining the feature extraction function processing mechanism in FIG. 1, and reference numerals correspond to those in FIG. An input pattern f (x) is input, and a certain predetermined feature extraction function,
For example, a feature pattern g resulting from applying the contour extraction function
(x) is output.

[0029]

(Equation 1)

(Equation 2)

Equation (1) shows an example of the contour extraction function, and the function U in equation (1) is given by equation (2). In the expressions (1) and (2), x represents a position function, f (x) represents an input pattern, and α and λ represent coefficients, respectively. Equation (1) is a function for assuming that a contour exists when the difference between the values of the function U when the blur coefficient a slightly differs is equal to or larger than a predetermined threshold.

FIG. 4 is an overall configuration diagram of the maximum point extracting mechanism. In the figure, reference numeral 7 denotes a maximum point extracting circuit, and 8 denotes a maximum point number extracting circuit.

FIG. 5 is a diagram for explaining the overall relationship of the local maximum point extracting circuit. FIG. 6 is an overall block diagram of the local maximum point extracting circuit. FIG. 7 is an input / output diagram of a one-point circuit constituting the local maximum point extracting circuit. FIG. 8 is a diagram for explaining the relationship.
It is a specific block diagram of a point circuit.

As shown in FIG. 4, the characteristic pattern values corresponding to a plurality of points (two-dimensional points) are input to the local maximum point extracting circuit 7 in parallel to perform the parallel processing. The maximum point extracting circuit 7 is provided with a threshold value V _th for finding the maximum point and an instruction signal (input pattern set) P _st for setting an input pattern, as shown in FIG.
Extract the maximum point pattern from the input pattern.

In the maximum point extracting circuit 7, one-point circuits 9 as shown in FIG. 8 are arranged in a matrix as shown in FIG. That is, each one-point circuit 9 receives an input value I _ij corresponding to a certain point (two-dimensional point) and generates an output value P _ij corresponding to the one point. At this time, the output P _{(i −1), j} , the output P _{i, (j + 1)} , the output P _{(i −1), j} from the other one-point circuit 9 located on the two-dimensional plane, at the top, bottom, left, and right P
_{(i + 1), j} and the output P _{i, (j-1)} are supplied.

That is, the input value I _{i, j} to the self and the output value P _{(i-1), j} from the adjacent position are compared, and the self output value P _{i, j} is generated based on the result. V _th is a threshold value for finding a local maximum value, and P _st is an input pattern set.

If the feature pattern g (x) has a value that changes according to the position as shown in FIG. 9 (one-dimensionally described in FIG. 9), the threshold value V _th Are sequentially reduced from the maximum value, and a position having a value exceeding the threshold value _Vth is determined as one of the maximum points. In the case of FIG. 9, it is assumed that the maximum point exists in a range exceeding the threshold value _Vth (the position indicated by oblique lines). Illustration a
Maximum point in the range of, which threshold V _th is already extracted in the a value (V _th + △), maximum point in the range shown b was first extracted in the threshold V _th However, as shown in FIG. 10, the maximum point at the threshold _Vth is 2
Is extracted. In the illustrated ranges a and b,
The detection of the position where the maximum point exists is processed as follows.

For example, the values of the feature patterns at a plurality of positions in the range b are compared, and if the values of all surrounding points are smaller, the corresponding point is determined to be the maximum point. If there is a larger value in surrounding points, the corresponding point is determined not to be a maximum point. Then, if there is a point having the same value in the surrounding points, the value of the corresponding point is output as it is (neither the process of determining the local maximum point nor the process of determining that it is not the local maximum point). By performing such processing, the range b
The position of the maximum point within is determined.

FIGS. 5 to 8 show a configuration for performing such processing. P _{(i-1), j} and P in FIGS. 7 and 8
_{(i + 1), j} , P _{i, (j−1)} and P _{i, (j + 1)} are outputs from the adjacent one-point circuit 9.

In FIG. 8, the self point (point on two dimensions)
(i, j) values I _i of the feature pattern g in) _(x), the _j is the signal P _st, a value is taken into the capacitor C ₁ (charging voltage of the capacitor C ₁ is corresponding to the value I _ij) .

The voltage of the capacitor C ₁ is
The output P _{(i-1), j} from the point circuit and the comparator IC
₁ to be compared in IC _4. In addition, the threshold V _th the given one (e.g. the threshold V _th shown in FIG. 9), are compared by the comparator IC _5.

The voltage (I _{i, j} ) of the capacitor C ₁ becomes (1)
If it is less than or equal to the threshold value _Vth , or (2) it is smaller than the output from the adjacent one-point circuit, the OR circuit IC
₇ Output logic "1", the transistor TR ₃ is turned on, the voltage of the capacitor C ₁ is dropped to the ground potential.
That is, the output P _{i, j} of the one-point circuit 9 is dropped to zero potential. Furthermore, it is not the maximum point.

If all the outputs from the adjacent one-point circuits are smaller than the voltage (I _{i, j} ) of the capacitor C ₁ , the negative input AND circuit turns on and the transistor TR ₂ turns on. and, the voltage of the capacitor C ₁ is set to the voltage V ₁ of the illustrated battery. That is to voltages V ₁ corresponding to the maximum point.

The condition that the voltage (I _{i, j} ) of the capacitor C ₁ does not exceed the threshold value V _th and there is no output larger than one of the outputs from the adjacent one-point circuits;
Under the condition that all the outputs from the adjacent one-point circuits are not smaller, it is impossible to determine whether the corresponding point is a local maximum point, and neither the transistor TR ₂ nor the transistor TR ₃ is turned on. voltage of the capacitor C ₁ will remain equivalent to I _{i, j,} the output P _{i, j}
Becomes I _{i, j} .

The processing shown in FIG. 8, performed in every 1-point circuit 9 in FIG. 6, the output P _{i, j} is the maximum point at the position indicating the voltages V ₁ is determined. That is, as shown in FIG. 10, the position of each local maximum point is determined (under a certain threshold).

FIG. 11 shows the structure of the maximum point extraction circuit shown in FIG. The output representing the voltage V ₁ from each one-point circuit 9 shown in FIG. 7 is added in an analog manner, converted to a digital value via an AD converter, and converted to a maximum value under a certain threshold value V _th. (For example, two as shown in FIG. 10).

As described above, the local maximum point positions are extracted. However, it is necessary to extract the characteristic point value (local maximum value) at each local maximum point position. The feature point extraction mechanism 4 shown in FIG. 1 performs this extraction.

FIGS. 12 to 16 are diagrams for explaining the processing mode of the feature point extracting mechanism.

Assume that the characteristic pattern changes depending on the position as shown in FIG. FIG. 12 is the same as FIG. When the threshold value is V _th + △, the range a as shown in FIG.
It turned out that one of the maximum points existed within. Then, between the threshold value V _th + △ and the threshold value V _th , one of the maximum points that will be present in the range b is found as shown in FIG. However, the range a 'shown in FIG. 14 is also found, but since the maximum point in the range a' has already been found as being in the range a shown in FIG. 13, it must be ignored. There is. FIG. 15 shows the ignored state.

In the ignoring process, it suffices to take AND logic between the state of FIG. 13 and the state of FIG. 14 and delete the part where the logic becomes "1". However, the range a 'shown is somewhat wider than the range a. This complicates the process somewhat.

FIGS. 17 and 18 show that, as shown in FIG.
It shows a circuit configuration for finding a maximum point in a range b found between the threshold value V _th + △ and the threshold value V _th . That is, FIG.
As shown in FIG. 6, a circuit configuration for finding one maximum point is shown.

In FIG. 17, a certain threshold value V_thUnder
The threshold value V_thOutput value P greater than _{i, j}1 point with
Circuit 9 is extracted. One point with a larger output value
Output value P_ijIs the output value as it is
P_thijBecomes However, the threshold V_thOutput value P smaller than
_ijOutput value P from the one-point circuit 9 having_thijIs zero
You.

FIG. 18 shows that (1) one maximum point is extracted in the range b shown in FIG. 14, and (2) the maximum point is not extracted in the range a 'shown in FIG. 3 shows a point extraction circuit configuration.

Reference symbols IH _{(i-1), j and the} like are inhibit signals given from an adjacent one-point circuit, and represent the range a shown in FIG. 13 and the AND logic of FIG. 13 and FIG. This is a signal that is output when it is determined that both the undesired remaining range and the undesired range should be deleted.

From each one-point circuit within the range b in FIG. 14, a logic "1" is output as the inhibit signal IH.
Does not occur. For this reason, the illustrated output PP _{i, j} emits a logic “1” from each one-point circuit within the range b. Further, in the one-point circuit within the range that is undesirably left based on the difference between the width a 'and the width a, the inhibit signal IH is supplied from one of the adjacent one-point circuits. Thus the illustrated AND circuit IC ₂ is logic "1", the OR circuit IC ₃ will be a logic "1". In the one-point circuit within the range a shown in FIG.
Since the signal P _th + △ is logic “1”, the OR circuit IC
₃ becomes logic "1". That is, the inhibit signal IHi _{, j} is output as logic "1" from the one-point circuit within the range a 'shown in FIG. 14, and is erased as shown in FIG.

FIG. 19 shows a configuration for extracting a feature point value (maximum value). That is, as shown in FIG. 16, there is shown a configuration in which a feature point value at one local maximum point can be extracted.

[0056] The configuration of FIG. 19 is an equivalent circuit configuration as in FIG. 8, found maximum point within a range b of FIG. 15, the operation to set the value of the maximum point to voltages V ₁ I do. Of course, if there is another maximum point, the output P △
_{Set ij} to zero potential. Since further detailed explanation can be understood by analogy with FIG. 8, it will be omitted.

FIG. 20 shows the entire configuration of the evaluation extracting mechanism.
Reference numeral 10 in the figure denotes an evaluation function processing mechanism, which applies an arbitrary desired evaluation function to an input pattern.
Obtain the evaluation function pattern.

Reference numeral 11 denotes an evaluation level extraction processing mechanism which examines the obtained evaluation function pattern and determines the evaluation level (feature point evaluation level) for each of the maximum points obtained as described above. Extract.

FIGS. 21 to 25 are diagrams for explaining the manner in which the rank sequence is extracted based on the feature point evaluation level.

As shown in FIGS. 21 to 23, it is assumed that a local maximum point having a value "5" is selected. The evaluation level corresponding to the maximum point is set as a threshold (dotted line in FIG. 24) as shown in FIG. 24, and the number of the maximum points shown in FIG. 21 having an evaluation level equal to or higher than the threshold is examined.
In the case of FIG. 24, it is found that there are six, and the evaluation level corresponding to the local maximum point to which the above-mentioned value “5” is assigned is the value “6”. FIG. 25 shows a state in which the presence of the six items is extracted.

FIG. 26 shows the evaluation level for each maximum point.
The circuit configuration to be obtained will be described. Signal P in the figure _ijIs the output shown in FIG.
Force, signal H_ijIs the evaluation function at point (i, j)
Value (evaluation level). One point shown in FIG.
Points which are shown to be the maximum points in the group of
The evaluation level at (i, j) is K_ijExtracted as
You. The result is as shown in the bar graph in FIG.
You.

FIG. 27 shows a configuration of a threshold level extracting circuit for determining the threshold shown in FIG. 24 in the rank sequence extracting mechanism.
In the figure, reference numeral 12 denotes a threshold level extraction circuit, and reference numeral 13 denotes a minimum value detection unit. The processing shown in FIGS. 12 to 16 as the minimum value signal △ LEVEL of first appeared maximum point (typically several) evaluation level indicated value between the threshold value V _th + △ and the threshold V _th Is detected. That is, in the example of FIG. 24, the levels of the threshold values (illustrated dotted lines) shown in FIG. 24 are extracted.

FIG. 28 shows a rank number extraction circuit for extracting the number shown in FIG. 25 in the rank sequence extraction mechanism. The evaluation level K _ij obtained from the circuit configuration for obtaining the evaluation level shown in FIG. 26 and the signal △ LEVEL obtained in FIG.
And an evaluation level K larger than the signal △ LEVEL
The output of the one having _ij is output as the value "1". Then, the value "1" is added, and the number information is obtained via the AD converter. The number information corresponds to the number of bar lines shown in FIG. 25 and corresponds to the value “6” shown in FIG. This is used as the rank number.

As described above, the feature rank and rank sequence described with reference to FIG. 2 are obtained. Needless to say, it is obtained for each feature extraction function and for each evaluation function.

FIG. 29 shows a feature rank and a rank sequence corresponding to a repetitive pattern (a figure pattern is repeated). In the case of a repetitive pattern, the characteristic pattern appears repeatedly as shown in the upper part of the figure, and the evaluation function pattern corresponding to each pattern also appears repeatedly as shown in the lower part of the figure. As shown in the figure, in the case of four repetitions, each element of the rank sequence takes a multiple value of four. As a result, it can be seen that a pattern feature capable of expressing the existence of the repetitive pattern is obtained.

FIG. 30 shows a feature rank and a rank sequence corresponding to a symmetric pattern (a figure pattern is symmetric). In the case of a symmetric pattern, it can be seen that each element of the rank sequence takes a multiple of two. Thus, it can be seen that a pattern feature that can express the existence of the symmetric pattern is obtained.

FIG. 31 shows an example of a configuration in which a plurality of feature functions are applied. In FIG. 31, reference numeral 1-i denotes a feature function processing mechanism, which corresponds to reference numeral 1 in FIG.
Although specific embodiments of the present invention have been described in detail, the present invention is not limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course there is. For example, in a mechanism equipped with a processor and a memory, the functions of the present invention were realized by a program to reduce the price.
How to extract the rank sequence. In a mechanism equipped with a processor and a memory, a method of partially extracting a maximum point extraction circuit and a rank sequence by a program to achieve high-speed hardware and low-cost software. In the embodiment of the present invention, a circuit for converting the analog level value into a voltage value is used. However, a method for extracting a rank sequence by a signal corresponding to the pulse modulation and a circuit corresponding to the pulse modulation.

FIG. 32 shows an example of a configuration in which a plurality of evaluation functions are applied. Reference numerals 5-i in FIG. 32 denote evaluation extraction mechanisms, respectively, and correspond to reference numeral 5 in FIG.

[0069]

As described above, according to the present invention, pattern features satisfying the conditions (1) to (5) described in the section of the prior art can be obtained.

For example, regarding the deformation of the input pattern, if the rank sequence for the input pattern f (x) is γ and the rank sequence for the input pattern f ′ (x) is γ ′, then f ′ ( If x) = f (x + X), then γ '= γ, and if it corresponds to scaling, if f' (x) = f (Ax), then γ '= γ, If f '(x) = Bf (x) in the case of magnitude relation, γ' = γ.

Furthermore, if the number of elements in the obtained rank sequence is limited, the number of figures classified into the same category as having the same pattern feature becomes large, and only the more superior features are used. Classification is also possible.

Of course, even when the same feature function is applied, finer classification can be performed by using different evaluation functions.

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a diagram illustrating pattern features.

FIG. 3 is a diagram illustrating a feature extraction function processing mechanism.

FIG. 4 is an overall configuration diagram of a local maximum point extracting mechanism.

FIG. 5 is an overall configuration diagram of a local maximum point extraction circuit.

FIG. 6 is an overall block diagram of a local maximum point extraction circuit.

FIG. 7 is a diagram illustrating an input / output relationship in a one-point circuit constituting a local maximum point extracting circuit.

FIG. 8 is a specific configuration diagram of a one-point circuit.

FIG. 9 is a diagram illustrating a maximum point extraction mode.

FIG. 10 is a diagram illustrating a local maximum point extraction mode.

FIG. 11 shows a configuration of a maximum point extraction circuit.

FIG. 12 is a diagram illustrating a processing mode of a feature point extraction mechanism.

FIG. 13 is a diagram illustrating a processing mode of a feature point extraction mechanism.

FIG. 14 is a diagram illustrating a processing mode of a feature point extraction mechanism.

FIG. 15 is a diagram illustrating a processing mode of a feature point extraction mechanism.

FIG. 16 is a diagram illustrating a processing mode of a feature point extraction mechanism.

FIG. 17 is a circuit for obtaining an output exceeding a threshold value V _th .

FIG. 18 shows a configuration of a maximum point extracting circuit.

FIG. 19 shows a configuration for extracting a feature point value.

FIG. 20 shows an overall configuration of an evaluation extraction mechanism.

FIG. 21 is a diagram illustrating a manner in which a rank sequence is extracted.

FIG. 22 is a diagram illustrating a manner in which a rank sequence is extracted.

FIG. 23 is a diagram illustrating a manner in which a rank sequence is extracted.

FIG. 24 is a diagram illustrating a manner in which a rank sequence is extracted.

FIG. 25 is a diagram illustrating a manner in which a rank sequence is extracted.

FIG. 26 shows a circuit configuration for obtaining an evaluation level for each maximum point.

FIG. 27 shows a configuration of a threshold level extraction circuit.

FIG. 28 shows a rank number extraction circuit.

FIG. 29 shows an example of a repeating pattern.

FIG. 30 shows an example of a symmetric pattern.

FIG. 31 shows a configuration example when a plurality of feature functions are applied.

FIG. 32 shows a configuration example when a plurality of evaluation functions are applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Feature extraction function processing mechanism 2 Maximum point cloud feature pattern extraction mechanism 3 Maximum point extraction mechanism 4 Feature point extraction mechanism 5 Evaluation extraction mechanism 6 Rank sequence extraction mechanism 9 1 point circuit

Claims (1)

(57) [Claims] 1. A pattern feature extraction apparatus for extracting pattern features of the pattern of the figure, from the feature pattern of the obtained pattern was characterized by a pattern based on each of the single or plurality of feature extraction functions, such and each of the local maximum points in the feature pattern and maximum value and the local maximum point group feature pattern extraction mechanism for extracting (2), for the input pattern imparted, the evaluation function pattern of results of the evaluation function processing given An extraction and extraction mechanism (5) that extracts and calculates a feature point evaluation level corresponding to each of the maximum points based on the evaluation function pattern and the respective maximum points, and an extraction and extraction mechanism (5) The characteristic points characterized by the local maximum points at the respective local maximum values extracted from 2).
And patterns, based on the evaluation level corresponding to each feature point calculated by the evaluation extraction mechanism (5), and level ranking the combined features ranking for each of the feature points, respectively feature points and charts sequence summarizes the evaluation level corresponding to, be equipped with a ranking sequence extraction mechanism (6) for generating, and characterized in that the said characteristic rank and the ranking sequence was extracted as the pattern feature Pattern feature extraction device.