JP2607312Y2 - Encoder - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder and, more particularly, to a novel improvement for reducing the number of cables compared to the conventional one by using two cables for connecting the inside of the encoder and the controller.

[0002]

2. Description of the Related Art As this type of encoder conventionally used, generally, as disclosed in Japanese Patent Application Laid-Open No. 62-278408, a cable connecting between the inside of the encoder and the controller side is constituted by: In order to transmit the request signal and the serial data on separate lines, four lines are used.

[0003]

[Problems to be solved by the invention] Conventional encoders
Because of the above configuration, the following problems exist. That is, for example, in an NC device or the like,
Since the number of cables connecting the inside of the encoder and the controller side is four, the cost and routing of the cable are not easy, and when many encoders are assembled in one device, the work and cost are extremely large. Needed and was a major obstacle.

The present invention has been made to solve the above problems, and in particular, has two cables for connecting the inside of the encoder and the controller, so that the number of cables is reduced as compared with the related art. It is intended to provide an encoder.

[0005]

An encoder according to the present invention includes an encoder inside for generating an encoder signal from an encoder data detector, and a second request recognition circuit and a reception recognition circuit connected to the inside of the encoder via a cable. A first switching buffer circuit provided inside the encoder and connected to a first receiving circuit and a first transmitting circuit, and an encoder connected to the first receiving circuit and the first switching buffer circuit. A first request recognition circuit, a second switching buffer circuit and a second transmission circuit connected to the second request recognition circuit, and a second reception circuit connected to the second switching buffer circuit and the reception recognition circuit. The encoder is in a normal reception (input) mode, and the controller side has a request (Output) mode, in which the request signal and the serial data are transmitted and received between the respective switch buffer circuits by using the dual cable, and the request signal is transmitted through the second request recognition circuit to the second switch buffer. Circuit, the request signal is sent to a first switching buffer circuit via a cable, a first request recognition circuit recognizes the request signal via the first receiving circuit, and the first transmission circuit operates. Then, the encoder signal is output as parallel data output from the second receiving circuit via the second switching buffer circuit as serial data.

[0006]

The encoder according to the present invention has two cables for connecting the inside of the encoder and the controller, and the request signal and the serial data transmitted between the switching buffers are transmitted and received through the two cables. However, the number of the components is half of the conventional one, and the configuration when the encoder is mounted can be greatly reduced.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the encoder according to the present invention will be described below in detail with reference to the drawings. In FIG. 1, reference numeral 1 denotes an encoder data detection unit of an encoder. An encoder signal 1a from the encoder data detection unit 1 is input to an encoder interior 2, and the encoder interior 2 is connected to a controller via a cable 3. 4
Interconnected.

The encoder interior 2 includes a first receiving circuit 5, a first transmitting circuit 6, a first switching buffer circuit 7 connected to each of the circuits 5, 6, and the first receiving circuit 5 and the first receiving circuit 5.
And a first request recognition circuit 8 connected to the switching buffer circuit 7.

The controller 4 includes a second request recognition circuit 1 connected to a second switching buffer circuit 10.
1, a second transmission circuit 12, a second reception circuit 13, and a reception recognition circuit 14. The second reception circuit 13 is configured to obtain a parallel data output 13a.

Therefore, in the above-described configuration, the inside of the encoder 2 is in the normal reception (input) mode, and the controller 4 (reception IC) is in the request (output) mode. Therefore, when the request signal 11a is sent to the second switching buffer circuit 10 via the second request recognition circuit 11 of the controller 4, the request signal 11a is sent to the first switching buffer circuit 7 via the cable 3, and 1st request recognition circuit 8 via 1 receiving circuit 5
Is recognized, the first transmission circuit 6 operates, and the encoder signal 1a is output as serial data 3a from the second reception circuit 13 via the second switching buffer circuit 10 as a parallel data output 13a. That is, the request signal 1
1a and serial data 3a are transmitted and received and transmitted using the cable 3 as well.

[0011]

Since the encoder according to the present invention is configured as described above, the following effects can be obtained. That is, since the request signal and the serial data can be transmitted by using the two-structured cable, the setting of the encoder inside and the controller side of the NC device is remarkably easy as compared with the conventional four-structured cable. Can be

[Brief description of the drawings]

FIG. 1 is a block diagram showing an encoder according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Encoder data detection part 1a Encoder signal 2 Encoder inside 3 Cable 4 Controller side 5 First receiving circuit 6 First transmitting circuit 7 First switching buffer circuit 8 Request recognition circuit 10 Second switching buffer circuit 11 Second request recognition circuit 12th 2 transmission circuit 13 2nd reception circuit 14 reception recognition circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-172203 (JP, A) JP-A-60-24750 (JP, A) Kota Kuroda, Introduction to pictorial book Data communication Basic knowledge of information and communication, Tokyo Electric University Press, March 20, 1988, p. 100 (2) Half duplex (58) Field surveyed (Int. Cl. ⁷ , DB name) G01D 5/00-5/62

Claims (1)

(57) [Scope of request for utility model registration] An encoder internal (2) for generating an encoder signal (1a) from an encoder data detector (1), and a second encoder (2) connected to the encoder internal (2) via a cable (3).
In an encoder including a request recognition circuit (11) and a controller (4) having a reception recognition circuit (14), a first reception circuit (5) and a first transmission circuit (6) provided inside the encoder (2) are provided. ) Connected to the first switching buffer circuit (7)
And the first receiving circuit (5) and the first switching buffer circuit
A first request recognition circuit (8) connected to (7), a second switching buffer circuit (10) and a second transmission circuit (12) connected to the second request recognition circuit (11), 2 switching buffer circuit (10) and a second reception circuit (13) connected to the reception recognition circuit (14), wherein the encoder internal (2)
Is the normal reception (input) mode, and the controller side (4)
Is a request (output) mode, in which the request signal (11a) and the serial data (3a) are transmitted and received between the switching buffer circuits (7, 10) by using the cable (3) having two components. The request signal (11a) is transmitted to the second switching buffer circuit (10) through the second request recognition circuit (11).
The request signal (11a) is sent to the cable (3).
To the first switching buffer circuit (7), the first request recognition circuit (8) recognizes the request signal (11a) through the first receiving circuit (5), and the first transmission circuit (6)
Is activated and the encoder signal (1a) is converted to serial data (3
The encoder according to claim 1, wherein a) is output as a parallel data output (13a) from the second receiving circuit (13) via the second switching buffer circuit (10) as a).