JP2606905B2 - IC lead member - Google Patents
IC lead memberInfo
- Publication number
- JP2606905B2 JP2606905B2 JP24716888A JP24716888A JP2606905B2 JP 2606905 B2 JP2606905 B2 JP 2606905B2 JP 24716888 A JP24716888 A JP 24716888A JP 24716888 A JP24716888 A JP 24716888A JP 2606905 B2 JP2606905 B2 JP 2606905B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- insulating layer
- thickness
- substrate
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 17
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- 239000011888 foil Substances 0.000 claims description 9
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 3
- 229910003271 Ni-Fe Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910000640 Fe alloy Inorganic materials 0.000 description 2
- 229920000954 Polyglycolide Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 235000010409 propane-1,2-diol alginate Nutrition 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910000851 Alloy steel Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910001566 austenite Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000004841 bisphenol A epoxy resin Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000009864 tensile test Methods 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ICリード用部材に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC lead member.
従来、ICリード用部材としては42％Ni−Fe合金、各種
Cu合金等が主に用いられており、スタンピングやエッチ
ング加工により所定のリードフレーム形状に成形されて
いた。Conventionally, 42% Ni-Fe alloy and various
Cu alloys and the like are mainly used, and are formed into a predetermined lead frame shape by stamping or etching.
しかしながら、近年のICの高集積化にともないリード
用部材に対して多ピン化、高密度実装化の要求が強まる
中、これまでのような単一材のリードフレーム材ではリ
ードフレーム材自体の厚さのために微細加工も限界に達
し、リードフレーム板厚よりも狭い幅のリード加工は困
難となってきた。However, with the recent increase in the number of pins and the need for high-density mounting for lead members due to the high integration of ICs, the thickness of the lead frame material itself has not been increased with a single lead frame material as in the past. Therefore, fine processing has reached its limit, and it has become difficult to process leads having a width smaller than the thickness of the lead frame.
また、ある程度以上の微細加工を行なうとリード強度
劣化によるリード位置ずれ、変形が発生しボンディング
不良を引き起こすという問題を有していた。Further, if the fine processing is performed to a certain degree or more, there is a problem that a lead position shift and a deformation due to the deterioration of the lead strength are caused to cause a bonding failure.
多ピン化対応のパッケージ技術としては、多数のリー
ドピンをバッケージ下面に配したPGA（Pin Grid Arra
y）や、絶縁テープ上に金属箔リードを配したTAB（Tape
Autmated Bonding）などが知られている。As a package technology supporting multiple pins, PGA (Pin Grid Arra) with many lead pins arranged on the lower surface of the package
y) or TAB (Tape) with metal foil leads on insulating tape
Autmated Bonding) is known.
しかしながら、ピン装入型であるPGAは高密度実装に
限界が有り、また通常のセラミックスPGAは熱放散性不
良、高価格といった問題を有する。また、熱放散性改
善、低価格化を狙ったプラスチックPGAでは耐湿性が劣
化してしまう。However, pin-mounted PGAs have a limit in high-density mounting, and ordinary ceramic PGAs have problems such as poor heat dissipation and high cost. In addition, the moisture resistance of a plastic PGA that aims to improve heat dissipation and reduce cost is degraded.
TABはリード部が箔で形成されているためエッチング
による微細加工が可能であるが、絶縁テープの伸縮によ
るリード位置精度の低下ならびに耐湿信頼性に欠けると
いった欠点を有している。TAB, which has a lead portion formed of a foil and can be finely processed by etching, has drawbacks such as a decrease in lead position accuracy due to expansion and contraction of an insulating tape and a lack of moisture resistance reliability.
本発明は、以上の欠点を解消し多ピン化および高密度
実装化が可能なICリード用部材の提供を課題とする。SUMMARY OF THE INVENTION An object of the present invention is to provide an IC lead member which can solve the above-mentioned drawbacks and can have a large number of pins and a high density mounting.
本発明者は種々検討した結果、第１図に示すように重
量％でNi35〜55％、残部実質的にFeからなる基板部３と
重量％でNi35〜55％、残部実質的にFeからなり厚さ100
μｍ以下の箔状でありリード部１とが絶縁層２を介して
接合た構造とし、かつ基板部およびリード部を形成する
合金の表面酸化膜の厚みが20〜150ÅであるICリード用
部材とすることにより前記課題を解決した。As a result of various studies, the inventor of the present invention has found that, as shown in FIG. 1, the substrate portion 3 is composed of 35 to 55% by weight of Ni and the balance being substantially 35% to 55% of Ni and the balance being substantially composed of Fe. Thickness 100
an IC lead member having a structure in which the lead portion 1 is joined to the lead portion 1 through the insulating layer 2 and the thickness of the surface oxide film of the alloy forming the substrate portion and the lead portion is 20 to 150 mm. This has solved the problem.
本発明において、基板部に重量％でNi35〜55％、残部
実質的にFeからなるFe−Ni合金を用いるのは、半導体チ
ップとの熱的整合性を持たせるためである。In the present invention, the reason for using the Fe-Ni alloy consisting of 35 to 55% by weight of Ni and the balance substantially of Fe for the substrate portion is to provide thermal compatibility with the semiconductor chip.
Ni量が35％未満ではオーステナイト単相組織が得られ
ず、熱膨張係数の変動をきたす可能性があるため35％以
上とする。また、55％を越えると熱膨張係数が大きくな
りチップとの整合性が維持できなくなるため55％以下と
した。またこの成分系であれば基板として必要な機械的
強度を十分満足できる。If the Ni content is less than 35%, an austenite single phase structure cannot be obtained, and the thermal expansion coefficient may fluctuate. On the other hand, if it exceeds 55%, the coefficient of thermal expansion increases, and it becomes impossible to maintain the consistency with the chip. In addition, this component system can sufficiently satisfy the mechanical strength required for the substrate.
リード部を形成する金属箔については前記TABには導
電性に優れたCuが用いられているが、Cuは強度が低いた
めワイヤーボンディング時に変形を起こしやすい。As for the metal foil forming the lead portion, Cu having excellent conductivity is used for the TAB. However, since Cu has low strength, it is easily deformed during wire bonding.
また、基板部との熱膨張整合性、めっき性、はんだ付
け性等を考慮した場合、基板部と同等の組成を有するこ
とが望ましい。Further, in consideration of thermal expansion matching with the substrate, plating properties, solderability, and the like, it is desirable that the composition has the same composition as the substrate.
本発明では以上の事項を考慮し、リード部に機械的強
度に優れたNi35〜55％、残部実質的にFeからなるFe−Ni
合金を用いることにした。In the present invention, in consideration of the above, Ni-35 to 55% having excellent mechanical strength is provided on the lead portion, and the remainder is substantially Fe-Fe-Ni.
We decided to use an alloy.
リード部の厚さを100μｍ以下とするのは微細加工を
容易にするためである。The reason why the thickness of the lead portion is set to 100 μm or less is to facilitate fine processing.
前記基板部とリード部とは絶縁層を介して接合されて
いる。The substrate and the lead are joined via an insulating layer.
絶縁層を介して接合するのは、絶縁層によって基板部
とリード部とを電気的に分離させるためである。すなわ
ちリード部は絶縁層を介して接合された箔をエッチング
によりリード形状に加工するが、その際にリード部のみ
がエッチングされる必要があり、また形成されたリード
同志が短絡しないように絶縁層を介して接合するのであ
る。絶縁層の耐熱性を150℃以上としたのは、150℃未満
では、チップやワイヤーのボンディング時の加熱の際に
絶縁層が変質を起すため、150℃以上とした。The bonding via the insulating layer is for electrically separating the substrate portion and the lead portion by the insulating layer. That is, the lead portion is processed into a lead shape by etching the foil bonded via the insulating layer. At that time, only the lead portion needs to be etched, and the insulating layer is formed so that the formed leads do not short-circuit. It joins through. The reason for setting the heat resistance of the insulating layer to 150 ° C. or higher is that if the temperature is lower than 150 ° C., the insulating layer is deteriorated when heated at the time of bonding a chip or a wire.
なお、絶縁層を介して前記基板部とリード部となる箔
を接合する方法としては、エポキシ系樹脂等の絶縁性の
接着剤で接着する。またはエポキシ樹脂、不飽和ポリエ
ステル樹脂等に紙、布等の基板を含浸させたシート、フ
ィルムの状態で前記基板部とリード部との間に介在さ
せ、加熱、加圧を施すことにより接合する等の方法が適
用される。In addition, as a method of joining the substrate portion and the foil serving as a lead portion via an insulating layer, the foil is bonded with an insulating adhesive such as an epoxy resin. Alternatively, a sheet or film in which a substrate such as paper or cloth is impregnated with an epoxy resin, an unsaturated polyester resin, or the like is interposed between the substrate and the lead in a state of a film, and bonded by applying heat and pressure. Method is applied.
本発明者が、基板部およびリード部と絶縁層との接着
について種々検討した結果、基板部およびリード部をな
す合金の表面に20Å以上の厚さを有する酸化層を形成さ
せた場合に、その接着力が改善されることが見出され
た。The present inventors have conducted various studies on the adhesion between the substrate and the lead and the insulating layer, and found that when an oxide layer having a thickness of 20 mm or more was formed on the surface of the alloy forming the substrate and the lead, the It has been found that the adhesion is improved.
但し、酸化膜の厚さが150Åを越えると、はんだの濡
れ性が劣化するため、表面酸化膜の適正な厚さを20〜15
0Åに限定した。However, if the thickness of the oxide film exceeds 150 mm, the wettability of the solder deteriorates.
Limited to 0Å.
表面酸化膜の厚さは、合金中に通常脱酸剤として含ま
れるSi、Mn、Al量によりコントロールすることも可能で
ある。The thickness of the surface oxide film can be controlled by the amounts of Si, Mn, and Al usually contained as a deoxidizing agent in the alloy.
また酸化膜は絶縁層との接合前に加熱により形成され
ればよい。The oxide film may be formed by heating before bonding to the insulating layer.
本発明によれば形成されたリード部が基板部および絶
縁層に固定されているため、リードの寄りや段差が生じ
ることはなく、多ピン化、高密度実装化の要求に十分対
応し得る。According to the present invention, since the formed lead portion is fixed to the substrate portion and the insulating layer, there is no deviation of the lead and no step difference, and it can sufficiently cope with the demand for multi-pin and high-density mounting.
また、基板部はそのままパッケージの外周として用い
ることが可能であり、従来のセラミックスやプラスチッ
ク封止に比べて熱放散性にも優れる。Further, the substrate portion can be used as it is as the outer periphery of the package, and is superior in heat dissipation as compared with conventional ceramics or plastic sealing.
本発明の実施例について述べる。 An embodiment of the present invention will be described.
基板部として、厚さ0.35mm、幅500mmの42％Ni−Fe合
金の鋼帯を用い、厚さ0.05mm、幅500mのビスフェノール
Ａエポキシ系樹脂を絶縁層（接着剤として使用）とし
て、リード部として厚さ0.05mm、幅500mmの42Ni−Fe合
金の箔を接合させた。得られた帯素材について平均熱膨
張係数、引張試験と電気伝導度の測定を行った。Using a 42% Ni-Fe alloy steel strip with a thickness of 0.35 mm and a width of 500 mm as the substrate, a bisphenol A epoxy resin with a thickness of 0.05 mm and a width of 500 m as an insulating layer (used as an adhesive) A foil of a 42Ni-Fe alloy having a thickness of 0.05 mm and a width of 500 mm was joined. About the obtained band material, the average thermal expansion coefficient, the tensile test, and the measurement of the electric conductivity were performed.
また、リード用箔をリード幅0.3mm、リードピッチ0.6
5mm、リード長15mmのQFP（Quad Flat Package）パター
ンにフォトエッチングを行いリード位置の判定を行っ
た。エッチング液は濃度42ボーメ、液温40℃の塩化第二
鉄水溶液を用いた。Also, use a lead foil with a lead width of 0.3 mm and a lead pitch of 0.6.
Photoetching was performed on a QFP (Quad Flat Package) pattern having a lead length of 5 mm and a lead length of 15 mm, and the lead position was determined. As an etching solution, a ferric chloride aqueous solution having a concentration of 42 Baume and a liquid temperature of 40 ° C. was used.
さらに、42％Ni−Fe合金と絶縁層との密着強度の評価
は、42％Ni−Fe合金の酸化膜厚さを種々変えて絶縁層と
の接合を行ない、得られた帯素材について180゜曲げ戻
し試験（曲げ部のＲは0.25mmRである）を行なった。Further, the evaluation of the adhesion strength between the 42% Ni-Fe alloy and the insulating layer was performed by variously changing the oxide film thickness of the 42% Ni-Fe alloy and joining the insulating layer. A bending return test (R at the bent portion is 0.25 mmR) was performed.
なお、比較例として42Ni−Fe合金単位、2.3Fe−0.03P
−Cu（鉄入り銅、CDA194）単体についても同様の測定、
判定を行なった。As a comparative example, 42Ni-Fe alloy unit, 2.3Fe-0.03P
-The same measurement was performed for Cu (copper with iron, CDA194) alone.
A decision was made.
結果を第１表に示す。第１表中の評価は以下の通りで
ある。The results are shown in Table 1. The evaluations in Table 1 are as follows.
Siチップとの熱的整合性は、常温から300℃までの平
均熱膨張係数が12×10-6/℃以下を良、12×10-6/℃を越
えるものを不良とした。Regarding the thermal compatibility with the Si chip, an average coefficient of thermal expansion from room temperature to 300 ° C. was determined to be good when the average thermal expansion coefficient was 12 × 10 −6 / ° C. or less, and poor when the average thermal expansion coefficient exceeded 12 × 10 −6 / ° C.
リード強度は引張強さが50kgf/mm2以上を良、50kgf/m
m2未満を不良とした。Lead strength tensile strength of 50 kgf / mm 2 or more good, 50 kgf / m
less than m 2 was defective.
リード位置の判定は、リードの寄りまたは段差が生じ
ないものを良、生じたものを不良とした。The lead position was determined as good when there was no deviation or step in the lead, and poor when there was.
樹脂密着性は180゜曲げ戻し試験後絶縁層が剥離して
隙間が生じたものを不良、剥離が生じないものを良とし
た。Resin adhesion was evaluated as poor when the insulating layer was peeled off after the 180 ° bending-back test and a gap was formed, and good when the peeling did not occur.
第１表から明らかなように本発明はICリード用部材に
要求される諸物性を十分に満足するものである。 As is apparent from Table 1, the present invention sufficiently satisfies various physical properties required for the IC lead member.
本発明によれば、多ピン化、高密度実装化が可能で、
かつ熱放散性に優れたICリード用部材を提供することが
でき、その効果は大きい。According to the present invention, multi-pin, high-density mounting is possible,
In addition, an IC lead member having excellent heat dissipation can be provided, and the effect is great.
第１図は本発明IC用リード部材の断面図である。 1:リード部、2:絶縁層、3:基板部 FIG. 1 is a cross-sectional view of an IC lead member of the present invention. 1: Lead part, 2: Insulation layer, 3: Board part
Claims (2)
なるFe−Ni合金の基板部と重量％でNi35〜55％、残部実
質的にFeからなり厚さ100μｍ以下の箔状であるリード
部とが絶縁層を介して接合されておりリード部を形成す
る合金の表面酸化膜の厚みが20〜150Åであることを特
徴とするICリード用部材。1. A Fe-Ni alloy substrate comprising 35 to 55% by weight of Ni and the balance being substantially Fe, and a foil having a thickness of 100 μm or less comprising 35 to 55% by weight of Ni and substantially balance of Fe. And a lead portion which is bonded via an insulating layer, and a thickness of a surface oxide film of an alloy forming the lead portion is 20 to 150 mm.
１記載のICリード用部材。2. The IC lead member according to claim 1, wherein the heat resistance of the insulating layer is 150 ° C. or higher.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24716888A JP2606905B2 (en) | 1988-09-30 | 1988-09-30 | IC lead member |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24716888A JP2606905B2 (en) | 1988-09-30 | 1988-09-30 | IC lead member |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0294658A JPH0294658A (en) | 1990-04-05 |
| JP2606905B2 true JP2606905B2 (en) | 1997-05-07 |
Family
ID=17159453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24716888A Expired - Fee Related JP2606905B2 (en) | 1988-09-30 | 1988-09-30 | IC lead member |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2606905B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012146730A (en) * | 2011-01-07 | 2012-08-02 | Hitachi Cable Ltd | Lead wire for solar cell and solar cell using the same |
| US9403233B2 (en) | 2011-12-16 | 2016-08-02 | Illinois Tool Works Inc. | DC electrode negative rotating arc welding method and system |
| US9511442B2 (en) | 2012-07-27 | 2016-12-06 | Illinois Tool Works Inc. | Adaptable rotating arc welding method and system |
-
1988
- 1988-09-30 JP JP24716888A patent/JP2606905B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0294658A (en) | 1990-04-05 |
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| Date | Code | Title | Description |
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| LAPS | Cancellation because of no payment of annual fees |