JP2606559B2 - LSI wiring structure and method of forming the same - Google Patents
LSI wiring structure and method of forming the sameInfo
- Publication number
- JP2606559B2 JP2606559B2 JP5196761A JP19676193A JP2606559B2 JP 2606559 B2 JP2606559 B2 JP 2606559B2 JP 5196761 A JP5196761 A JP 5196761A JP 19676193 A JP19676193 A JP 19676193A JP 2606559 B2 JP2606559 B2 JP 2606559B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- groove
- lsi
- sio
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子作成プロセス
の一つであるＬＳＩ配線の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an LSI wiring which is one of processes for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術および発明が解決しようとする課題】従
来、ＬＳＩの配線材料にはＡｌあるいはＡｌ合金が用い
られていたが、今後の微細化にはＡｌあるいはＡｌ合金
では抵抗値の高さによる信号伝達速度の遅れ、マイグレ
ーション耐性の低さによる信頼性の低下が問題となる。
Ａｕ、Ａｇ、Ｃｕは低抵抗、高マイグレーション耐性か
らＡｌに代わる配線材料として期待されている。従来の
ＡｌおよびＡｌ合金配線は、塩素を用いたドライエッチ
ング法により蒸気圧の高いＡｌＣｌ3を形成し、低温で
加工を行っていた。しかしながらＡｕ、Ａｇ、Ｃｕの塩
素化合物は蒸気圧が低く、ドライエッチング法による低
温での加工は困難である。そこで埋め込み法による配線
形成が試みられている。この方法は配線形状に溝を形成
してその溝に配線材料を選択成長させるか、もしくは配
線材料を溝以外の箇所にも均一に堆積した後にエッチバ
ックすることにより配線を形成する方法である。この埋
め込み配線ではグラフォエピタキシーが期待されている
が、実際には製造プロセス温度が低温であるためグラフ
ォエピタキシーは困難である。本発明の目的は、埋め込
み配線において、低温でのグラフォエピタキシーを実現
し、大粒径、高配向のＬＳＩ配線構造とその形成方法を
提供することにある。2. Description of the Related Art Conventionally, Al or an Al alloy has been used as a wiring material for an LSI. However, in the future miniaturization, a signal due to a high resistance value of the Al or an Al alloy is used. Problems such as a delay in transmission speed and a decrease in reliability due to low migration resistance become problems.
Au, Ag, and Cu are expected to replace Al because of their low resistance and high migration resistance. Conventional Al and Al alloy wiring have been formed at a low temperature by forming AlCl 3 having a high vapor pressure by a dry etching method using chlorine. However, the chlorine compounds of Au, Ag, and Cu have low vapor pressures, and it is difficult to perform low-temperature processing by dry etching. Therefore, wiring formation by an embedding method has been attempted. This method is a method in which a groove is formed in a wiring shape and a wiring material is selectively grown in the groove, or a wiring material is formed by uniformly depositing the wiring material in a portion other than the groove and then etching back. Graphoepitaxy is expected in this buried wiring, but in practice, graphoepitaxy is difficult because the manufacturing process temperature is low. An object of the present invention is to provide a large grain size, highly oriented LSI wiring structure which realizes graphoepitaxy at a low temperature in an embedded wiring, and a method of forming the same.
【０００３】[0003]
【課題を解決するための手段】本発明は、配線形状に溝
を設けた配線パターンが基板上に形成され、該溝に配線
材料が埋め込まれたＬＳＩ配線構造であって、前記配線
パターンの溝部の側壁における底辺部の材料は、前記溝
部の底面および側壁上部の材料よりも配線材料に対する
吸着力の強い材料で構成されてなることを特徴とするＬ
ＳＩ配線構造である。ここで、吸着力の弱い材料と吸着
力の強い材料との組み合わせは、それぞれＳｉＯ2とＳ
ｉxＮ1-x、またはＳｉＯ2とＴｉＮ、またはＳｉＯ2とＴ
ｉＷ、またはＳｉxＮ1-xとＴｉＮ、またはＳｉxＮ1-xと
ＴｉＷであることを好適とする。According to the present invention, there is provided an LSI wiring structure in which a wiring pattern having a groove in a wiring shape is formed on a substrate, and a wiring material is embedded in the groove. Wherein the material at the bottom of the side wall is made of a material having a stronger attraction to the wiring material than the material at the bottom of the groove and the upper part of the side wall.
This is an SI wiring structure. Here, the combination of a material having a weak adsorption force and a material having a strong adsorption force is SiO 2 and S, respectively.
i x N 1-x , or SiO 2 and TiN, or SiO 2 and T
iW, or a suitable that the Si x N 1-x and TiN or Si x N 1-x and TiW,.
【０００４】また、そのＬＳＩ配線構造を形成するため
の方法は、基板上に第１の材料を堆積する工程と、該第
１の材料上に第１の材料よりも配線材料に対する吸着力
の強い第２の材料を堆積する工程と、該第２の材料上に
第２の材料よりも配線材料に対する吸着力の弱い第３の
材料を堆積する工程と、前記第２の材料および前記第３
の材料を加工して、前記第１の材料を溝の底面とする配
線形状の溝を形成する工程と、該溝に配線材料を堆積す
る工程と、溝の外部に堆積された配線材料を除去する工
程とからなることを特徴とする。Further, a method for forming the LSI wiring structure includes a step of depositing a first material on a substrate and a method of forming a first material on the first material, which has a stronger attraction force to the wiring material than the first material. A step of depositing a second material, a step of depositing a third material having a lower adsorbing power on the wiring material than the second material on the second material, and a step of depositing the second material and the third material.
Forming a wiring-shaped groove using the first material as the bottom surface of the groove, depositing a wiring material in the groove, and removing the wiring material deposited outside the groove. And a step of performing
【０００５】[0005]
【作用】埋め込み配線のパターンの溝の底面および側壁
上部に配線材料に対する吸着力の弱い材料を、側壁の底
辺部分の材料に配線材料に対する吸着力の強い材料を用
いて配線を形成する。グラフォエピタキシーは結晶粒の
配向が下地だけでなく側壁の影響を受けることによりエ
ピタキシャル成長させるのが基本原理である。１０００
℃程度以上の高温堆積の場合、埋め込みの穴の部分のど
こで核成長が生じても、結晶粒の面内回転自由度が高い
ため壁との界面エネルギーを最小にするように結晶粒が
回転し全ての結晶粒の配向が揃いグラフォエピタキシャ
ル成長が可能となる。しかしながらＬＳＩ製造プロセス
で許されるような低温堆積では埋め込み幅程度の結晶粒
の面内回転は困難であり、グラフォエピタキシーするた
めには核形成を壁と底の境界部分に生じさせ核の段階か
ら配向を揃えなければならない。本発明では溝の底面お
よび側壁上部に吸着力の弱い材料を、側壁の底辺部分に
吸着力の強い材料を用いることにより、底面を表面拡散
した配線材料粒子が壁面でトラップされ核形成は壁と底
の境界から生じ、グラフォエピタキシーが可能となる。
低温でグラフォエピタキシーを実現することにより、埋
め込み配線の大粒径化、高配向化が可能となる。大粒径
化、高配向化により配線のマイグレーション耐性が向上
し、信頼性の高い配線が可能となる。The wiring is formed by using a material having a low attraction to the wiring material on the bottom surface of the groove and an upper portion of the side wall of the pattern of the buried wiring, and a material having a high attraction to the wiring material at the bottom of the side wall. The basic principle of graphoepitaxy is that the crystal grains are epitaxially grown by the influence of the side walls as well as the orientation of the crystal grains. 1000
In the case of high-temperature deposition of about ℃ or more, no matter where nucleus growth occurs in the buried hole, the crystal grains rotate so as to minimize the interfacial energy with the wall due to the high degree of freedom of in-plane rotation of the crystal grains. All the crystal grains have the same orientation, enabling grapho-epitaxial growth. However, in low-temperature deposition, which is allowed in LSI manufacturing processes, in-plane rotation of crystal grains with a buried width is difficult, and in order to perform graphoepitaxy, nucleation occurs at the boundary between the wall and the bottom. The orientation must be aligned. In the present invention, by using a material having a low adsorptivity on the bottom surface and the upper portion of the side wall and a material having a strong adsorptivity on the bottom portion of the side wall, wiring material particles whose surface is diffused on the bottom surface are trapped on the wall surface and nucleation is formed on the wall. Arising from the bottom boundary, graphoepitaxy is possible.
By realizing graphoepitaxy at a low temperature, it is possible to increase the grain size and orientation of the buried wiring. By increasing the grain size and increasing the orientation, the migration resistance of the wiring is improved, and a highly reliable wiring can be obtained.
【０００６】[0006]
【実施例】次に、本発明の実施例について図面を参考に
して説明する。 実施例１ 図１は本発明のＬＳＩ配線形成方法の一実施例を示す基
板の断面図である。まず図１（ａ）に示すように、Ｓｉ
基板１上に吸着力の弱い第１の材料であるＳｉＯ2２を
ＣＶＤ法により１００〜１００００オングストローム堆
積し、次にＳｉＯ2２上にＳｉＯ2に比べて吸着力の強い
第２の材料であるＳｉxＮ1-x３をＣＶＤ法により５〜１
００オングストローム堆積し、次にＳｉxＮ1-x３上に吸
着力の弱い第３の材料であるＳｉＯ2４をＣＶＤ法によ
り１００〜１００００オングストローム堆積する。次に
図１（ｂ）に示すように、通常のドライエッチング技術
によりＳｉxＮ1-x３およびＳｉＯ2４を加工し、溝の底
がＳｉＯ2２となるようにＳｉxＮ1-xのみを除去し、配
線形状の溝を形成する。次に配線材料のＣｕを室温〜５
００℃で堆積すると、堆積初期の段階で図１（ｃ）に示
すように底部と側壁部の境界部分からのみＣｕ核５ａが
形成する。Ｃｕ核５ａは底部と側壁部の両方に対し（１
１１）配向するため、埋め込まれたＣｕはグラフォエピ
タキシャル成長する。そのまま堆積を続けると、図１
（ｄ）に示すように、溝の内部には単結晶Ｃｕ５が、外
部には多結晶Ｃｕ６が形成される。その後、通常のエッ
チバック技術により溝の外部の多結晶Ｃｕを除去し、図
１（ｅ）に示すような単結晶Ｃｕ配線が形成される。Next, embodiments of the present invention will be described with reference to the drawings. Embodiment 1 FIG. 1 is a sectional view of a substrate showing an embodiment of an LSI wiring forming method of the present invention. First, as shown in FIG.
SiO 2 2, which is a first material having a weak adsorption force, is deposited on the substrate 1 by 100 to 10000 angstroms by a CVD method, and then a second material having a stronger adsorption force than SiO 2 is formed on the SiO 2 2. the Si x N 1-x 3 by the CVD method 5-1
Then, 100 Å of SiO 2, which is a third material having a low adsorptivity, is deposited on the Si x N 1 -x 3 by CVD in a thickness of 100 to 10000 Å. Next, as shown in FIG. 1 (b), processing the Si x N 1-x 3 and SiO 2 4 by conventional dry etching technique, Si as the bottom of the groove is SiO 2 2 x N 1-x Is removed to form a wiring-shaped groove. Next, Cu of the wiring material is changed from room temperature to 5
When deposited at 00 ° C., Cu nuclei 5a are formed only at the boundary between the bottom and the side wall at the initial stage of the deposition, as shown in FIG. 1C. The Cu nucleus 5a has (1
11) The embedded Cu grows by grapho-epitaxial growth for orientation. If the deposition is continued as it is,
As shown in (d), single-crystal Cu5 is formed inside the groove, and polycrystalline Cu6 is formed outside. Thereafter, the polycrystalline Cu outside the groove is removed by a normal etch-back technique, and a single-crystal Cu wiring as shown in FIG. 1E is formed.
【０００７】以上の結果は、吸着力の弱い材料と強い材
料がそれぞれＳｉＯ2とＳｉxＮ1-xでなく、ＳｉＯ2とＴ
ｉＮ、またはＳｉＯ2とＴｉＷ、またはＳｉxＮ1-xとＴ
ｉＮ、またはＳｉxＮ1-xとＴｉＷであっても同様の結果
を得ることができる。また配線材料の堆積方法はスパッ
タ法でもＣＶＤ法でも良い。また吸着力の弱い第１の材
料および第３の材料は、二つとも同じ材料であってもよ
いし、別の材料であってもよい。さらに、配線材料とし
ては、本実施例で用いたＣｕのほかに、Ａｕ，Ａｇ，Ａ
ｌなどであってもよい。[0007] These results, rather than a SiO 2 material susceptible and strong material suction force each Si x N 1-x, SiO 2 and T
iN or SiO 2 and TiW, or Si x N 1-x and T,
iN or Si x N 1-x and TiW is a also similar result can be obtained. The wiring material may be deposited by a sputtering method or a CVD method. Further, the first material and the third material having weak adsorption powers may be the same material or different materials. Further, as the wiring material, in addition to Cu used in this embodiment, Au, Ag, A
1 or the like.
【０００８】[0008]
【発明の効果】以上説明したように、本発明によれば埋
め込み配線においてグラフォエピタキシーを実現し、大
粒径、高配向のＬＳＩ配線構造を提供することができ
る。As described above, according to the present invention, graphoepitaxy can be realized in a buried wiring, and a large grain size and highly oriented LSI wiring structure can be provided.
【図１】本発明によるＬＳＩ配線形成方法の一実施例を
示す工程断面図である。FIG. 1 is a process sectional view showing one embodiment of an LSI wiring forming method according to the present invention.
１ Ｓｉ基板 ２ ＳｉＯ2 ３ ＳｉxＮ1-x ４ ＳｉＯ2 ５ 単結晶Ｃｕ ５ａ Ｃｕ核 ６ 多結晶Ｃｕ1 Si substrate 2 SiO 2 3 Si x N 1 -x 4 SiO 2 5 single crystal Cu 5a Cu nuclei 6 polycrystalline Cu
Claims (3)
板上に形成され、該溝に配線材料が埋め込まれたＬＳＩ
配線構造であって、前記配線パターンの溝部の側壁にお
ける底辺部の材料は、前記溝部の底面および側壁上部の
材料よりも配線材料に対する吸着力の強い材料で構成さ
れてなることを特徴とするＬＳＩ配線構造。An LSI in which a wiring pattern having a groove in a wiring shape is formed on a substrate and a wiring material is embedded in the groove.
An LSI having a wiring structure, wherein a material of a bottom portion of a side wall of a groove of the wiring pattern is made of a material having a stronger attraction to a wiring material than a material of a bottom surface of the groove and an upper portion of the side wall. Wiring structure.
の組み合わせが、それぞれＳｉＯ2とＳｉxＮ1-x、また
はＳｉＯ2とＴｉＮ、またはＳｉＯ2とＴｉＷ、またはＳ
ｉxＮ1-xとＴｉＮ、またはＳｉxＮ1-xとＴｉＷである請
求項１記載のＬＳＩ配線構造。2. A combination of a strong material suction force and weak adsorption force material, SiO 2 and Si x N 1-x, respectively, or SiO 2 and TiN, or SiO 2 and TiW, or S,
i x N 1-x and TiN or Si x N 1-x and the LSI wiring structure according to claim 1, wherein a TiW,.
該第１の材料上に第１の材料よりも配線材料に対する吸
着力の強い第２の材料を堆積する工程と、該第２の材料
上に第２の材料よりも配線材料に対する吸着力の弱い第
３の材料を堆積する工程と、前記第２の材料および前記
第３の材料を加工して、前記第１の材料を溝の底面とす
る配線形状の溝を形成する工程と、該溝に配線材料を堆
積する工程と、溝の外部に堆積された配線材料を除去す
る工程とからなることを特徴とするＬＳＩ配線の形成方
法。3. depositing a first material on a substrate;
Depositing a second material having a higher adsorbing power on the wiring material than the first material on the first material, and weaker adsorbing power on the wiring material than the second material on the second material; Depositing a third material; processing the second material and the third material to form a wiring-shaped groove having the first material as a bottom surface of the groove; A method of forming an LSI wiring, comprising: a step of depositing a wiring material; and a step of removing the wiring material deposited outside the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5196761A JP2606559B2 (en) | 1993-07-15 | 1993-07-15 | LSI wiring structure and method of forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5196761A JP2606559B2 (en) | 1993-07-15 | 1993-07-15 | LSI wiring structure and method of forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0729907A JPH0729907A (en) | 1995-01-31 |
| JP2606559B2 true JP2606559B2 (en) | 1997-05-07 |
Family
ID=16363187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5196761A Expired - Lifetime JP2606559B2 (en) | 1993-07-15 | 1993-07-15 | LSI wiring structure and method of forming the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2606559B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100387257B1 (en) * | 1999-12-28 | 2003-06-11 | 주식회사 하이닉스반도체 | Method of forming a metal line in a semiconductor device |
| US6566248B1 (en) * | 2001-01-11 | 2003-05-20 | Advanced Micro Devices, Inc. | Graphoepitaxial conductor cores in integrated circuit interconnects |
| KR100783274B1 (en) * | 2006-11-29 | 2007-12-06 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
| KR20200093514A (en) | 2017-11-30 | 2020-08-05 | 라이온 가부시키가이샤 | Oral biofilm formation inhibitor and oral composition |
| CN111417381B (en) | 2017-11-30 | 2023-06-30 | 狮王株式会社 | Oral scale remover, oral scale formation inhibitor, and oral composition |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59195844A (en) * | 1983-04-20 | 1984-11-07 | Toshiba Corp | Manufacture of semiconductor device |
-
1993
- 1993-07-15 JP JP5196761A patent/JP2606559B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0729907A (en) | 1995-01-31 |
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