JP2604072B2 - Etching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method used for manufacturing a semiconductor device, and more particularly to an etching method suitable for manufacturing a semiconductor device having a diaphragm such as a pressure sensor or an acceleration sensor.

[0002]

2. Description of the Related Art In recent years, there has been a movement in the United States to obligate the installation of an airbag system in a passenger car, and the need for an acceleration sensor, which is an important component of this system, is increasing very much. There are two types of acceleration sensors, a mechanical type and a semiconductor type. However, semiconductor type acceleration sensors are becoming mainstream from the viewpoints of sensing sensitivity and reliability, and the fact that semiconductor type pressure sensor technology can be used. .

On the other hand, the applicant of the present invention has proposed gallium arsenide (GaAs).
s) An acceleration sensor using a compound semiconductor was previously proposed (Japanese Patent Application Laid-Open No. 2-67966). The manufacturing method shown in FIGS. 4 and 5 was used for the diaphragm portion forming step and the element separating step of the acceleration sensor.

[0004] As shown in FIG.
AlGaAs stopper layer 102, P-type or semi-insulating GaAs buffer layer 10
3. An N-type GaAs active layer 104 is sequentially laminated, an element separation and a dicing mark 105 are formed on the surface of the wafer using a sulfuric acid-based etchant, and an electrode 106 is formed on each element surface by a lift-off method.

After forming an interlayer insulating film 107 on the wafer and forming contact holes on the electrodes of each element, gold 108 as an upper layer wiring is vapor-deposited on the entire surface (FIG. 4B).

The surface of the gold is covered with the patterned photoresist 109, and at the same time, the entire back surface of the substrate is protected by the photoresist 110 (FIG. 4c).

The gold as the upper layer wiring is patterned, and the back surface of the diaphragm portion 11 is formed by jet polishing.
1 (FIG. 5d).

Then, as shown in FIG. 5E, a protective member 112 such as wax is buried in the diaphragm portion 111, and is completely cut from the upper portion of the semiconductor substrate using a dicing machine, and divided into chips.

[0009]

However, in the conventional manufacturing process, in the process of forming the upper wiring metal layer by etching, the back surface of the GaAs semiconductor substrate is also etched at the same time, and a reaction product at this time is removed by the back surface. Since this may hinder the etching, it is necessary to protect the back surface with a resist.

Further, since the chip is divided from the surface of the substrate by using a dicing machine, the diaphragm portion 111
Although the protection member 112 is embedded in the diaphragm 111, the diaphragm 111 may be damaged.

The present invention has been made to solve such problems, and an object of the present invention is to provide a method for etching a semiconductor substrate, which can simplify a manufacturing process and improve a yield at the time of chip division. And

[0012]

According to the present invention, there is provided an etching method comprising: forming a metal layer containing at least gold on a GaAs substrate;
A patterning layer is formed on the back surface of the substrate, and the metal layer containing gold and the back surface of the GaAs substrate are simultaneously etched using an aqueous solution containing potassium iodide (KI) and iodine (I ₂ ).

[0013]

Since the etching of the metal layer and the etching of the back surface of the substrate are performed at the same time, the formation of the metal wiring pattern and the formation of the dicing mark on the back surface of the substrate can be performed simultaneously.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are manufacturing process diagrams of a semiconductor sensor to which the etching method according to the present invention is applied. FIG.
In the step shown in FIG. 2A, an AlGaAs stopper layer 2, a P-type or semi-insulating GaAs buffer layer 3, and an N-type GaAs active layer are formed on a semi-insulating GaAs substrate 1 by using a known MBE method, VPE method, or the like. After the epitaxial growth of the N-type GaAs active layer 4 by using a sulfuric acid-based etchant, an element 5 is formed on the surface of the device by a lift-off method.

A photosensitive polyimide resin is applied to the entire surface of the semiconductor substrate and exposed to light to perform patterning. Gold (Au) for upper wiring is deposited on the photosensitive polyimide resin as the interlayer insulating film 6 by a vacuum deposition method. Formed using
A resist 8 for wiring patterning is formed on the metal layer 7. Further, a resist 9 for forming a dicing mark 10 is formed on the back surface of the semiconductor substrate.
b).

The semiconductor wafer is wet-etched with potassium iodide: iodine: water (volume ratio 100: 25: 300) (FIG. 1c). In this step, gold (Au) deposited on the entire surface of the wafer is etched to form an upper wiring pattern, and at the same time, a dicing mark 10 is formed on the back surface of the semiconductor substrate.

The wet etching conditions (capacity ratio,
(Temperature, time, etc.) are preferably performed under conditions that are optimal for etching the metal layer 7 containing gold (Au). This is because gold (A) for a potassium iodide-based etchant is used.
This is because comparing the etching rates of u and GaAs, gold (Au) has a higher etching rate, and the processing accuracy of the dicing mark 10 may be lower than that of gold (Au).

Next, the surface of the semiconductor substrate is covered with a polyimide resin 11 to protect it, and a pattern is formed on the back surface of the semiconductor substrate by using a resist in order to form a diaphragm 12, and deep selective etching is performed using a jet polishing method. Then, the diaphragm portion 12 is formed (FIG. 2D). The etching at this time uses an ammonia-based etchant, and is H ₂ O ₂ (30%) / NH ₄ OH.
(28%), the capacity ratio of 5 to 30 is most excellent in terms of both selectivity and etch rate.

Using this etchant, jet polishing is performed using a spin etching apparatus 31 shown in FIG. By etching while increasing the number of rotations of the wafer 32 mounted on the spin etching apparatus 31, a local flow at the time of etching is eliminated, and the yield increases. Note that reference numeral 33 in FIG.
4 is an etching solution.

Next, as shown in FIG. 2E, a semiconductor substrate with the diaphragm portion 12 facing upward is attached to a silicon substrate 14 via a wax 13 and dicing is performed. Since the diaphragm portion 11 faces upward, there is no need to break during dicing or to embed a protective member in the diaphragm portion 11.

[0021]

As described above, the following effects can be obtained by using the etching method according to the present invention. Conventionally, a dicing mark can be formed simultaneously with metal wiring of a substrate by using a resist that has protected the back surface of a semiconductor substrate, thereby simplifying the manufacturing process. Further, since the dicing mark is formed on the back side of the semiconductor substrate, the semiconductor substrate can be turned upside down and attached to the silicon substrate, and full dicing can be performed from the back side of the semiconductor substrate. Therefore, in the past, dicing was performed by embedding a protective member in the diaphragm portion, but such a protective member is not required, and the yield in the chip dividing step is improved.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor sensor to which an etching method according to the present invention is applied.

FIG. 2 is a manufacturing process diagram of a semiconductor sensor to which the etching method according to the present invention is applied.

FIG. 3 is a schematic structural diagram of a spin etching apparatus.

FIG. 4 is a manufacturing process diagram of a conventional semiconductor sensor.

FIG. 5 is a manufacturing process diagram of a conventional semiconductor sensor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate, 7 ... Metal layer for upper wiring, 10 ... Dicing mark, 12 ... Diaphragm part.

Claims (1)

(57) [Claims] 1. An etching method for etching a metal layer containing at least gold formed on a semiconductor substrate containing gallium (Ga) and arsenic (As), wherein the metal layer on the semiconductor substrate and the back surface of the semiconductor substrate are etched. A patterning layer, and simultaneously etching the metal layer and the back surface of the semiconductor substrate with an aqueous solution containing potassium iodide (KI) and iodine (I ₂ ).