JP2603125B2 - Content reference memory cell - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell, and more particularly to an improvement in a content reference memory cell.

[Prior art] Figure 28 shows the IEEE Journal of Solid State Circuits vo
FIG. 1 is a circuit diagram showing a content reference memory cell shown in l.sc-7, No. 5, October 1972, pp. 364-369. The first conductive terminal of the first insulated gate field effect transistor M _W1 (in this case, an n-MOS transistor) is connected to the first bit line BL.
, And the control terminal (gate) is connected to the word line WL. Similarly, the second n-MOS transistor M
The first conduction terminal of _W2 is connected to the second bit line ▼, and the gate is connected to the word line WL.

The first conduction terminal of the third n-MOS transistor M _S1 is connected to the first bit line BL, and the gate thereof is connected to the second conduction terminal of the first transistor M _W1. Similarly, the first conduction terminal of the fourth n-MOS transistor M _S2 is not connected to the second bit line ▲ ▼, gate is connected to the second conduction terminal of the second transistor M _W2 I have.

The first conduction terminal of the fifth n-MOS transistor M _D are connected in common to a respective second conduction terminal of the third and fourth transistors M _S1, M _S2, a gate and a second conduction The terminals are commonly connected to a match line ML.

In the conventional content reference memory cell configured as described above, since the memory cell is now formed of an n-MOS transistor, the first bit line BL is set to “H” level and the second bit line is set to “H” level. Set ▲ ▼ to “L” level. Because if this time word line WL is "H" level first transistor M _W1 is turned on, a positive charge is accumulated from the first bit line BL at the "H" level to the gate of the third Toranjinsuta M _S1 As a result, the third transistor _MS1 is also turned on. On the other hand, the second transistor _MW2 is also turned on by the "H" level of the word line WL, but the gate of the fourth transistor _MS2 has the second bit line at the "L" level.
Is connected to ▼, the fourth transistor _MS2 is turned off. If the word line WL is set to the "L" level in this state, the writing of information (data) is completed. now,
This storage state is defined as data logic “1”.

Next, when searching the stored data, the match line ML is precharged to the “H” level, and the bit line pair BL, ▲
Give the data you want to refer to ▼. Now, if "1" is given as the reference data, the first bit line
BL is set to “H” level, and the second bit line ▲ ▼ is set to “L”.
Level. At this time, since the match line ML is "H" level the transistor M _D of the fifth is turned on, the memory state "1" in the third and fourth transistors M _S1, M _S2 respectively ON and OFF states of the above , The match line ML is connected to the first bit line BL and cut off from the second bit line ▲ ▼. However, since the first bit line BL is at the “H” level, the “H” level of the match line ML is maintained. That is, by maintaining the precharge level “H” of the match line ML, it can be known that the stored data matches the reference data.

On the other hand, when "0" is given as reference data, the first bit line BL is set to "L" level and the second bit line BL
Is set to the “H” level. At this time, the fifth
Through transistor M _D and the third transistor M _S1,
From the match line ML at the “H” level to the first at the “L” level
Since the charge is extracted to the bit line BL, the match line ML in the floating state becomes “L” level. That is, by changing the precharge level “H” of the match line ML to “L”, it can be known that the stored data does not match the reference data.

FIG. 29 is a circuit diagram showing a content reference memory cell disclosed in JP-A-63-31091. In this memory cell, the first non-volatile memory transistor M _F1 (e.g., floating gate type en balun Gerhard transistor) first conduction terminal connected to the word line WL / match line ML, control gate first bit line Connected to BL, and the second conduction terminal is grounded. In contrast, the first conduction terminal of the second non-volatile memory transistor M _F2 is connected to the word line WL / match line ML, control gate is connected to the second bit line ▲ ▼ to and the The two conductive terminals are grounded.

In the content reference memory cell of FIG. 29, the first bit line BL is temporarily set to "H" level, and the second bit line
Was in the "L" level, and if the "H" level to the word line WL, the electron generated by the avalanche breakdown in the first floating-gate avalanche transistor M _F1 is toward the control gate at the "H" level It is attracted and electrons are injected into the floating gate. As a result, the threshold voltage V _TH of the first floating-gate avalanche transistor M _F1 increases. On the other hand, since the control gate of the second floating-gate avalanche transistor M _F2 is in the "L" level, not generated electrons injected into the floating gate, the threshold voltage V _TH is kept low while. Thus, it is possible to write a pair of data to the nonvolatile memory transistor M _F1 and M _F2.

When referring to such written data, the match line ML is precharged to the “H” level, for example, the first bit line BL is set to the “H” level, and the second bit line ▲ ▼ is set to the “L” level. "To the level. Then, without conducting the threshold voltage V _TH of the first nonvolatile memory transistor M _F1 is high. Also, a second nonvolatile memory transistor
M _F2 is the remains threshold voltage V _TH is low, the potential of the control gate does not conduct since the "L" level. That is, the first and second nonvolatile memory transistors are both in a non-conductive state, and the “H” level of the match line ML is maintained. As a result, bit line pair B
It can be seen that the content reference data given to L, ▲ ▼ matches the stored data.

Conversely, when the first bit line BL is set at "L" level and the second bit line ▼ is set at "H" level, the second nonvolatile memory transistor _MF2 is turned on. Accordingly, the second charge from the match line ML via the non-volatile memory transistor M _F2 is pulled, the match line ML is changed to "L" level. As a result, the first and second bit line pairs B
It turns out that the content reference data given to L, ▲ ▼ matches the stored data.

[Problems to be Solved by the Invention] In the memory cell referred to in FIG. 28, electric charge is stored in the gate of the insulated gate field effect transistor to hold stored data, so that rewriting (refresh) must be performed. There is a problem that stored data is lost if power is cut off.

On the other hand, in the content reference memory cell of FIG. 29, the stored data is retained even if the power is cut off, but the data stored in the memory cell cannot be read directly from the bit line pair. That is, the content reference memory cell in FIG.
There is a problem that it cannot be used as a RAM cell (random access memory cell).

In view of the above-described problems in the prior art, an object of the present invention is to retain stored data even when power is cut off, and to read the data directly from a bit line pair, and further operate with low power consumption. The object is to provide a fast content reference memory cell.

[Means for Solving the Problems] A content reference memory cell according to one aspect of the present invention includes a first conductive terminal connected to a first bit line of a bit line pair, a control terminal connected to a word line, And a first insulated gate field effect transistor having a second conductive terminal; a first conductive terminal connected to the second bit line of the bit line pair; a control terminal connected to the word line; A second insulated gate field effect transistor having a first conductive terminal; and a first conductive terminal connected to the first bit line, and a second conductive terminal of the second insulated gate field effect transistor. A first non-volatile memory transistor having a control terminal and a second conduction terminal; a first conduction terminal connected to a second bit line; a second conduction of the first insulated gate field effect transistor Connect to terminal A second nonvolatile memory transistor having a connected control terminal and a second conductive terminal; and a first commonly connected to respective second conductive terminals of the first and second nonvolatile memory transistors. A third insulated gate field effect transistor having a conduction terminal, a control terminal commonly connected to the match line, and a second conduction terminal is included.

In a content reference memory cell according to another aspect of the invention, a first conductive terminal of each of the first and second nonvolatile memory transistors is connected to a corresponding one of the bit line pairs.
They are not directly connected to each other, but are connected via one insulated gate field effect transistor whose conduction is controlled by a word line.

A content reference memory cell according to still another aspect of the present invention includes not only a pair of bit lines but also a pair of word lines, and stores data stored in a pair of nonvolatile memory transistors in a bit line pair. From the word line pair.

[Operation] In the content reference memory cell according to the present invention, since the nonvolatile memory transistor holds the storage data, the refresh operation is unnecessary, the power consumption is small, the operation speed is high, and the storage is performed even when the power is cut off. No data is lost. Further, since the conductive terminals of each of the pair of nonvolatile memory transistors are electrically connected to the corresponding one of the bit line pairs, the stored data can be directly read from the bit line pairs. it can.

FIG. 1 is a circuit diagram showing a content reference memory cell according to an embodiment of the present invention. In this figure, a first conductive terminal of a first insulated gate field effect transistor M _W1 (here, an n-MOS transistor) is connected to a first bit line BL.
And the gate is connected to the word WL. Similarly, the first conduction terminal of the second n-MOS transistor M _W2 are be connected to the second bit line ▲ ▼, gate is connected to the word line WL.

The first floating-gate avalanche over transistor M _F1 of the first nonvolatile memory transistor
Is connected to the first bit line BL, and the control gate is the second terminal of the second n-MOS transistor _MW2 .
Is connected to the conduction terminal of Similarly, the first conduction terminal of the second floating-gate avalanche transistor M _F2 are be connected to the second bit line ▲ ▼,
The control gate is connected to the second conduction terminal of the first n-MOS transistor _MW1 .

The first conduction terminal of the third n-MOS transistor M _D are connected in common to a respective second conduction terminal of the first and second floating-gate avalanche transistor M _F1, M _F2, and a gate The second conduction terminals are commonly connected to a match line ML.

In the content reference memory cell configured as described above, the “H” level of each signal line is normally set to 5V.
However, only at the match line ML at the time of data writing, its “H” level is raised to 10 V by a driver or the like. “L” level is 0V (GND
Potential).

Now, to temporarily write data "1", the first bit line BL
Is set to “H” level (5V), and the second bit line BL is set to “L” level (0V). At this time, if the word line WL is set to “H” level (5V) and the match line ML is set to “H” level (10V), the floating gate type avalanche transistor
Cause avalanche breakdown between the source and the drain of M _F2, electrons are injected into the floating gate.
As a result, the threshold voltage VTH of the second floating gate type avalanche transistor _MF2 is increased, and the second floating gate type avalanche transistor _MF2 is turned off.

Referring to FIG. ₂ , an example of the second floating gate type avalanche transistor MF2 is shown in a cross-sectional view, illustrating the process of injecting electrons into the floating gate. In the floating gate type avalanche transistor, the main surface of the p-Si substrate 1 has n ⁺ diffusion regions 2a and 2b serving as a source and a drain, respectively.
Are formed. These source 2a and drain 2b
Via a contact hole formed in the insulating layer 3, they are connected to a source electrode 5 a and a drain electrode 5 b serving as first and second conduction terminals, respectively. A floating gate 4 is provided in an insulating layer region 3a on a channel region between a source and a drain, and a control gate 6 is further provided thereon via an insulating layer. The first conduction terminal 5a is connected to the second bit line at the "L" level (0 V).
▼ is connected to the second conduction terminal 5b via a third n-MOS transistor M _D in the ON state "H" level (10
V) is connected to the match line ML. That is, the drain potential V _D is 10 V, and the potential difference between the source and the drain is 10 V. The control gate electrode 6 is connected to the "H" level (5 V) via the first n-MOS transistor _MW1 in the ON state. That is, the gate potential V _G = 5V. Further, the p-Si substrate 1 is set to the GND potential. At this time, avalanche breakdown occurs between the source and the drain, and as shown by the arrow in the drawing, holes escape to the p-Si substrate 1 side, and electrons are injected into the floating gate 4 and accumulated. Due to the electric field effect of the accumulated electrons, the threshold voltage VTH of the floating gate type avalanche transistor _MF2 is increased and the floating gate type avalanche transistor _MF2 is turned off.

Returning to FIG. 1, the second conduction terminal of the first floating-gate avalanche transistor M _F1 is 10V match line ML is applied via the third n-MOS transistor M _D, first 5V of the first bit line BL is connected to the conduction terminal of, and the potential difference between the source and the drain becomes 5V. Further, since the control gate second bit line ▲ ▼ is 0V is connected via a second n-MOS transistors M _W2, in the first floating-gate avalanche transistor M _F1, electron avalanche injection Does not occur and the ON state is maintained.

Thus, the first and second floating-gate avalanche transistor M _F1, if the M _F2 to "L" level of the word line WL after the on and off states, respectively,
This means that data "1" has been written to the memory cell. However, ultraviolet data is used to erase the written data.

When reading the written data, the bit line pair BL,
▲ ▼ to "H" level to match line ML after discharging and the third n-MOS transistor M _D in the ON state. At this time, if if data "1" is written, "H" match line ML in the level, the third n-MOS transistor M _D and the first floating gate avalanche in the ON state It is connected to the first bit line BL via the transistor M _F1, and is blocked second bit line ▲ from ▼ by the second floating gate Abba Alan Chez transistor M _F2 in the off state.
As a result, the potential of only the first bit line BL increases,
Data can be read by sensing the potential difference between the pair of bit lines BL and ▲ ▼.

When inspecting the stored data, the match line ML is precharged to the “H” level, and the bit line pair BL, ▲ ▼
Give the data you want to refer to. Now, assuming that "1" is given as the reference data, the first bit line BL becomes "H".
Level, and the second bit line ▲ ▼ is set to “L” level. At this time, since the match line ML is precharged but the third n-MOS transistor M _D is turned on, the first and second floating-gate avalanche transistor if the data has been stored is "1" Since M _F1 and M _F2 are on and off, respectively, the match line ML is connected to the first bit line BL and the second bit line
Will be cut off. However, since the first bit line BL is at the “H” level, the “H” level of the match line ML is maintained. That is, by maintaining the precharge level “H” of the match line ML, it can be known that the stored data matches the reference data.

If reference data "0" is given while data "1" is stored, first bit line BL is set to "L" level and second bit line ▲ ▼ is set to "H" level. So
"H" charge from the match line ML to a third n-MOS transistor M _D and the first bit line BL through the first floating-gate avalanche transistor M _F1 in level is extracted, the match line ML becomes "L" Become a level. Match line ML
Is changed from the "H" level to the "L" level, it can be known that the stored data did not match the reference data.

In a memory cell array including a plurality of such memory cells, if both lines of a certain bit line pair BL are set to the “H” level, the “H” level of the match line ML is changed regardless of the stored data. Since this memory bit is maintained, this memory bit is in a don't care state, that is, it can be ignored and only the data of the other memory bits can be searched.

In the above embodiment, the example in which the floating gate type avalanche transistor holds stored data has been described. Instead of the floating gate type avalanche transistor, MNOS (metal nitride oxide silicon) is used.
Type transistors can be used equally.

FIG. 3 is a sectional view showing an example of an MNOS transistor. The MNOS type transistor of FIG. 3 is similar to the floating gate type avalanche transistor of FIG. 2, but an oxide film 10, a nitride film 11, and a control gate 6 are sequentially stacked on a channel region. These layers 1
0, 11 and 6 are covered with an insulating film 7, and the control gate 6 is connected to the gate electrode 5c via a contact hole formed in the insulating film 7. This MNOS transistor can accumulate electrons near the interface between the oxide film 10 and the nitride film 11, and can be operated in the same manner as a floating gate type avalanche transistor.

In the embodiment shown in FIG. ₁ , a FLOTOX (floating gate tunnel oxide) transistor can be used as the nonvolatile memory transistors M _F1 and M _F2 . In this case, all "H" levels may be set to, for example, 10 V when writing data, and may be set to, for example, 5 V when reading and searching data. Also FL
Data written to the OTOX transistor can be electrically erased.

Referring to FIG. 4, an example of a FLOTOX transistor is shown in a cross-sectional view, illustrating the process of injecting electrons into the floating gate. In this FLOTOX transistor, the first surface of the p-Si substrate 1
And two n ⁺ diffusion regions 2 a and 2 b serving as second conduction terminals are formed, and are covered with the insulating layer 3. Channel region between two n ⁺ diffusion regions 2a and 2b and n ⁺ diffusion region 2a
, A floating gate 4 is provided via an insulating layer, and a control gate 6 is further provided thereon via an insulating layer. When the match line ML connected to the second conductive terminal 2b is in a floating state, and the first conductive terminal 2a is connected to 0V of the second bit line ▲ ▼, the first control gate 6 is connected to the control gate 6. When a voltage of 10 V is applied to the bit line BL, electrons are tunneled and accumulated in the floating gate 4 from the n ⁺ diffusion region 2a through the extremely thin insulating layer region 3b as shown by an arrow e. Due to the electric field effect of the accumulated electrons, the FLOTOX transistor has its threshold voltage V
_TH becomes high and it is turned off.

FIGS. 5 and 6 are circuit diagrams showing two other embodiments of the present invention. The memory cell according to these embodiments has a first
The circuit has a circuit completely equivalent to the memory cell shown in FIG. However, when these memory cells are realized as a semiconductor device, wirings crossing each other are different between the embodiments. In the layout of the integrated circuit, which wiring crosses affects the size of the chip area. Therefore, an appropriate one of the above embodiments may be selected depending on the case.

FIG. 7 is a circuit diagram showing still another embodiment of the present invention. The memory cell is replaced with a first and second n-MOS transistors M _W1, M _W2 the first respectively second p-MOS transistor M _W1 ', M _W2' in the memory cell of FIG. 1 is there. Therefore, if the word line is set to the "L" level (0 V) when writing data, and set to the "H" level (5 V) at the time of reading and searching, the same operation as the first memory cell is performed.

FIG. 8 is a circuit diagram showing still another embodiment of the present invention. This memory cell is similar to the memory cell of FIG. 1, a first conduction terminal of the first non-volatile memory transistor M _F1 is not directly connected to the first bit line BL, and first It is connected via an n-MOS transistor _MW1 . Similarly, the second nonvolatile memory transistor M
The first conduction terminal of _F2 is not directly connected to the second bit line ▼, but is connected via the second n-MOS transistor _MW2 . The memory cell shown in FIG.
It will be apparent that the operation at the “H” level is equivalent to that of the memory cell of FIG.

FIG. 9 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 9 is similar to the memory cell of FIG. 7, except that the first nonvolatile memory transistor M
The first conduction terminal of _F1 is connected to the first bit line BL via a first MOS transistor M _W1 'of p-channel type, a first conduction terminal of the second non-volatile memory transistor M _F2 Is also a p-channel type second MOS transistor
It is connected to the second bit line ▲ ▼ via M _W2 ′. The memory transistor of FIG. 9 also sets the word line WL to “L”.
It will be apparent that the level operation behaves similarly to the memory cell of FIG.

FIG. 10 is a circuit diagram showing still another embodiment of the present invention. This memory cell is obtained by replacing the second n-MOS transistor _MW2 in the memory cell of FIG. 8 with a p-MOS transistor _MW2 ', and accordingly, the gate of the p-MOS transistor _MW2 ' Is connected to the second
Word line ▲ ▼. It will be apparent that the memory cell of FIG. 10 operates similarly to the memory cell of FIG. 8 by setting the second word line WL to the “L” level.

FIG. 11 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 11 is similar to the memory cell of FIG. 10, except that the first nonvolatile memory transistor
The first conduction terminal of M _F1 is connected directly to the first bit line BL, and a first conduction terminal of the second non-volatile memory transistor M _F2 also direct a second bit line ▲ ▼ to be connected I have.

FIG. 12 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 12 is similar to the memory cell of FIG. 8, _{except that} the gate terminal of the second n-MOS transistor MW2 is connected to the second word line ▼. The memory cell in FIG. 12 includes a first conduction terminal connected to the first word line WL, a control terminal connected to the first bit line BL, and a first non-volatile memory transistor _MF1 . A first conduction terminal connected to a second word line and a second bit line including a fourth n-MOS transistor _MB1 having a second conduction terminal connected to the first conduction terminal; A fifth n-MOS transistor M having a control terminal connected to ▼ and a second conduction terminal connected to the first conduction terminal of the second nonvolatile memory transistor _MF2
Contains _B2 . Further, the memory cell of FIG.
When the second non-volatile memory transistor M _F1, the first conduction terminal, and the second to the match line ML ₂ and gate terminal connected to a common second, which is connected to the common to the second conduction terminal of M _F2
A sixth n-MOS transistor _MD2 having a conduction terminal of.

In the memory cell of FIG. 12 having such a structure, when the same signal as that of the first word line WL is applied to the second word line ▼, the bit line pair BL, It will be understood from ▲ that data can be written to and read from the first and second nonvolatile memory transistors M _F1 and M _F2 . Also, the bit line pair BL, ▲
Be given a content reference data to ▼, depending on whether the first precharged potential of the match line ML ₁ is changed, also whether the stored data matches the reference data can be determined understood Let's do it.

By the way, in the memory cell of FIG.
BL, ▲ ▼ and the word line WL, ▲ ▼ is in symmetrical relationship with each other, the word line pair WL, ▲ ▼ from also the first and second non-volatile memory transistor M _F1, writing the data into the M _F2 It can also be seen and can be read therefrom. Further, when providing the word line pair WL, ▲ ▼ content reference data to, depending on whether the second potential of the match line ML ₂ precharged is changed, the data stored matches the reference data It will also be appreciated that it may be known or not.

FIG. 13 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 13 is similar to the memory cell of FIG. 12, but has first and second n-MOS transistors.
M _W1 and M _W2 and the fourth and fifth n-MOS transistors M _B1 and M _B1
B2 are p-MOS transistors M _W1 ′, M _W2 ′, M _B1 ′,
And _MB2 '. It is understood that the same operation as the memory cell in FIG. 12 can be performed in the memory cell in FIG. 13 by applying an appropriate signal potential to the word line pair WL, ▲ or the bit line pair BL, ▲ ▼. Let's do it.

FIG. 14 is a circuit diagram showing still another embodiment of the present invention. This content reference memory cell is an IBM Technical Di
sclosure Bulletin, Vol. 26, No. 1, June 1983, pp. 191-19
2 includes the nonvolatile SRAM cell 100 shown in FIG. In this nonvolatile SRAM cell 100, the first conduction terminal of the first n-MOS transistor T1 is connected to the first bit line BL, the gate is connected to the word line WL, and the second conduction terminal is the second conduction terminal. It is connected to one data node N1. The first conduction terminal of the first non-volatile memory transistor TF1 is connected to the first data node N1, the control gate is connected to a programming line V _P, and a second conduction terminal to the power supply line V _D It is connected. Similarly, the second n-MOS
The first conduction terminal of the transistor T2 is connected to the second bit line ▲
, The gate is connected to the word line WL, and the second conduction terminal is connected to the second data node N2. First of the second nonvolatile memory transistor TF2
The conduction terminal connected to the second data node N2, the control gate is connected to a programming line V _P,
The second conduction terminal connected to the power supply line V _D. Further, the first conduction terminal of the third n-MOS transistor T3 is connected to the first data node N1, the gate is connected to the second data node N2, and the second conduction terminal is connected to the ground line. It is connected to the. Further, the first conduction terminal of the fourth n-MOS transistor T4 is connected to the second data node N2, the gate is connected to the first data node N1, and the first conduction terminal is connected to the ground line. It is connected to the.

FIG. 15 schematically shows a cross-sectional view of a FLOTOX transistor that can be used as the nonvolatile memory transistors TF1 and TF2 in the SRAM cell 100. The FLOTOX transistor of FIG. 15 is similar to that of FIG. 4, but does not have a thinned insulating layer region 3b between the floating gate 4 and the substrate 1, and instead has a floating gate 4
And the control gate 6 have a thinned insulating layer region 3c.

In a normal write or read operation in the nonvolatile SRAM cell 100, the floating gates of the FLOTOX transistors TF1 and TF2 are not charged, and work as a normal depression load. The control gates of these load transistors TF1 and TF2 are set to the ground potential (0 V). But when power cuts are imminent, usually
Supply voltage V _D is 5V rises to approximately 15V programming voltage. Now, assuming that the first data node N1 is at "H" level (5V) and the second data node N2 is at "L" level (0V), the first FLOTOX transistor TF
Electrons are injected into the floating gate 4 from one programming gate 6, and the floating gate 4 is negatively charged. On the other hand, since the second data node N2 is at the ground potential, no electrons are injected into the floating gate of the second FLOTOX transistor TF2, and the second data node N2 is in a normal neutral state. This allows the data to be stored in the first and second FLOTOX
It is held in a nonvolatile manner in the floating gates of the type transistors T1 and T2.

When the power is restored, first, the word line WL is set to the “H” level and the bit line pair BL, ▼ is set to the “L” level, whereby the first and second data nodes N1 and N2 are set to the “L” level. To be. Then, raise both power line V _D and programming line V _P to 15V. First FLTOX transistor TF1
Have a tendency to become non-conductive because the floating gate is negatively charged. On the other hand, the second FLTOX transistor TF2 tends to be conductive because its floating gate is not charged. Therefore, the first data node N1 remains at the ground potential and the second data node N2 charges toward the programming potential. Thus, the first and second data nodes before the power interruption
Data opposite to the data stored in N1,2 is stored. The power supply voltage V _D is returned to 5V, from the floating gate 4 of the first FLOTOX transistor T1 to the programming gate 6 is electrons withdrawn, the floating gate is returned to a neutral state. After that, the programming line _VP
Is returned to the ground potential. As a result, the nonvolatile SRAM cell 100 can perform normal reading and writing. The inverted data stored in the first and second data nodes N1 and N2 after power recovery can be easily returned to the original data by reading once and rewriting via the inverter.

14 is a nonvolatile SRAM cell 10
It further includes a content reference circuit 200 consisting of four n-MOS transistors T5-T8 in addition to zero. The first conduction terminal of the fifth n-MOS transistor T5 is connected to the match line ML, and the gate is connected to the first bit line BL. A first conduction terminal of the sixth n-MOS transistor T6 is connected to a second conduction terminal of the fifth n-MOS transistor T5;
The gate is connected to the second data node N2, and the second conduction terminal is connected to the ground line. Symmetrically, the first conduction terminal of the seventh n-MOS transistor T7 is connected to the match line ML, and the gate is connected to the second bit line ▲.
Connected to ▼. The first conduction terminal of the eighth n-MOS transistor T8 is connected to the second conduction terminal of the seventh n-MOS transistor T7.
And the gate is connected to the first data node N1.
And the second conduction terminal is connected to a ground line.

When performing a search operation in the content reference memory cell configured as described above, first, the bit line pair BL, ▲ is pre-discharged to “L” level, and the fifth and seventh n−
The MOS transistors T5 and T7 are turned off, and then the match line ML is precharged. Now, assume that the data stored in the SRAM cell 100 is “1”. That is, assuming that the first data node N1 is at "H" level and the second data node N2 is at "L" level, the sixth n-MOS transistor T6 is in a non-conductive state, The eighth n-MOS transistor T8 is conducting. Therefore, the reference data of "1" (that is, "H") is applied to the bit line pair BL, ▲ ▼.
Level BL, “L” level ▲ ▼) gives the 5th
N-MOS transistor T5 is turned on, and the seventh n-MOS transistor T7 is turned off. That is, since the sixth n-MOS transistor T6 and the seventh n-MOS transistor T7 are non-conductive, the potential of the precharged match line is maintained. As a result, the reference data given to the bit line pair BL,
It can be seen that the data matches the data stored in.

Conversely, reference data of “0” is applied to the bit line pair BL, ▲ ▼ (that is, “L” level BL, “H” level ▲ ▼)
, The fifth n-MOS transistor T5 is turned off, and the seventh n-MOS transistor T7 is turned on. That is, the seventh and eighth n-MOS transistors T7,
Since both T8s are in a conductive state, charges are extracted from the match line ML to the ground line, and the match line ML is set to the ground potential. This indicates that the reference data given to the bit line pair BL, ▲ ▼ did not match the data stored in the SRAM cell 100.

By the way, in the content reference memory cell of FIG. 14, when the content reference data is given to the bit line pair BL, ▲ ▼, one of the fifth and seventh n-MOS transistors T5, T7 must be conductive. It is in a state. Therefore, even when the reference data and the stored data match, the parasitic capacitance 12 formed between the fifth and sixth n-MOS transistors T5 and T6 or the seventh and eighth n-MOS transistors A part of the precharged charge of the match line ML flows into one of the parasitic capacitances 13 formed between T7 and T8. Therefore, there is a possibility that the potential of the match line ML decreases and an error in content reference occurs.

FIG. 16 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 16 is similar to the memory cell of FIG. 14, except that the gate of the fifth n-MOS transistor T15a is connected to the second data node N2 and the sixth n-MOS transistor The gate of T6 is connected to the first bit line BL. Also, symmetrically, the gate of the seventh n-MOS transistor T7a is connected to the first data node N1, and the gate of the eighth n-MOS transistor T8a is connected to the second data node N1.
Are connected to the bit line ▲ ▼. When data "1" is stored in the memory cell of FIG. 16 (that is, "H" level data node N1 and "L" level data node N2), the seventh n-MOS transistor T7a is conductive. Therefore, the parasitic capacitance 13 is simultaneously precharged while the match line ML is precharged. Therefore, when the reference data applied to the bit lines BL and ▼ matches the data stored in the SRAM cell 100, no further charge flows into the parasitic capacitance 13 from the match line ML. That is, when the data match, the potential of the match line ML does not partially drop, and the malfunction of the content reference is prevented.

FIG. 17 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 17 is similar to the memory cell of FIG. 14, except that the first and second transfer gates T1 'and T2' in the SRAM cell 100 are constituted by p-MOS transistors. Further, the fifth to eighth MOS transistors T5 '
-T8 'is also a p-channel type. In the memory cell of FIG. 17, it can be understood that the word line WL should be set to "L" level in order to activate the transfer gates T1 'and T2'. Also, if for a content addressable operation, the match line ▲ ▼ is pre-discharge to the ground potential, the sixth MOS transistors T6 of the 8 ', T8' second conduction terminal of which is connected to the power supply voltage V _CC . Therefore, it will be understood that the memory cell of FIG. 17 can operate similarly to the memory cell of FIG.

FIG. 18 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 18 is similar to the memory cell of FIG. 16, except that the first and second transfer gates T
1 'and T2' are composed of p-MOS transistors, and the fifth to eighth MOS transistors T5 'to T8' are also p-channel transistors. It will be appreciated that the memory cell of FIG. 18 can operate similarly to the memory cell of FIG.

By the way, when a pair of transfer gates in the SRAM cell 100 are formed by n-channel MOS transistors, a large distance between the read bit lines BL and ▲ ▼ is considered in consideration of the back gate effect of those transistors. To obtain the potential difference, the bit line pair BL,
It is desirable to precharge ▲ ▼ to the power supply potential “H” level. Conversely, a pair of transfer gates is p
In the case of a channel type MOS transistor, in order to obtain a large potential difference between the pair of bit lines BL and ▲ ▼ after reading, the bit line pair BL, ▲
It is desirable that ▼ is pre-discharged. On the other hand, when a pair of MOS transistors whose conduction state is controlled by the bit line in the content reference circuit 200 is of an n-channel type, the bit line pair BL,
▲ ▼ must be pre-discharged to ground potential. This is because the potential of the precharged match line ML must be maintained before the content reference is started. Conversely, the pair of MOS transistors, whose conduction state is controlled by the bit line pair BL,
In case of channel type, before starting the content reference
BL, ▲ ▼ must be precharged to “H” level. This is because the potential of the pre-discharged match line ML must be maintained before the content reference is started.

That is, when both the pair of transfer gate MOS transistors in the SRAM cell 100 and the pair of MOS transistors whose conduction state is controlled in the bit line in the content reference circuit 200 are n-channel type, data reading is performed. Sometimes, the bit line pair must be precharged, and during the content reference operation, the bit line pair must be precharged. Conversely, a pair of transfer gate MOS transistors in the SRAM cell 100 and the content reference circuit 2
If the pair of MOS transistors whose conduction state is controlled by the pair of bit lines BL and ▲ in 00 are both p-channel type, the bit line pair is
BL and ▲ ▼ are pre-discharged and must be pre-charged during the content reference operation.

FIG. 19 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 19 is similar to the memory cell of FIG. 18, except that a pair of transfer gates T1 and T2 in the SRAM cell 100 are formed by n-channel MOS transistors. On the other hand, the four MOS transistors in the content reference circuit are of the p-channel type. Therefore, in this content reference memory cell, when data is read, bit line pair BL, ▼ is precharged, and also when the content is referenced, bit line pair BL, ▼ is precharged.
That is, the bit line pair BL, ▲
It is not necessary to repeat the precharge and predischarge of ▼, which can reduce power consumption and improve operation speed.

FIG. 20 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 20 is similar to the memory cell of FIG. 19, except that the fifth and seventh MOS transistors T5b, T7b
Is an n-channel type. Along with that, the 5th MO
The gate of the S transistor T5b is connected to the first data node N1, and the gate of the seventh MOS transistor T7b is connected to the second data node N2. It will be appreciated that the memory cell of FIG. 20 operates similarly to the memory cell of FIG.

FIG. 21 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 21 is similar to the memory cell of FIG. 16, except that a pair of transfer gates T1 'and T2' in the SRAM cell 100 are formed by p-channel MOS transistors. It will be appreciated that the memory cell of FIG. 21 can operate similarly to the memory cell of FIG.

FIG. 22 is a circuit diagram showing still another embodiment of the present invention. In the memory cell shown in FIG.
MOS transistors T5b 'and T7b' are p-channel type. Accordingly, the gate of the fifth MOS transistor T5b 'is connected to the first data node N1, and the gate of the seventh MOS transistor T7b' is connected to the second data node N2. It will be appreciated that the memory cell of FIG. 22 can operate similarly to the memory cell of FIG.

FIG. 23 is a circuit diagram showing still another embodiment of the present invention. In the memory cell of FIG. 23, the content reference circuit 200 is composed of only three MOS transistors. That is, the first conductive terminal and the gate of the fifth n-MOS transistor T5c are commonly connected to the match line ML, and the second conductive terminal is connected to the sixth and seventh n-MOS transistors T6c, T6c, Commonly connected to the first conduction terminal of T7c. The gate of the sixth n-MOS transistor T6c is connected to the first data node N1, and the second conduction terminal is connected to the first data node N1.
Are connected to the bit line BL. The gate of the seventh n-MOS transistor T7c is connected to the second data node N2, and the second conduction terminal is connected to the second bit line ▲ ▼.

In this memory cell, a pair of transfer gates T
Since 1 and T2 are constituted by nMOS transistors, it is desirable to precharge the bit line pair BL, ▲ ▼ before starting data reading. On the other hand, at the time of referring to the contents, if it is assumed that data of "1" (node N1 at "H" level, node N2 at "L" level) is stored, the sixth n-MO
The S transistor T6c is in a conductive state, and the seventh n-MOS transistor T7c is in a non-conductive state. Therefore, before the start of content reference, the bit line pair BL, ▼ may be precharged in the same manner as before the start of reading. That is, there is no need to switch the precharge and predischarge of the bit line pair BL, ▲ ▼ according to the operation mode. Therefore, power consumption can be reduced and operation speed can be improved.

After the bit line pair BL, ▲ ▼ is precharged when referring to the contents, the match line ML is precharged. Suppose now that bit line pair BL, ▲ ▼ is referenced with “1” reference data (“H”
If the level BL, “L” level ▲ ▼) is given, the sixth
The n-MOS transistor T6c is in a conductive state, but since the first bit line BL is at the “H” level, the precharged potential of the match line ML is held. This indicates that the content reference data and the stored data match.

On the other hand, when the reference data “0” is given, the first bit line BL
Becomes "L" level, the first bit line BL from the match line ML via the fifth and sixth n-MOS transistors T5c and T6c.
The charge is extracted. As a result, it can be seen that the potential of the match line ML decreases and the content reference data does not match the stored data.

FIG. 24 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 24 is similar to the memory cell of FIG. 23, except that a pair of transfer gates T1 ', T2'
Are constituted by n-MOS transistors, and three MOS transistors T5c ', T6c', T7c 'in the content reference circuit are further provided.
Is a p-channel type. In this memory cell,
At the time of reading, the pit line pair BL, ▲ ▼ may be pre-discharged to set the word line WL to “L” level. Further, it can be understood that the bit line pair BL, ▲ ▼ may be pre-discharged to bring the match line ML to the “L” level before the content reference is started. That is, also in the memory cell of FIG. 24, there is no need to switch between the precharge and the predischarge of the bit line pair BL, ▲ in accordance with the operation mode.

FIG. 25 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 25 is similar to the memory cell of FIG. 23, except that only three MOS transistors T5c ', T6c' and T7c 'in the content reference circuit 200 are of the p-channel type. In this memory cell, it is desirable to precharge the bit line pair BL, ▲ ▼ before the start of reading, but it is understood that the bit line pair BL, ▲ ▼ must be pre-discharged before the start of content reference. Let's do it. Therefore, in the memory cell of FIG. 25, the precharge and predischarge of the bit line pair BL, ▲ ▼ must be switched according to the operation mode, and the power consumption and operation speed are lower than those of the memory cell of FIG. It is slightly disadvantageous in view.

FIG. 26 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 26 is similar to the memory cell of FIG. 23, except that the sixth and seventh MOS transistors T6d ', T6
7d 'is a p-channel type. Along with this, the sixth
The second conduction terminal of the MOS transistor T6d 'is connected to the second bit line ▲ ▼, and the second conduction terminal of the seventh MOS transistor T7d' is connected to the first bit line BL. . In this memory cell, it is desirable to precharge the bit line pair BL, ▲ ▼ before reading data, and to start bit line pair BL, ▲
It will be understood that ▼ must be precharged. That is, in the memory cell of FIG. 26, it is not necessary to switch between the precharge and the predischarge of the bit line pair BL, ▼ in accordance with the operation mode, as in the memory cell of FIG.

FIG. 27 is a circuit diagram showing still another embodiment of the present invention. The memory cell of FIG. 27 is similar to the memory cell of FIG. 24, except that the sixth and seventh MOS transistors T6d, T7d
Is an n-channel type. As a result, the sixth MO
The second conduction terminal of the S transistor T6d is connected to the second bit line ▲
The second bit line of the seventh MOS transistor T7d is connected to the first bit line BL.
In this memory cell, it is desirable to pre-discharge bit line pair BL, ▲ ▼ before reading data, and it is necessary to pre-discharge bit line pair BL, ▲ ▼ before starting content reference. Let's do it. That is, also in this memory cell, there is no need to switch between the precharge and predischarge of the bit line pair BL, ▼ in accordance with the operation mode, as in the memory cell of FIG.

In the memory cell shown in the above embodiment,
By making the bit line voltage at the time of writing variable or making the writing time variable, weighting can be performed for each memory cell, thereby making the memory cell suitable for an associative system that allows ambiguity. It is.

[Effect of the Invention] As described above, according to the present invention, there is provided a content reference memory cell capable of retaining stored data and reading stored data directly from a bit line pair even when power is cut off. can do. Furthermore, the content reference memory cell according to the present invention can operate with low power consumption and high speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a content reference memory cell according to one embodiment of the present invention. 2 to 4 are cross-sectional views schematically showing structures of various nonvolatile memory transistors. FIGS. 5 to 14 are circuit diagrams showing further various embodiments of the present invention. FIG. 15 is a sectional view schematically showing the structure of yet another nonvolatile semiconductor memory cell. FIGS. 16 to 27 are circuit diagrams showing further various embodiments of the present invention. FIG. 28 and FIG. 29 are circuit diagrams showing prior art content reference memory cells. In the figure, _MF1 and _MF2 are nonvolatile memory transistors,
M _W1, M _W2, M _D is a MOS transistor, BL and ▲ ▼ bit line pair, WL denotes a word line, and ML represents the match line. In each drawing, the same reference numerals indicate the same contents or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Natsuo Mika 4-1-1 Mizuhara, Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Machinery Co., Ltd. No. 1 In Mitsubishi Electric Corporation LSI Research Institute (72) Inventor Shinichi Sato 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation LSI Research Institute (56) References JP 49-119543 (JP, A) JP-A-62-99994 (JP, A) JP-A-61-246996 (JP, A)

Claims (3)

(57) [Claims] A first insulated gate field effect transistor having a first conductive terminal connected to a first bit line of a bit line pair, a control terminal connected to a word line, and a second conductive terminal; A second insulated gate field effect transistor having a first conduction terminal connected to a second bit line of the bit line pair, a control terminal connected to a word line, and a second conduction terminal; A first conductive terminal connected to a first bit line, a control terminal connected to the second conductive terminal of the second insulated gate field effect transistor, and a first conductive terminal having a second conductive terminal A non-volatile memory transistor; a first conductive terminal connected to the second bit line; a control terminal connected to the second conductive terminal of the first insulated gate field effect transistor; Conduction end A first conductive terminal commonly connected to the second conductive terminal of each of the first and second nonvolatile memory transistors, and a common connection to a match line. And a third insulated gate field effect transistor having a control terminal and a second conduction terminal. A first insulated gate field effect transistor having a first conduction terminal connected to a first bit line of the bit line pair, a control terminal connected to a word line, and a second conduction terminal; A second insulated gate field effect transistor having a first conductive terminal connected to a second bit line of the bit line pair, a control terminal connected to the word line, and a second conductive terminal; A first conductive terminal connected to the second conductive terminal of the first insulated gate field effect transistor, and a control terminal connected to the second conductive terminal of the second insulated gate field effect transistor , And a first non-volatile memory transistor having a second conductive terminal; a first conductive terminal connected to the second conductive terminal of the second insulated gate field effect transistor; A second nonvolatile memory transistor having a control terminal connected to the second conductive terminal of the edge gate type field effect transistor and a second conductive terminal; and each of the first and second nonvolatile memory transistors And a third insulated gate field effect transistor having a control terminal and a second conduction terminal commonly connected to the second conduction terminal, and a control terminal commonly connected to the match line. A content reference memory cell characterized by the following. A first conductive terminal connected to the first bit line of the pair of bit lines, a control terminal connected to the first word line of the pair of word lines, and a first conductive terminal having a second conductive terminal. An insulated gate field effect transistor; a second insulated gate having a first conductive terminal connected to the first word line, a control terminal connected to the first bit line, and a second conductive terminal Type field effect transistor, a first conductive terminal connected to a second bit line of the bit line pair, a control terminal connected to a second word line of the word line pair, and a second conductive terminal. A third insulated gate field effect transistor having a first conductive terminal connected to the second word line, a control terminal connected to the second bit line, and a second conductive terminal. 4 insulated gate field effect transformer Star and, first connected to the common to each of the second conduction terminal of said first and second insulated gate field effect transistor
And a control terminal commonly connected to the second conductive terminal of each of the third and fourth insulated gate field effect transistors; and a first conductive terminal having a second conductive terminal.
And a first common terminal commonly connected to the second conductive terminal of each of the third and fourth insulated gate field effect transistors.
A second conductive terminal, a control terminal commonly connected to the second conductive terminal of each of the first and second insulated gate field effect transistors, and a second conductive terminal.
A first conductive terminal commonly connected to the second conductive terminal of each of the first and second nonvolatile memory transistors, and a first parallel terminal parallel to the word line pair. A fifth insulated gate field effect transistor having a control terminal and a second conduction terminal commonly connected to the match line; and a second conduction terminal of each of the first and second nonvolatile memory transistors. A sixth insulated gate field effect transistor having a first conductive terminal connected in common, a control terminal commonly connected to a second match line parallel to the bit line pair, and a second conductive terminal; A content reference memory cell comprising: