JP2600964B2 - Staff synchronization method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stuff synchronization system, and in particular, performs stuffing in units of words for digital data having a data rate that is asynchronous with the transmission path speed, and synchronizes with the transmission path speed. Related to the staff synchronization method.

[Conventional technology]

In the digital transmission system, one synchronous transmission line clock is used to realize a flexible and efficient communication network configuration in response to changes in the communication demand for each route and to improve the reliability of the network by smoothing the route switching at the time of failure. A digital synchronous multiplex transmission system in which a communication network is configured and digital transmission is performed has been widely adopted. On the other hand, it is often necessary to transmit digital data having a data rate asynchronous to a transmission line clock via such a communication network.

A typical example is transmission of a video signal. That is, when converting a video signal from analog to digital, the frequency of the sampling clock is set to an integral multiple (3 times) of the frequency of the color subcarrier in the video signal in order to suppress aliasing of the color signal spectrum and image quality deterioration due to quantization noise. Double ~
(4 times). As a result, the encoded data rate of the video signal becomes asynchronous with the transmission path rate of the synchronous multiplexing method. In order to synchronize various kinds of digital information having such an asynchronous data rate with a transmission line speed, and multiplex and transmit the multiplexed information, stuff synchronization has been conventionally performed.

FIG. 5 is a block diagram showing an example of such a conventional stuff synchronization system. In Figure 5, the input digital data is written at a speed of f _S word in the elastic memory 10 by the input clock to the words. On the other hand, digital data is read from the elastic memory 10 in word units by the read clock RCK, and is input to one input terminal of the selector 20. A stuff data value is given to the other input terminal of the selector 20, and the selector 20 selects and outputs one of the inputs according to the selection control signal SEL. The read clock generation circuit 30 determines the number of data read from the elastic memory 10 and transmitted to the transmission line every frame time by a flag signal F from the elastic memory 10.
Determined by the value of 1, F2, the number of read clocks corresponding to the number of data to be transmitted is generated, and the selection control signal SEL is generated.
Is created and given to the selector 20.

As described above, in the stuff synchronization method shown in FIG. 5, the setting of the synchronization word rate per one frame time is set to a constant value larger than the word rate of the input digital data, and the difference is compensated by the stuff data. Synchronize to the transmission path speed. That is, the number of inserted stuff data is determined by the read clock generation circuit 30 every frame time, and the selection control signal SEL
By controlling the selector 20, the stuff data is inserted.

In FIG. 5, the number of words of data waiting to be read after writing to the elastic memory 10 (hereinafter referred to as the number of staying words) is monitored, and the number of staying words is the maximum capacity of the elastic memory 10. (For example, 7/8 or more), the number of staff is reduced, and the number of retained words is reduced (for example, elastic memory 10).
Less than one-eighth of the maximum capacity) is trying to reduce the number of staff. For this reason, from the elastic memory 10, the flag signal F1 indicates that the number of staying words is equal to or greater than the maximum capacity 7/8.
It is output at the active level, while the flag signal F2 is
When the number of staying words is equal to or less than 1/8 of the maximum capacity, it is output at an active level, and is supplied to the read clock generation circuit 30 to perform the above-described stuff operation. In this way, the digital data becomes synchronized with the transmission path speed by inserting the stuff data, and can be multiplexed with other data and transmitted.

[Problems to be solved by the invention]

However, when such a conventional stuff synchronization method is used, jitter having a long cycle occurs in the reproduced data speed in destuffing which is performed on the receiving side and removes the stuff data and reproduces the original asynchronous digital data. However, there is a disadvantage that a large phase wander occurs.

For example, if the number of words staying in the elastic memory on the transmitting side is close to 1/8 between 1/8 and 7/8, the flag signals F1 and F2 of the inactive level at this time are
It is assumed that the data rate read from the elastic memory is slightly lower than the input data rate under the number of stuffs defined in (1). At this time, the number of words staying in the elastic memory gradually increases from around 1/8 of the elastic memory capacity to 7/8.
Since the flag signals F1 and F2 do not change until it becomes 8 or more, 1
There is no change in the number of staff per frame.

On the other hand, on the receiving side, the information on the data rate to be reproduced is in the number of stuffs, so the output data rate is reproduced based on the information. However, for a change in the number of staff to occur, there must be some change in the number of stuck words, and while there is no change in the number of staff, the output data rate is
Since there is no new information to be changed, it is not updated. Therefore, the output data rate is not controlled in detail corresponding to the input data rate, and includes a relatively large jitter and wander relative to the input data.

An object of the present invention is to provide a stuff synchronization system capable of eliminating such a drawback and reducing jitter and wander.

[Means for solving the problem]

According to the stuff synchronization method of the present invention, input data is written, a buffer memory for reading data written by a read clock, input speed information is monitored by monitoring the input data speed of the buffer memory, and stuff control is performed from the buffer memory. And means for obtaining a difference value from information indicating the speed of the data to be output and output, and generating means for generating a read clock and sending it to the buffer memory so that the accumulated value of the difference value always takes a small value. It is characterized by:

In addition, the stuff synchronization method of the present invention writes input data, creates a buffer memory for reading data written by a read clock, and monitors input data speed of the buffer memory to create input speed information. Means for obtaining a difference value between the stuff-controlled data to be output and information indicating the speed, and a means for obtaining an accumulated value of the difference value to always take a small value.
Control means for generating stuff information for each frame time and controlling a read clock to the buffer memory.

Furthermore, the stuff synchronization method of the present invention writes the input data, measures the input data rate at predetermined time intervals based on the transmission line clock frequency, and measures the input data rate at each time based on the transmission line clock frequency. An input speed information means for outputting the measured value, and an input / output speed for obtaining a difference between the measured value of the input speed information means and a value corresponding to a read clock frequency in a previous transmission frame time for each transmission frame time The difference obtained by the difference detection means and the input / output speed difference detection means is accumulated for each transmission frame time, and the number of read clocks in the current transmission frame time is determined so that the accumulated value always takes a small value near zero. And the number of readout clones determined by the staff information generating means. It is characterized by having a read clock generating means for generating a click given to the buffer memory.

[Action]

The stuff synchronization method of the present invention compares the stuff control in the current transmission frame with the input data rate information and the output data rate information output by the stuff control in the previous transmission frame, and calculates a difference value between the two information, that is, the input data rate. By obtaining information indicating the difference between the number and the number of output data, and adding it to the accumulated value of the difference value in the stuff control performed two times before and before in the past to obtain a new accumulated value, Creates information proportional to the difference in the total number of input / output data due to the result of the stuff control up to the previous time, and as a result of the stuff control in the current transmission frame, the accumulated value is 0.
Alternatively, the number of read clocks is controlled based on the new accumulated value so as to be a small value near 0.

As described above, the stuff synchronization method of the present invention obtains information proportional to the difference between the total number of data output by the stuff control and the total number of input data every time the stuff control is performed, and the difference is determined by the next stuff control. Perform staff control to reduce the number.

For this reason, the average speed of the output data is kept the same as the input data speed, and the fluctuation amount of the output data speed is kept small. Therefore, the average number of data staying in the buffer memory (1 in FIG. 1) becomes constant,
Generation of wander can be suppressed. Further, stuff jitter can be suppressed to a small value.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The stuff synchronization method shown in FIG.
And an input speed information circuit 2 and an input / output speed difference detection circuit 3
And a stuff information generating circuit 4 and a read clock generating circuit 5.

In such a stuff synchronous circuit, the buffer memory 1 is for storing input data. The input data is connected to the input terminal DI of the buffer memory 1. The input clock indicating the word timing of the input data is connected to the write clock terminal WCK of the buffer memory 1. The output data is output from the output terminal DO of the buffer memory 1. Read clock generation circuit 5
Is input to the read clock terminal RCK of the buffer memory 1. Such a buffer memory 1 outputs data in word units from the output terminal DO according to the read clock.

The input speed information circuit 2 creates a longer cycle based on the cycle of the frame pulse FP, measures the number of input clocks in the cycle, and outputs the input speed information FI. FIG. 2 shows a configuration example of the input speed information circuit 2.
In FIG. 2, 201 is a 10-bit counter, 202 and 203 are latches, 204 is a subtractor, and 205 is a frequency divider.

The input / output speed difference detection circuit 3 includes a decoder 301 and a subtractor 302.
And Then, the input / output speed difference detection circuit 3
The stuff information k output from the stuff information generating circuit 4 is used as one input, which is decoded by a decoder 301 and converted into output speed information FO, and input speed information FI input from the other by a subtractor 302. Is obtained and given to the stuff information creating circuit 4.

The stuff information generating circuit 4 accumulates the difference value d for each frame time, and determines the number of words of the stuff data to be added to the output data from the buffer memory 1 during the current frame time based on the accumulated value. Is output as staff information k. An example of the configuration of the staff information generation circuit 4 is shown in FIG.
Shown in the figure. In FIG. 3, 401 is an accumulator, 401A is an adder, 401B is a latch, and 402 is a comparator.

The read clock generating circuit 5 receives the stuff information k, and generates a read clock having a pulse number of the number obtained by subtracting the value of the stuff information k from the number of data words allocated to the data channel in one frame time. , A read clock terminal RCK of the buffer memory 1. FIG. 4 shows the configuration of the read clock generation circuit 5. In FIG. 4, 501 is a differentiator, 502 is a counter, and 503 is a ROM.

The value of the counter 502 is cleared to 0 every time the frame pulse FP is added in the cycle of the transmission frame, and the output value increases by one by the transmission line clock. The output of the counter 502 and the stuff information k are given to the address input of the ROM 503 which is a read-only memory.

Here, the counter 502 is composed of an 11-bit binary counter, and a total of 12 bits obtained by adding the transmission line side clock added to the counter 502 to the 11-bit count value as the least significant bit are output and given to the ROM. . That is, 11 bits representing the count value of the counter 502 are allocated to the upper 11 bits of the 12 bits, and the 12-bit output with the transmission path clock being the least significant bit is connected to the lower 12 bits of the address input of the ROM 503. On the other hand, the stuff information k is connected to the upper 4 bits of the address input of the ROM 503 by a 4-bit binary number.

On the other hand, in the ROM 503, the following output values are stored as output values corresponding to the 16-bit address input value.

• If the 4-bit value of the upper address is 10 in decimal and the 12-bit value of the lower address is in the range of 0 to 1789 in decimal, "0" is output when the 12-bit value of the lower address is odd. If the number is even, '1' is output.

・ If the value of the upper 4 bits is 11 in decimal and the value of the lower 12 bits is 0 to 1788 in decimal, if the value of the lower 12 bits is odd, '0' is output. If the number is even, '1' is output.

・ When an address value outside the above range is input, '0' is output.

By generating the output value of the ROM 503 as described above, the read clock generation circuit 5 outputs the stuff information k.
When stuff information is 10, 1790 clock pulses are generated, and when stuff information k is 11, 1789 clock pulses are generated. Therefore, this clock pulse is read out and output from the buffer memory 1 of FIG. 1 connected to the read clock terminal RCK only 1790 words when the stuff information k is 10, and 1789 words when the stuff information k is 11. .

Next, the operation of the stuff synchronization method will be described.

The input clock is applied to the buffer memory 1 and the input speed information circuit 2, and the frame pulse FP is applied to the stuff information generation circuit 4 and the read clock generation circuit 5.
The counter 201 of the input speed information circuit 2 is made up of 10 bits and constantly counts the input clock. The 8 kHz frame pulse FP is frequency-divided by the frequency divider 205 into 1/458, and is supplied to the latch 202 and the latch 203 as a clock. The 10-bit output of the counter 201 is connected to the input of the latch 202, and the output of the latch 202 is connected to the input of the latch 203. The subtractor 204 subtracts the output value of the latch 203 from the output value of the latch 202 and outputs the result. Therefore,
From subtractor 204, The remainder obtained by dividing the number of input clocks by 2 ¹⁰ = 1024 is output as input speed information FI.

As described above, the input speed information FI output from the input speed information circuit 2 of the present embodiment is based on the number of input clocks input during one cycle time of the cycle created by dividing the frame pulse FP by the divider 205. That is, it is a measured value of the number of words of the input data, and is a value expressed in modulo 1024. Where 1024 is 2 to the 10th power, a 10-bit counter
This is the count number in which the output value of 201 makes one cycle.

As an example, the sampling frequency of the input video data is
Assuming 14318.182kHz, the following (1) is used as input speed information FI
About 516 is obtained as shown in the equation.

14318.182 × 458 ÷ 81024 × 800 + 516 (1) When the sampling frequency changes, it can be detected by the input speed information FI. For example, + 50ppm change and -50p
When pm changes, the input speed information FI becomes about 557 and 475, respectively.

Now, assuming a system in which the number of words allocated to one video data channel when multiplexing and transmitting video data is 1800 words per frame with a claim repetition frequency of 8 kHz, the video data with a sampling frequency of 14318.182 kHz is 1798.77 words per frame time (14318.182 / 8)
Therefore, average the number of stuff words per frame
It is necessary to make 1800-1789.77 = 10.23 in order to make the average speed of the output data the same as the input data speed. Accordingly, the stuff information creating circuit 4 prepares at least two of the stuff information k of 10,11. Here, if k = 10 words as the stuff information, the read clock generation circuit 5
1800-10 = 1790 pulses are generated and applied to the read clock terminal RCK of the buffer memory 1.

At this time, 1790 words of video data are extracted from the output terminal DO of the buffer memory 1 and output. Therefore, the output speed of the video data for one frame time is 1790
× 8 = corresponds to the rate sampled at 14320 kHz (+127 ppm relative to 14318.182 kHz). At this time, the input / output speed difference detection circuit 3 receives the stuff information k = 10 and converts it into output speed information FO by the decoder 301. That is, the decoder 301
Then, the output speed information FO is obtained by the following equation (3).

[(1800-k) x 8] x 458/8 = 1024 x 800 + FO ...
(2) Here, [] in equation (2) is the output speed (unit: k words / second) of video data by performing k-word stuffing, and [] is multiplied by 458/8. This is because the input speed information FI is measured in units of 1/458 cycle of 8 kHz, and thus the number of output data words converted per the same cycle is obtained. in this way,
Since the equations (1) and (2) perform the same calculation, the input / output information FI is subtracted by the subtractor 302 from the output / speed information FO to represent the input / output data rate difference in the buffer memory 1. The difference value d is obtained. Therefore, the difference value d is a value indicating the difference in the number of words of input / output data per 1/458 cycle of 8 kHz. Table 1 shows an example in which the value of the output speed information FO according to the equation (2) is expressed by a ppm-converted speed deviation with respect to 14318.182 kHz.

Here, the ppm conversion value can be obtained by the following equation (3).

Therefore, the decoder 301 for converting k to FO is shown in Table 1
It can be easily realized by ROM (read only memory) or the like. Accumulated value 401 of staff information creation circuit 4
Accumulates the difference value d output from the input / output speed difference detection circuit 3 every frame time, and outputs an accumulated value S.

As described above, the difference value d is a number obtained by converting the difference in the number of words of input / output data in the previous frame time into a time obtained by dividing 8 kHz by 458, that is, by converting it per 458 frame period. The accumulated value S indicates 458 times the total value of the difference between the number of input and output data in the previous frame time and all the frame times before that. Thus, the accumulated value S is a value proportional to the number of input / output data from the past to the present. Therefore, if the accumulated value S is 0, it indicates that the input / output data rate difference is 0 on average for a long time, and if the accumulated value S keeps a constant value for a certain period of time, the accumulated data S is not input during that time. When the output data speed difference indicates 0 and the accumulated value S continues to increase on the average in the positive direction, the output data speed is on average higher than the input data speed, and therefore the buffer memory 1 Indicates that the number of data stored in the memory continues to decrease, and the data delay time decreases. When the accumulated value S continues to decrease in the negative direction on average, the output data speed is equal to the input data speed. More averagely smaller, and therefore buffer memory 1
This indicates that the number of data stored in the memory continues to increase and the data delay time increases. A large fluctuation of the accumulated value S indicates a large fluctuation of the output data rate, and a small fluctuation of the accumulated value S indicates a small fluctuation of the output data rate.

As described above, the value of the accumulated value S and the temporal change of the value indicate the magnitude of the stuff jitter generated by the stuff control, the occurrence of wander, and the magnitude thereof.

In the stuff synchronization method of the present invention, the accumulated value S is obtained,
Staff control is performed so that the accumulated value S always takes a small value.

Comparator 402 outputs stuff information k = 11 when it is determined that accumulated value S is “0” or positive, and outputs stuff information k = 10 when accumulator S is negative.

The read clock generation circuit 5 generates a number of clock pulses according to the value of the stuff information k. That is, in the read clock generation circuit described above, when the stuff information k = 11 (the accumulated value S is 0 or positive), 1789 clock pulses are generated in the next transmission frame time, and the stuff information k = 10 (accumulated). 1790 when the calculated value S is negative)
Generate clock pulses.

At this time, data of the number of words of the number of clock pulses is read from the buffer memory 1.

On the other hand, the average number of words of data input to the buffer memory 1 per transmission frame time is 1789.77.

Therefore, if the accumulated value S is positive, the number of stuff data increases, the number of data read from the buffer memory 1 becomes smaller than the number of input data, and the accumulated value S decreases in the negative direction. When the accumulated value S becomes negative, the reverse operation is performed.

Therefore, the absolute value of the accumulated value S does not increase, and is always kept at a small value near the value 0.

When any of the output speed information FO shown in Table 1 is added to the accumulated value S instead of the comparator 402, k is selected which can minimize the absolute value of the accumulated value S after the addition. It is also possible to use a circuit for outputting as stuff information.

Such a circuit can be easily realized by using, for example, a signal processor. As an example, the case where the accumulated value S is 200 will be described.
Calculate by substituting FO = 200 to obtain +385 (unit ppm) as the speed error amount. Next, the signal processor reads each table from Table 1 prepared in advance as the inside database.
The converted ppm value is called and added to the calculated speed error amount. At this time, the addition results are as shown in Table 2.

Next, the signal processor performs a magnitude judgment operation of the absolute value, and determines the value having the smallest absolute value among the addition results as −
Get 432. Further, the signal processor obtains and outputs the stuff information k = 11 corresponding to -432 according to Table 1.

As described above, in the stuff synchronization method according to the present embodiment, the input data speed is monitored, and the accumulated value of the difference value of the input / output input speed difference information is always “0” based on the speed information.
Since the stuff information is generated and controlled every frame time so as to take a small value in the vicinity, when the data rate is reproduced using the stuff information on the receiving side, jitter and wander can be reduced, A high quality communication system can be realized.

〔The invention's effect〕

As described above, according to the present invention, since the output data rate is controlled in accordance with the input data rate, there is an effect that digital data transmission with less jitter and wander can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a configuration example of an input speed information circuit shown in FIG. 1, and FIG. 3 is a stuff shown in FIG. FIG. 4 is a diagram showing a configuration example of a read clock generation circuit shown in FIG. 1, and FIG. 5 is a block diagram showing an example of a conventional stuff synchronization system. DESCRIPTION OF SYMBOLS 1 ... Buffer memory 2 ... Input speed information circuit 3 ... Input / output speed difference detection circuit 4 ... Staff information creation circuit 5 ... Read clock generation circuit

Claims (3)

(57) [Claims] 1. A buffer memory for writing input data and reading data written by a read clock, and monitoring input data speed of the buffer memory to create input speed information, and outputting the data under stuff control from the buffer memory. A stuff synchronization system having means for obtaining a difference value from information indicating the speed of data to be read, and generation means for generating a read clock and sending it to a buffer memory so that the accumulated value of the difference value always takes a small value . 2. A buffer memory for writing input data and reading data written by a read clock, and monitoring the input data speed of the buffer memory to create input speed information, and outputting the data under stuff control from the buffer memory. Means for obtaining a difference value between the data to be processed and the information indicating the speed, and stuffing information generated for each frame time so that the accumulated value of the difference value always takes a small value, and a read clock to the buffer memory is set. A stuff synchronization system having a controlling means for controlling. 3. A buffer memory for writing input data and reading data written by a read clock, and measuring an input data rate at predetermined time intervals based on a transmission line clock frequency and outputting the measured value. Input / output speed difference means for comparing a measured value of the input speed information device with a numerical value corresponding to a read clock frequency in a previous transmission frame time for each transmission frame time to obtain a difference therebetween; Stuff information creating means for accumulating the difference obtained by the input / output speed difference detecting means for each transmission frame time and determining the number of read clocks in the current transmission frame time so that the accumulated value always takes a small value; The number of read clocks determined by the information generating means is generated and applied to the buffer memory. And a stuff synchronous system having a read clock generating means.