JP2600284B2 - Digital rectifier circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital rectifier circuit used for a CX decoder of laser vision.

[Prior Art] In laser vision, an audio signal is recorded on a medium after band compression. Then, at the time of reproduction, the detection signal from the medium is returned to the state before band compression by the CX decoder, and reproduced as an audio signal. In the CX decoder, an RMS value (effective value) is used as a reference value for a restoration process of a signal before band compression, and a rectifier circuit is used as a means for obtaining the RMS value.

FIG. 2 is a circuit diagram of the analog rectifier circuit. This circuit comprises an operational amplifier A, a diode B, resistors R ₁ and R ₂ and a smoothing capacitor C ₁ . In this circuit, the input signal {i and the output signal {
and υi> υo, a time constant τ ₁ = R ₂
Capacitor C ₁ is charged with C _1, the capacitor C ₁ is discharged by .upsilon.i <constant tau _{2 =} time when _{υo (R 1 + R 2)} C 1. As a result, the input signal υi and the output signal υo have the waveforms shown in FIG.

Well, recently, signal processing has been mostly digitized,
As the rectifier circuit, a digital rectifier circuit is used. FIG. 4 is a configuration diagram of a conventional digital rectifier circuit. This circuit comprises multipliers 1 and 2, adder 3, delay circuit 4, comparator 5, RO
Consists of M6. Hereinafter, the operation of this circuit will be described.

When the input digital signal X is input at a predetermined sampling cycle, the comparator 5 outputs an output digital rectified signal Y
Is compared with. Then, the coefficient data a is read from the ROM 6 based on the comparison result. The coefficient data a is supplied to the multiplier 2 and also input to an arithmetic unit (not shown), where the coefficient data (1-a) is calculated and supplied to the multiplier 1. In the multiplier 1, the input digital signal X is multiplied by the coefficient data (1-a) and output to the adder 3. On the other hand, the output digital rectified signal Y is taken into the delay circuit 4 every sampling period. Then, the delay circuit 4 always outputs the digital data YZ one sampling cycle earlier.
^-1 is output. This digital data YZ- ¹ is output to the multiplier 2
Is multiplied by the coefficient data a and output to the adder 3. Then, in the adder 3, the digital signal (1-a) X from the multiplier ¹ and the digital signal aYZ ^-1 from the multiplier 2 are output.
Are added, and the result is output as a new output digital rectified signal Y.

[Problems to be Solved by the Invention] Meanwhile, the conventional digital rectifier circuit requires a comparator for comparing the magnitude of the input digital signal with the output digital rectified signal, and calculates the coefficient data (1-a). It is necessary to provide an arithmetic unit for performing the above or to store the coefficient data (1-a) in the ROM in advance. Therefore, this digital rectifier circuit has a large number of components in the entire circuit,
There is a problem that the processing speed is slow because there are many arithmetic circuits.

The present invention has been made in view of the above circumstances, and has as its object to provide a digital rectifier circuit with a simple circuit configuration and a high calculation speed.

[Means for Solving the Problems] According to the present invention, a subtractor that subtracts a feedback signal from an input digital signal input at a predetermined sampling period to output a difference signal, and a sign bit of the difference signal are input. A storage unit that outputs coefficient data corresponding to a sign bit, and a multiplier that multiplies the difference signal by the coefficient data and outputs the result.
An adder that adds the output signal of the multiplier and the feedback signal to output a digital rectified signal, and a delay circuit that delays the digital rectified signal by one sampling cycle and outputs the digital rectified signal as the feedback signal. I have.

[Operation] According to the above configuration, the digital rectified signal one sampling period before is taken in by the delay circuit and output as a feedback signal. Then, a difference signal between the input digital signal and the feedback signal is output from the subtractor, and coefficient data corresponding to the sign bit is read from the storage means and output to the multiplier. In the multiplier, the subtracter multiplies the coefficient data of the difference signal and outputs the result. And, by the adder,
A feedback signal is added to the output signal of the multiplier, and the result is output as a new digital rectified signal.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a digital rectifier circuit according to one embodiment of the present invention. This circuit includes a subtractor 7, a multiplier 8, an adder 9, a delay circuit 4, and a ROM 6. Hereinafter, the operation of this circuit will be described.

In the delay circuit 4, the output digital rectified signal Y is taken in every sampling cycle. Then, the output digital data YZ- ¹ one sampling cycle before is always output from the delay circuit 4 as a feedback signal. On the other hand, when the input digital signal X is input to the digital rectifier circuit at a predetermined sampling cycle, the subtractor 7 subtracts the feedback signal YZ- ^{1 and} outputs a difference signal. Then, the sign bit F in the difference signal is supplied to the ROM 6. In the ROM 6, the coefficient data a stored at the address corresponding to the sign bit F
Is read. Then, the coefficient data a is supplied to the multiplier 8. The multiplier 8 multiplies the difference signal from the subtractor 7 by coefficient data a and outputs the result. The output signal of the multiplier 8 is supplied to the feedback signal YZ by the adder 9.
^-1 is added and output as a new digital rectified signal Y.

The specific circuit configuration of the digital rectifier circuit according to one embodiment of the present invention has been described above, and the processing contents have been described. Recently, the processing by such a digital rectifier circuit has been performed by a DSP (digital signal processor). Often done internally. Also in this case, according to the present invention,
Since the number of calculations is reduced, the processing speed is increased, and the same effect as in the above-described embodiment is obtained.

[Effects of the Invention] As described above, according to the present invention, a subtractor that subtracts a feedback signal from an input digital signal input at a predetermined sampling period and outputs a difference signal, and a sign bit of the difference signal is Storage means for inputting and outputting coefficient data corresponding to the sign bit, a multiplier for multiplying the difference signal by the coefficient data and outputting the result, and a digital rectifier for adding an output signal of the multiplier and the feedback signal to add Since an adder that outputs a signal and a delay circuit that delays the digital rectified signal by one sampling cycle and outputs the signal as the feedback signal are provided, a digital rectifier circuit that operates at high speed with a small number of operations can be realized. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital rectifier circuit according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional analog rectifier circuit, FIG. 3 is a waveform diagram showing the operation of the circuit of FIG. 1 is a configuration diagram of a conventional digital rectifier circuit. 7 ... subtractor, 6 ... ROM, 8 ... multiplier, 9 ... adder, 4 ... delay circuit.

Claims (1)

(57) [Claims] 1. A subtractor for subtracting a feedback signal from an input digital signal inputted at a predetermined sampling period to output a difference signal, and a sign bit of the difference signal is inputted, and coefficient data corresponding to the sign bit is inputted. Storage means for outputting, a multiplier for multiplying the difference signal by the coefficient data and outputting the same, an adder for adding an output signal of the multiplier and the feedback signal to output a digital rectified signal, and the digital rectified signal And a delay circuit for delaying the signal by one sampling period and outputting the feedback signal.