JP2599057B2 - Tape speed control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape speed control circuit at the time of mode transition of a magnetic recording / reproducing apparatus using a tape such as a VTR.

[0002]

2. Description of the Related Art Conventional fast forward (FF) and rewind (RE)
In the operation W), as shown in the block diagram of FIG. 3, a speed control circuit 21 is provided to rotate the motor 20 for driving the reel base at a constant speed. However, in this F / V converter for speed control, the control voltage at the time of starting the motor is not
An H "(high) level output is generated, and the motor receives the output and enters a high torque state, resulting in tape damage immediately after the start of FF / REW.

In order to prevent this, FF / R
From the start of EW, the control voltage is resistance-divided by the PWM signal, and the control voltage level at the time of starting the motor is lowered by smoothing it with a capacitor, and the PWM duty is changed with time as shown in FIG. The technique of gradually increasing the rotation of the motor by causing
No. 3731 (G11B15 / 10).

In this prior art, as shown in FIG. 3, a cycle of an FG pulse of a motor 20 for driving a reel is compared with a reference cycle optimum for FF or REW by a speed control circuit 21, and an FG for the reference cycle is determined. A speed control output that changes as shown in FIG. 4A in accordance with the pulse cycle error is created,
A motor control voltage is applied to the motor 20 via a buffer 22 and a resistor 23. Further, a smoothing capacitor 24 and a switch 25 are inserted in series between the ground in a line subsequent to the buffer 22, and a voltage dividing resistor is connected. 26 and a switch 27 are connected in parallel, a mode signal is issued from the cis-con at the time of FF or REW, the switch 25 is closed to smooth the control signal, and the switch 27 is closed during the H level period of the control PWM signal from the cis-con. The control voltage is configured to be divided.

Although the speed control output voltage changes as shown in FIG. 4A, the duty of the control PWM signal is changed as shown in FIG.
B, the closing time of the switch 27 is gradually shortened, and the resistance 23 of the speed control output voltage is reduced.
4 and the motor control voltage gradually increases immediately after the transition to the FF / REW mode as shown in FIG. .

[0006]

According to the above prior art, the control PWM signal must have a high frequency that can be smoothed by a smoothing capacitor, and the control voltage is determined by resistance division, so that the PWM signal is interrupted. Then, at the time of this interruption, discontinuity occurs in the motor control voltage.
Therefore, even if the rotation of the motor is stabilized, it is necessary to continue the control by the control PWM signal until the PWM duty becomes 0%, and an extra time is required until the mode transition is completed.

[0007]

SUMMARY OF THE INVENTION The present invention provides a reel drive motor for driving a reel, a rotation detector for outputting an FG signal of the motor, and an error between a cycle of the FG signal and a reference period as speed error data. Speed error data generating means for outputting, control data output means for outputting N (N: integer) bits of control data for maintaining a constant value after gradually increasing, and M (M: integer, M>) for counting clocks An N) -bit counter, first comparing means for comparing the count value of the counter with control data, second comparing means for comparing the count value of the counter with speed error data, and AND having inputs of outputs of both comparing means A gate and a smoothing means for smoothing the output of the AND gate and supplying the smoothed output to the motor are provided.

[0008]

According to the present invention, as described above, when the speed at which the speed control effectively operates is reached, the influence of the N-bit control data can be immediately eliminated.

[0009]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram of one embodiment of the present invention. In the drawing, reference numeral 1 denotes a reel stand drive motor for selectively driving a supply reel stand or a take-up reel stand, and 2 denotes a rotation of this motor. A rotation detector that outputs an FG pulse having a frequency proportional to the speed, 3 is an FG amplifier that amplifies the FG pulse, 4 is a cycle measuring circuit that measures the cycle of the amplified FG pulse, and 5 is a cycle measuring circuit 4. An error that the measured FG pulse cycle has with respect to a reference cycle prepared so as to correspond to the optimum speed of each mode is represented by M shown in FIG.
This is a speed error data calculation circuit that calculates speed error data of (M: integer value) bits. Although the speed error data is significantly large immediately after the shift to the FF or REW mode, the error data gradually decreases with the acceleration of the motor 1 and eventually becomes substantially zero.

Further, at the same time, the system controller 6 instructs a mode shift from the stop mode to the FF / REW mode, and at the same time, the data gradually increases for a predetermined period T1 as shown in FIG. After this, N becomes a constant value.
A control data output circuit that outputs (N: integer value, M> N) bits of control data. Reference numeral 8 denotes a free-run M-bit counter that counts high-frequency clock pulses and generates an output as shown in FIG. is there.

By decoding the count value of the M-bit counter 8 with the speed error data and the control data,
Two PWM signals can be created. Where N
Bit data corresponds to the upper N bits of M bits,
The lower (MN) bits are ignored.

That is, the level of the control data from the control data generating circuit 7 is compared with the output of the counter 8 by the comparator 9, and the H-level comparison output is obtained as shown in FIG. can get. The comparison output D initially maintains a duty of 50%, and after the mode shift, the duty gradually increases, and after the period T1, the output is limited to the output limit PWM which is always at the H level (duty is 100%). is there.

Similarly, the speed error data from the speed error data calculation circuit 5 is level-compared with the output of the counter 8 by the comparator 10, and the H level comparison output is output during a period when the speed error data is larger. Of E. The comparison output E is maintained at the H level until the rotation period of the motor is shortened to some extent after the mode shift, that is, the duty output is maintained.
The duty is maintained at 100%, thereafter, the duty gradually decreases, and after the rotation cycle reaches a certain cycle, the speed control PWM is fixed to a certain duty (50%).

The comparison outputs D and E thus obtained are represented by A
The signal is input to the ND circuit 11, and the logical product of both PWM outputs is output as a composite PWM output. In the composite PWM, while the comparison output E immediately after the mode shift maintains the H level, the comparison output D is limited and the comparison output D appears as it is, and the duty gradually increases. Conversely, the comparison output D becomes H level, and the comparison output E appears as it is.

The synthesized PWM output is smoothed by the LPF 12, supplied to the reel drive motor 1 via the buffer 13 as the speed control output voltage G, and used for driving the motor.

The voltage level of the speed control output voltage G thus created gradually increases during the soft start period after the mode shift, and the motor 1 is started slowly and responsively accelerated accordingly. Thereafter, when the speed of the motor 1 is increased to some extent and the magnitude relation between the two PWMs of the comparison outputs D and E is inverted, for example, the comparison output D
Of the comparison output E at this time is 70%.
If the tee is also 70%, thereafter, the speed control period in which only the speed control system operates. That is, the duty of the comparison output E
The tee controls the motor 1 as a PWM output. Since the control data has no influence thereafter, there is no problem even if the output of the control data is interrupted or the duty is suddenly changed to 100%.

[0018]

As described above, according to the present invention, the time for performing any special processing on the motor control voltage in addition to the normal speed control at the time of mode transition is minimized, and only the speed control servo is quickly performed after the mode transition. Can control the tape speed.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart of one embodiment of the present invention.

FIG. 3 is a circuit block diagram of a conventional example.

FIG. 4 is a timing chart of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 reel drive motor 2 rotation detector 5 speed error data calculation circuit 7 N-bit data output circuit 8 M-bit counter 9 1st comparator 10 2nd comparator 11 AND gate 12 LPF

Claims (1)

(57) [Claims] 1. A reel stand drive motor for driving a reel stand, a rotation detector for outputting an FG signal having a frequency proportional to a rotation speed of the motor, and an error between a cycle of the FG signal and a reference cycle. Speed error data generating means for outputting as error data; N-bit data output means for outputting N (N: integer) -bit control data for maintaining a constant value after gradually increasing; and M (M: An integer, M> N) -bit counter; first comparing means for comparing the count value of the counter with the output of the control data output means; second comparing means for comparing the count value of the counter with the speed error data; An AND gate that receives the outputs of the two comparison means as inputs, and a smoothing means that smoothes the output of the AND gate and supplies the output to the motor as a drive control signal. Tape speed control circuit that.