JP2598068B2 - Parasitic current correction circuit - Google Patents
Parasitic current correction circuitInfo
- Publication number
- JP2598068B2 JP2598068B2 JP63042178A JP4217888A JP2598068B2 JP 2598068 B2 JP2598068 B2 JP 2598068B2 JP 63042178 A JP63042178 A JP 63042178A JP 4217888 A JP4217888 A JP 4217888A JP 2598068 B2 JP2598068 B2 JP 2598068B2
- Authority
- JP
- Japan
- Prior art keywords
- lateral
- transistor
- collector
- conductivity type
- parasitic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000003071 parasitic effect Effects 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は集積回路素子に発生する寄生電流によるラテ
ラルPNPトランジスタの不都合を解消するのに好適な寄
生電流補正に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a parasitic current correction suitable for solving the problem of a lateral PNP transistor due to a parasitic current generated in an integrated circuit device.
(従来の技術) 大電流駆動用として第2図に示す回路を造込んだ集積
回路が使用されているが、その概要を説明する。この大
電流駆動回路は対称的なA,Bからなり、しかもこの両方
が同時に出力されず、インバータと多段のダーリントン
接続により構成されている。(Prior Art) An integrated circuit incorporating the circuit shown in FIG. 2 is used for driving a large current, and its outline will be described. This large current drive circuit is composed of symmetrical A and B, and both are not output at the same time, and are constituted by an inverter and a multi-stage Darlington connection.
即ち、第2図に明らかなように入力IN−A,IN−Bには
順方向接続したダイオードQ51,Q55を設置し、VCC端子に
接続した抵抗A,Bの端部にはこのダイオードQ51,Q55に接
続した抵抗C,Dを接続し、更にPNPトランジスタQ52,Q56
のベースにもこのて抵抗C,Dを接続して夫々インバータ
を構成する。That is, the second input as is apparent in FIG. IN-A, IN-B established a diode Q51, Q55 connected forward, resistance A connected to the V CC terminal, the end portion of the B diode Q51 , Q55 and the PNP transistors Q52, Q56
The resistors C and D are also connected to the base of the inverter to form an inverter.
次にこのPNPトランジスタQ52,Q56のコレクタ端にはエ
ミッタ接地型NPNトランジスタQ53,Q54,Q57,Q58を接続し
て多段ダーリントン回路を構成するが、このPNPトラン
ジスタQ52,Q56のコレクタ端子とNPNトランジスタQ53,Q5
7のベース間には抵抗E,Fを、この抵抗E,Fとエミッタ接
地型NPNトランジスタQ54,Q58のベース間には抵抗G,Hを
設置する。Next, a multi-stage Darlington circuit is formed by connecting collector-grounded NPN transistors Q53, Q54, Q57 and Q58 to the collector terminals of the PNP transistors Q52 and Q56. , Q5
7, resistors E and F are provided between the bases, and resistors G and H are provided between the resistors E and F and the bases of the common-emitter NPN transistors Q54 and Q58.
エミッタ接地型NPNトランジスタQ54,Q58のコレクタ端
子は出力Out−A,Out−Bとしてモータコイルφ1,φ2に
接続し、出力Out−A,Out−Bには逆起電力吸収用クラン
プ ダイオードQA,QBを接続し更にその出力端子を連結
して構成するコンモン端子はモータコイルφ1,φ2の接
続線に結んでVDD端子として利用する。Common-emitter NPN transistor Q54, the collector terminal of the Q58 output Out-A, the motor coil phi 1 as Out-B, connected to phi 2, the output Out-A, counter electromotive force absorbing clamp diode QA in Out-B , QB, and the output terminal thereof are connected to form a common terminal, which is connected to the connection line of the motor coils φ 1 and φ 2 and used as a VDD terminal.
この入力IN−A,IN−Bにはハイ(High)とロウ(Lo
w)の電圧が印加されるが前述のように同時には出力さ
れないのが一つの特徴である。High (High) and low (Lo) are applied to these inputs IN-A and IN-B.
One feature is that the voltage of w) is applied but not output simultaneously as described above.
以上の大電流駆動用集積回路を形成するには半導体基
板にトレンチ アイソレイション(Trench Isolation)
やディープN+領域等の分離領域により区分された島領域
に抵抗とバイポーラトランジスタを夫々形成する方法が
一般的である。To form the large current driving integrated circuit described above, a trench isolation (Trench Isolation) is applied to the semiconductor substrate.
Generally, a method of forming a resistor and a bipolar transistor in an island region divided by an isolation region such as a deep N + region or the like is common.
しかし、この集積回路ではこの半導体基板と各不純物
領域間ではQLNAを入力とする接地された寄生素子が形成
されるのは不可避である。However, in this integrated circuit, it is inevitable that a grounded parasitic element having a QLNA as an input is formed between the semiconductor substrate and each impurity region.
(発明が解決しようとする課題) 前述の大電流駆動用集積回路はM結合を起こすモータ
に接続すると、そのOn−Offに伴ってコイルに逆起電力
電流が流れるので、出力トランジスタは瞬間的に逆方向
に流れてSub(基板)電位が浮いて寄生トランジスタがO
nする状況が発生して、スイッチング時に異常動作を起
こす。(Problems to be Solved by the Invention) When the above-described large current driving integrated circuit is connected to a motor that causes M coupling, a back electromotive force current flows through the coil in accordance with the on-off of the integrated circuit. Flows in the opposite direction, the Sub (substrate) potential floats, and the parasitic transistor becomes O
n occurs, causing abnormal operation during switching.
この異常状況を説明すると、 (1) 第2図に示した集積回路パターンにおいて、互
いに隣接して設置した回路A,Bの構造上クランプダイオ
ードQA,QBと基板(P-導電型)間には寄生Sub PNP Trが
形成され、又出力NPN Tr Q58のコレクタ、イオバータ用
PNP Tr Q52のベースと基板間にも寄生SubラテラルPNP T
rが発生し、図ではQLNAとして表示した。一方出力NPN T
r Q54のコレクタ、インバータ用PNP Tr Q56のベースと
基板間にも寄生SubラテラルPNP Trが発生し、図ではQ
LNBとして表示してある。This abnormal situation will be described as follows: (1) In the integrated circuit pattern shown in FIG. 2, due to the structure of the circuits A and B installed adjacent to each other, the clamp diodes QA and QB and the substrate (P - conductivity type) Parasitic Sub PNP Tr is formed and output NPN Tr Q58 for collector and ioverter
Parasitic Sub lateral PNP T between PNP Tr Q52 base and substrate
r occurred and is indicated as QLNA in the figure. On the other hand, output NPN T
r Parasitic Sub lateral PNP Tr also occurs between the collector of Q54, the PNP Tr for inverter and the base of Q56 and the substrate.
Indicated as LNB .
(2) このような回路の入力IN−Aにハイ(High以下
Hと省略して記載する)がロウ(Low以下Lと省略して
記載する)を、入力IN−Bに同じく“H"が“L"の信号を
入力するが、IN−Aが“H"になるとQ52,Q53,Q54がOffし
てOut−Aが“H"になる。このためにコイルφ1には逆
起電力が生じ、クランプダイオードQAに寄生Sub PNP Tr
を通してISUB電位を浮かせる。(2) The input IN-A of such a circuit has a high (High and abbreviated as H) and a low (Low and abbreviated as L) and the input IN-B has "H" as well. A signal of "L" is input, but when IN-A becomes "H", Q52, Q53 and Q54 are turned off and Out-A becomes "H". It occurs back electromotive force in the coil phi 1 to the parasitic Sub PNP Tr in clamp diode QA
To float the ISUB potential.
(3) Sub電位の浮上により隣接して設置するOut−B
(逆相で“L"になっている)の出力IrQ58のコレクタに
接続する寄生ラテラルNPN Tr QLNAを動作させる。このQ
LNAがOnするとラテラルPNP Tr Q52のベース電位が下が
り、IN−Aが“H"にも拘らずQ52,Q53,Q54がOnし、Out−
Aは“L"に落ちる。(3) Out-B installed adjacent to the floating of Sub potential
Operate the parasitic lateral NPN Tr Q LNA connected to the collector of output IrQ58 (which is “L” in opposite phase). This Q
When the LNA turns on, the base potential of the lateral PNP Tr Q52 drops, and Q52, Q53, and Q54 turn on and Out-
A falls to "L".
(4) IN−Aが“L"になるとコイルφに電流が流れて
逆起電力が泣くなり、Subに流れる電流も消えて、Sub電
位が下がるので、寄生ラテラルNPN Tr QLNAはOffしてPN
P Tr52のベース電位も“H"に戻る。(4) When IN-A becomes “L”, a current flows through the coil φ, the back electromotive force crys, the current flowing through the Sub disappears, and the Sub potential drops. Therefore, the parasitic lateral NPN Tr Q LNA is turned off. PN
The base potential of P Tr52 also returns to “H”.
(5) Q52がOffすると、Out−Aは再び“H"になり
(2)〜(4)の動作を繰返す。(5) When Q52 is turned off, Out-A becomes "H" again, and the operations of (2) to (4) are repeated.
(6) この帰還ループはコイルに蓄積された逆起電力
エネルギーが消滅するまで繰返され発振現象を引起こ
す。(6) This feedback loop is repeated until the back electromotive force energy stored in the coil disappears, causing an oscillation phenomenon.
この例とは逆に入力IN−Bに“H"、IN−Aに“L"電位
を印加すると前述の説明と全く逆の駆動が起きるので説
明は割愛する。Contrary to this example, when a potential "H" is applied to the input IN-B and a potential "L" is applied to the input IN-A, the driving which is completely opposite to that described above occurs, and the description is omitted.
このように集積回路に適用するラテラルPNP Tr Q60は
第3図に示したように何等補正を施していない。Thus, the lateral PNP Tr Q60 applied to the integrated circuit is not subjected to any correction as shown in FIG.
本発明は上記難点を除去する新規な寄生電流補正回路
に関し、特に集積回路に設置する分離領域と半導体基板
間に発生する寄生効果に基づく電流を補正するものであ
る。The present invention relates to a novel parasitic current correction circuit that eliminates the above-mentioned difficulties, and more particularly to a circuit that corrects a current based on a parasitic effect generated between an isolation region provided in an integrated circuit and a semiconductor substrate.
(課題を解決するための手段) この目的を達成するのに本発明では、半導体基板に形
成するある導電型のラテラルトランジスタに近接してエ
ミッタ同志を接続する同一導電型でベースオープンの他
のラテラルトランジスタを設置し、この両トランジスタ
に対応しかつ近接して逆導電型のエミッタ接地型ラテラ
ルトランジスタを形成し、他のラテラルトランジスタの
コレクタを逆導電型の一方のエミッタ接地型ラテラルト
ランジスタのベース及びコレクタに接続し、他方の逆導
電型のエミッタ接地型ラテラルトランジスタのベースを
他のラテラルトランジスタのコレクタに、コレクタをあ
る導電型のラテラルトランジスタのコレクタに接続する
手法を採用する。(Means for Solving the Problems) In order to achieve this object, according to the present invention, another lateral transistor of the same conductivity type and base open which connects emitters in close proximity to a certain conductivity type lateral transistor formed on a semiconductor substrate is provided. A transistor is provided, and a grounded-emitter lateral transistor of the opposite conductivity type is formed adjacent to and close to both transistors, and the collector of the other lateral transistor is connected to the base and collector of one of the grounded-lateral emitter transistors of the opposite conductivity type. , The base of the other opposite-conductivity-type grounded-lateral transistor is connected to the collector of another lateral transistor, and the collector is connected to the collector of a lateral transistor of a certain conductivity type.
(作 用) この寄生電流補正回路は寄生電流が流れる集積回路に
設置するラテラルPNP Trに近接して同等の特性を持つ他
のラテラルPNP Trを形成し、それに発生する寄生電流に
より本来の回路に使用するラテラルPNP Trに発生する寄
生電流をキャンセルする手法を採用する。(Operation) This parasitic current correction circuit forms another lateral PNP Tr with the same characteristics in close proximity to the lateral PNP Tr installed in the integrated circuit where the parasitic current flows, and the parasitic current generated by it forms the original circuit. A method of canceling the parasitic current generated in the lateral PNP Tr used is adopted.
(実施例) 第1図により本発明の実施例を詳述する。(Example) An example of the present invention will be described in detail with reference to FIG.
図に示すようにこの回路では互いに近接してしかも同
一の特性を持ったある導電型のラテラルPNPトランジス
タQ1,Q2は半導体基板(図示せず)に常法に従って設置
する。その一方であるQ2はベースオープンと、両トラン
ジスタのエミッタを接続する。更にこの両トランジスタ
Q1,Q2のコレクタ端子は夫々に対応して設置する逆導電
型のラテラルNPNトランジスタQ3,Q4のコレクタ端子に接
続し、ある導電型のラテラルPNPトランジスタQ2のコレ
クタ端子はラテラルNPNトランジスタQ3,Q4のベースに接
続し、更にある導電型のラテラルPNPトランジスタQ1の
コレクタ端子を出力端子とする。As shown in this figure, in this circuit, lateral PNP transistors Q1 and Q2 of a certain conductivity type which are close to each other and have the same characteristics are installed on a semiconductor substrate (not shown) in a conventional manner. On the other hand, Q2 connects the base open and the emitters of both transistors. Furthermore, these two transistors
The collector terminals of Q1 and Q2 are connected to the collector terminals of opposite conductive lateral NPN transistors Q3 and Q4, respectively, and the collector terminal of a certain conductive lateral PNP transistor Q2 is connected to the lateral NPN transistors Q3 and Q4. It is connected to the base, and the collector terminal of a lateral PNP transistor Q1 of a certain conductivity type is used as an output terminal.
この構造を持つ回路接続では逆導電型のラテラルNPN
トランジスタQ3,Q4はカレントミラ回路を構成してい
る。In circuit connection with this structure, lateral NPN of reverse conductivity type
The transistors Q3 and Q4 constitute a current mirror circuit.
従ってある導電型のラテラルPNPトランジスタQ1に寄
生効果による寄生電流IPが流れるとQ2にも同様な電流が
流れる。そのQ2の電流IPをカレントミラ回路を構成する
ラテラルNPNトランジスタQ3,Q4で折り返して、ある導電
型のラテラルPNPトランジスタQ1に発生した寄生電流を
このQ3でGNDに逃がせば、IOUTからは本来の回路でドラ
イブされた電流IINに比例することになる。Therefore, when a parasitic current I P due to a parasitic effect flows through a certain conductivity type lateral PNP transistor Q1, a similar current flows through Q2. The current I P of the Q2 are turned back at lateral NPN transistors Q3, Q4 constituting a current mirror circuit, if Nigase parasitic current generated in the lateral PNP transistor Q1 is conductive to GND in this Q3, originally from I OUT Will be proportional to the current I IN driven by the circuit.
この関係を以下の式により示す。 This relationship is shown by the following equation.
IOUT=β×(IIN+IP)−I1 I2=β×IP ここでQ3,Q4のβが非常に大きければI2≒I1 IOUT=βIIN+βIP−I1 =βIIN β:ラテラルPNPトランジスタQ1,Q2の電流増幅率 IP:寄生効果により発生する寄生電流 IOUT:出力 上式によりラテラル PNPトランジスタを適用した回路
でドライブされた電流IINに比例した電流が出力される
ことが明らかである。I OUT = β × (I IN + I P ) −I 1 I 2 = β × I P Here, if β of Q3 and Q4 is very large, I 2 ≒ I 1 I OUT = βI IN + βI P −I 1 = βI IN β: Current amplification factor of lateral PNP transistors Q1 and Q2 I P : Parasitic current generated by parasitic effect I OUT : Output Current that is driven by circuit using lateral PNP transistor according to the above equation Outputs current proportional to IN It is clear that it will be.
なお前述の補正回路を備えた集積回路は熱酸化膜を積
層して設置した半導体基板にいわゆる分離領域により電
気的に分離した島領域を形成し、この各島領域に抵抗と
トランジスタを別個に造込む公知の方法によって製造す
る。In the integrated circuit provided with the above-described correction circuit, island regions electrically separated by so-called separation regions are formed on a semiconductor substrate on which a thermal oxide film is laminated, and a resistor and a transistor are separately formed in each island region. It is manufactured by a known method.
このように本発明では前述のように半導体基板に形成
する分離領域により電気的に分離した島領域に集積回路
を形成し、この分離領域と半導体基板間において発生す
るのが不可避なラテラル型トランジスタの寄生電流をこ
れに隣接して同一特性のラテラル型トランジスタのセン
サとして設置し、かつこの両素子に対応して逆導電型の
ラテラル型トランジスタを配置して形成するカレントミ
ラ回路によって折返すことにより、本来の回路によって
得られる電流に比例した出力が得られる。As described above, according to the present invention, as described above, an integrated circuit is formed in an island region electrically separated by the separation region formed in the semiconductor substrate, and the lateral type transistor which is inevitable to occur between the separation region and the semiconductor substrate is formed. By installing a parasitic current adjacent thereto as a sensor of a lateral transistor having the same characteristics, and turning it back by a current mirror circuit formed by arranging a lateral transistor of the opposite conductivity type corresponding to both elements, An output proportional to the current obtained by the original circuit is obtained.
従って大電流駆動用集積回路にこの補正回路を適用す
ると、前述の寄生電流をキャンセル可能となるので、例
えばモータ制御に適用しても本来の特性を長期にわたっ
て稼働させることができる大きな利点がある。Therefore, when this correction circuit is applied to a large-current driving integrated circuit, the above-described parasitic current can be canceled, so that there is a great advantage that the original characteristics can be operated for a long time even when applied to motor control, for example.
第1図は本発明に係わる寄生電流補正回路の回路図、第
3図は従来のその要部を示す回路図、第2図はモータに
適用した大電流駆動用集積回路図である。FIG. 1 is a circuit diagram of a parasitic current correction circuit according to the present invention, FIG. 3 is a circuit diagram showing a main part of the conventional circuit, and FIG. 2 is a diagram of an integrated circuit for driving a large current applied to a motor.
Claims (1)
ルトランジスタに近接して寄生電流センサとして同一導
電型を持ちエミッタ同志を接続する他のラテラルトラン
ジスタを設置し、そのベースをオーブンとし、この両ト
ランジスタに近接かつ対応する逆導電型のエミッタ接地
型ラテラルトランジスタを設置し、他のラテラルトラン
ジスタのコレクタを逆導電型の一方のエミッタ接地型ラ
テラルトランジスタのベースならびにコレクタに接続
し、他方の逆導電型のエミッタ接地型ラテラルトランジ
スタのベースを他のラテラルトランジスタのコレクタ
に、コレクタをある導電型のラテラルトランジスタのコ
レクタに接続することを特徴とする寄生電流補正回路。1. A lateral transistor which has the same conductivity type as a parasitic current sensor and is connected to emitters is installed near a certain lateral conductivity type transistor formed on a semiconductor substrate. An opposite-grounded lateral transistor of the opposite conductivity type is installed near and corresponding to the transistor, the collector of the other lateral transistor is connected to the base and collector of one of the opposite- conductivity type lateral-emitter lateral transistors, and the other is the opposite conductivity type. And a collector connected to a collector of another lateral transistor, and a collector connected to a collector of a lateral transistor of a certain conductivity type.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63042178A JP2598068B2 (en) | 1988-02-26 | 1988-02-26 | Parasitic current correction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63042178A JP2598068B2 (en) | 1988-02-26 | 1988-02-26 | Parasitic current correction circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01217959A JPH01217959A (en) | 1989-08-31 |
JP2598068B2 true JP2598068B2 (en) | 1997-04-09 |
Family
ID=12628732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63042178A Expired - Fee Related JP2598068B2 (en) | 1988-02-26 | 1988-02-26 | Parasitic current correction circuit |
Country Status (1)
Country | Link |
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JP (1) | JP2598068B2 (en) |
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KR100913141B1 (en) | 2004-09-15 | 2009-08-19 | 삼성전자주식회사 | An evaporator using micro- channel tubes |
-
1988
- 1988-02-26 JP JP63042178A patent/JP2598068B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH01217959A (en) | 1989-08-31 |
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