JP2598046B2 - Packet switch - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a packet switch used for a packet switch, which is an important element constituting a communication network.

[Conventional technology]

A bus matrix switch has been known as a conventional packet switch. FIG. 8A is a block diagram showing the configuration of such a conventional bus matrix switch.

In the figure, the input packets from the lines 101 to 10n are:
Necessary processing is performed in the input packet processing devices 301 to 30n, and a header designating any one of the output packet processing devices 311 to 31m is added thereto, and the packet is sent out onto the row buses 201 to 20n. The cross-point elements (XE) 411 to 4 nm monitor packets transmitted on the row-direction bus, and the cross-point emergent having the number of 4ij is a packet having a header destination of j (the output packet processing device 31j). Only the forwarded packet) is temporarily stored in a buffer in the element described later.

When the cross-point elements 411 to 4 nm accumulate packets in this way, they issue a bus use request for packet transmission to the column direction bus. Bus control circuit 321-32m
Detects and controls a request from each crosspoint element connected to the bus for each column direction bus, gives a transmission right to one crosspoint element, and transmits a packet.

FIG. 8B is a block diagram showing a configuration of the cross point element XE in FIG. 8A.

In FIG. 8 (b), the header added to the packet (data) input from the row direction bus 20n is monitored by the control circuit 401, and only the packet having the specific header is buffered as described above. Captured by 400.
A buffer is a so-called FIFO that outputs data to the input side.
(First-in first-out memory). The column direction bus includes a data bus 211-1 and a control bus 211-2. The control bus 211-2 transmits control signals such as request / permission, and the data bus 211-1 transmits packets (data).

[Problems to be solved by the invention]

As described above, the conventional bus matrix switch has (nxm) crosspoint elements to realize an nxm switch having n inputs and m outputs. Furthermore, these crosspoint elements have buffers for several packets. Therefore, as n and m increase, the number of crosspoint elements increases, and the buffer amount also increases nxm times.

Further, since the buffers in these cross point elements are independent of each other, if the buffer of one cross point element overflows, it cannot be relieved by the buffer of another cross point element. Therefore, it is necessary that the buffer of each cross point element has a sufficient capacity so as not to overflow, and this is a problem particularly in the case of a large capacity packet switch in which n and m are large.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the problem that a conventional packet switch has a buffer for each cross-point element, making it difficult to configure a large-capacity packet switch. To provide.

[Means for solving the problem]

To achieve the above object, according to the present invention, a crosspoint element is arranged at each of matrix-like intersections formed by crossing a plurality of input lines and a plurality of output lines, and a packet input from the input line is input to the input line. After temporarily storing in a buffer provided on the line, the header information added to the packet is detected in the buffer and transmitted on the input line toward the crosspoint element. A particular cross-point element monitoring the input line detects and receives the header information, thereby closing the junction between the input line and the output line in the element, and issuing a transmission command from the element to the buffer. By issuing
A packet switch that outputs a packet on an output line by transmitting a packet to which the header information is added from the buffer and passing through the cross point, wherein the cross point element is transmitted from the buffer on an input line. Has a means for monitoring that information on whether or not there is a subsequent packet is attached to the arriving packet, and if there is a subsequent packet, the once-closed junction is maintained as it is. Subsequent packets are allowed to pass to the output line, and packet processing devices are provided on the input line and the output line, respectively. The packet processing device inputs the packets.
A FIFO, and means for changing the speed of the packet output from the FIFO given the speed information of the packet, enabling conversion of packets having different speeds, further comprising a bus control device on an output line, The control device monitors the congestion state of each buffer provided on the input line and the vacancy of the output line. I tried to make it.

[Action]

The present invention is based on the premise that a buffer is provided on the input line, not at each crosspoint, and furthermore, the packet length can be made variable, multi-packet exchange can be efficiently realized, and high-speed switching of different packets can be performed. It differs from the prior art in that it can be replaced. Also, the configuration of this input buffer is configured so that it can be shared by a plurality of input lines, and it is characterized by increasing the grouping effect so as to prevent call loss due to packet congestion as much as possible. The method and the configuration are different from those of the related art in which the call loss is prevented by increasing the length.

〔Example〕

FIG. 1A is a block diagram showing a configuration of a packet switch useful for understanding the embodiment of the present invention. In the figure, 101 to 10n are input lines, 111 to 11m are output lines, 201 to 20n are row direction buses, 211 to 21m are column direction buses, 30
1 to 30n are input packet processing devices, 311 to 31m are output packet processing devices, and 411 to 4nm are cross-point elements (X
E), 321 to 32m are bus controllers, and 501 to 50n are buffers (FIFO) for temporarily storing packets.

FIG. 1 (b) is a block diagram showing the configuration of the cross point element (XE) in FIG. 1 (a). First
In FIG. 2B, reference numeral 401 denotes a control circuit, and 402 denotes a gate.

The operation will be described with reference to FIGS. 1 (a) and 1 (b). Packets input from the input lines 101 to 10n are subjected to necessary processing in the input packet processing devices 301 to 30n, added with a header specifying one of the output packet processing devices 311 to 31m, and added to the buffers 501 to 50n. Stored. When the packets are stored, information indicating that the packets have arrived and header information having the number of the output packet processing device are sent to the row buses 201 to 20n. In this case the row bus 201
21n comprises data buses 201-1 to 20n-1 for transmitting data and control data buses 201-2 to 20n-2 for transmitting and receiving control information.

The cross-point element (XE) 411-4 nm monitors the control data bus in the row direction, and the cross-point element having the number 4ij stores the header whose destination information is j (header toward the output packet processing device 31j). Upon receiving the request, it issues a bus use request for packet transmission to the column direction bus.

The bus control circuits 321 to 32m detect and control a request from each cross point element connected to the bus for each column direction bus, give a transmission right to one cross point element, and transmit a transmission permission signal to the cross point element. In the cross point element which receives the transmission permission signal and transmits to the gate 402 through which the packet data can pass.
And the row direction data bus 201-1 and the column direction data bus 2
11-1 and the input data buffers 501-5
Send a send command to one of 0n. In response to this command, the packet data in the input data buffer is transmitted to the output packet processing device.

As described above, there is no buffer for storing packets on the matrix constituted by the cross point elements. Therefore, the configuration of the cross point element is simpler than that of a conventional packet switch of a type having a buffer at each cross point, and at the same time, the buffer can be shared in the row direction. Compared to the total buffer amount required for the conventional switch as a whole, it is possible to greatly save.

Based on the above, FIGS. 2A and 2B are diagrams for explaining an embodiment of the present invention. FIG. 2 (a) is a block diagram having almost the same contents as the configuration diagram of the cross point element shown in FIG. 1 (a), but is shown again here for convenience of explanation.

In FIG. 2A, the control circuit 401 in the crosspoint element monitors the header of the packet. At the same time as the packet is connected, the control circuit 401 also monitors the last bit of the packet connection. As shown in FIG. 2 (b), this last bit is a bit indicating whether or not a succeeding packet is continued, and when the last bit is "1", the gate 40 in the cross point element
Without closing 2, successive packets are passed and output to the output packet processing device.

When the last bit is "0", the gate 402 is closed and an open command is sent to the bus control circuit through the vertical control line 211-2. Each packet has a fixed length, and the position of the last bit is determined by a counter. In this way, multi-packet information composed of a plurality of packets can be switched and connected. That is, packets of fixed length × n can be easily processed.

FIG. 3 is a diagram for explaining another embodiment of the present invention. That is, FIG. 3 is a block diagram showing a main part of the output packet processing device of the packet switch in FIG. 1 (a). When the header information includes information indicating the speed of the packet, the cross point element and the bus control unit generate a cross point in the element as described above by the operation of the bus control unit.
The speed information is transmitted via the data bus 211-2 to determine the speed of the output line.

The FIFO in FIG. 3 is for absorbing jitter (time axis fluctuation) generated in the switch. The speed information transmitted via the data bus 211-2 is used by the selection circuit SeL to output a desired one of clocks (f _{0 to} f ₃ ) of various speeds generated from the clock generation circuit Cen. The data is selected and supplied to the FIFO and the flip-flop F / F, and the transmission speed on the output line 111 is determined.

Further, the input packet processing device and the input buffer are also provided with a clock generation circuit and a FIFO so that the speed is variable.

FIG. 4 is a block diagram showing a configuration example of the buffer 501 in FIG. 1 (a). In FIG. 4, when certain header information 501-1 is transmitted to the row bus 201-2 via the AND gate A and the changeover switch SW, and no transmission permission is returned from the cross point element at that time, Another header sends the information, for example, 501-2 again to the row bus 201-2 via the AND gate A, the changeover switch SW, and waits for the permission of sending from the cross point element.

In this case, the header information transmission 501-
1 is abandoned once and the second header information transmission 501-2
After the end, transmission is performed again. The cross point element also recognizes that the header is a packet to be transmitted after the row signal, and discards the packet if it cannot be connected to the output line without transmission permission from the output control circuit. In this way, a plurality of packets can be switched and connected with priority over a packet having an output line.

FIG. 5 (a) is a block diagram showing another embodiment of the present invention.

In FIG. 5A, input data buffers 501 to 50n
Information lines 601-6 toward the column-oriented bus controllers 321-32m
0n. The information lines 601 to 60n transmit the use status of the input data buffer, that is, the congestion information of the buffer, as data to the bus control device. In the bus control device, the cross-point element 41 is provided so that the packets congested in the buffer are preferentially transmitted to the output line.
Send transmission command to 1-4nm. Thus, overflow due to congestion of the input data buffers 501 to 50n can be reduced.

FIG. 5 (b) shows the bus control device 32 in FIG. 5 (a).
It is the circuit diagram which showed the specific example of any one, for example, 321 of 1-32m.

The circuit operation will be described with reference to FIGS. 5 (a) and 5 (b). It is assumed that the input buffer 501 is congested.
Then, a signal enters the AND gate A1 through the control line 601. If the AND gate A1 is open at that time, the signal passes through the AND gate A1 and sets the flip-flop F1.

What this means is that several of the 501-50n input buffers may be congested at the same time. Although it has priority control, the control line
When 601 of 601 to 60n sends a signal as described above, the flip-flop F1 is set, and the set output (high) is turned to low by the NOR gate and applied to the AND gates A1 to A3, The AND gates A1 to A3 which were in the open state until then are closed. Therefore, after that, control line 60
No matter which of 2 to 60n sends a signal, the signal cannot pass through the AND gate and the flip-flop cannot be set.

Thus, only one, in the present case, only the flip-flop F1 is set and its Q output is high, but it opens the AND gate A4 and outputs the output free information 31
If any of 1 to 31 m, for example, the output packet processing device 311 is empty, empty information 311 indicating that arrives via a control line not shown, passes through the AND gate A4,
The transmission permission signal 211-2 is sent to the control unit (see FIG. 1 (a)) of the corresponding cross point element, whereby the contents of the buffer 501 can be sent to the output side.

FIG. 6 is a circuit diagram showing still another embodiment of the present invention. In the figure, a packet switch having n input lines and m output lines is composed of (n + 1) × m crosspoint elements, (n + 1) input buffers, and an n: 1 selector 701.

Packet traffic concentrates on a certain input line 10i,
When the buffer 50i becomes full and overflows (or overflows), a packet loss occurs.
In order to avoid this, grasp the usage status of buffers 501 to 50n and limit the use of congested buffer 50i.
The packet on the input line 10i is transmitted to the buffer 50 (n + 1) by the n: 1 selector 701.

As a result, it is possible to rescue the packets that have been lost. Also, this spare buffer 50
Since (n + 1) can be shared by the packets on each of the input lines 101 to 10n, a larger grouping effect can be obtained and the buffers can be used more efficiently than simply increasing the capacity of all the buffers 501 to 50n. .

FIG. 7 is a block diagram showing still another embodiment of the present invention. This embodiment corresponds to an apparatus having an n × n space switch 801 between the packet processing devices 301 to 30n and the buffers 501 to 50n of the packet switch shown in FIG.

Packets of a certain line arrive intensively and buffers 501-5
In accordance with the congestion state of 0n, the n × n switches 801 are connected to flatten the use state of the buffer. Also,
Since this is equivalent to sharing the buffer memory with n input lines, the throughput and efficiency of packet switching increase due to the grouping effect.

〔The invention's effect〕

As described above, since the buffer is provided on the input line, and the cross-point element is constituted only by the gate for passing the packet, the amount of hardware in the buffer is small, the packet length can be changed, and packet exchange at different speeds can be performed. There is an advantage that the effect can be achieved in a unified manner, and a buffer grouping effect can be achieved by managing the buffers.

[Brief description of the drawings]

FIG. 1 (a) is a block diagram showing a configuration of a packet switch useful for understanding an embodiment of the present invention, and FIG. 1 (b).
2 is a block diagram showing a configuration example of a cross point element in FIG. 1 (a), FIG. 2 (a) is a block diagram showing a configuration example of the same cross point element, and FIG. FIG. 3 is a block diagram showing a configuration example of an output packet processing device, FIG. 4 is a block diagram showing a configuration example of a buffer, and FIG. 5 (a). 5 is a block diagram showing another embodiment of the present invention, FIG. 5 (b) is a circuit diagram showing a configuration example of the bus control device in FIG. 5 (a), and FIG. 6 is still another embodiment of the present invention. Block diagram showing an example, FIG.
The figure is a block diagram showing a main part of still another embodiment of the present invention,
FIG. 8A is a block diagram showing a configuration example of a conventional packet switch, and FIG. 8B is a block diagram showing details of a main part in FIG. 8A. Explanation of reference numerals 101 to 10n ... input line, 111 to 11m ... output line, 201 to 2
0n: Row-direction bus, 211-21m ... Column-direction bus, 301-30n
... Input packet processing device, 311-31m ... Output packet processing device, 321-32n ... Bus control circuit, 411-4nm ... Cross point element, 501-50n ... Input data buffer, 601-160n ... Output Data buffer information line, 701 ...
... n: 1 selector, 801 ... n × n switch

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-163438 (JP, A) JP-A-62-136948 (JP, A) Oyama, Tonami, Honda "Characteristics of matrix switch for packet switching equipment" Showa 58 IEICE General Conference, 1683 Oyama, Ishino, Honda, “Matrix Switch for Packet Switching”, 1982 IEICE Communication Division National Convention 1-131 DIEUDONE M. QUIN NQUIS "SWITCHING TE CHNIQUES FOR ASYN- CHRONOUS TIME DIVI SION MULTIPLEXING (OR FAST PACKET SW ITCHING)" ISS87 MARK J. KAOL MICH AEL G. HLUCHYJ SAMU EL P. MORGAN (AT & T BELL LABORATORIES) "INPUT VS OUTPUT QUEUEING ON A SPA CE-DIUSION PACK SWITCH" GLOBECOM86

Claims (2)

(57) [Claims] A cross point element is arranged at each of intersections in a matrix formed by crossing a plurality of input lines and a plurality of output lines, and a packet input from the input line is provided on the input line. Once stored in the buffer, the header information added to the packet is detected in the buffer and transmitted on the input line toward the crosspoint element, and the input line is monitored to detect specific header information. A particular crosspoint element has detected and received the header information,
Thereby, the junction between the input line and the output line in the element is closed, and a transmission command is issued from the element to the buffer, so that the packet with the header information is transmitted from the buffer and In a packet switch for outputting a packet on an output line by passing a point, the cross-point element is provided with information on whether or not a subsequent packet is present in an incoming packet from the buffer on the input line. If there is a subsequent packet, and if there is a subsequent packet, keep the closed junction once closed and pass the subsequent packet to the output line, on the input line and on the output line. Each has a packet processing device, and the packet processing device has an FI for inputting a packet.
FO and means for changing the speed of the packet output from the FIFO given the speed information of the packet, and enabling the exchange of packets having different speeds, and comprising a bus control device on an output line, The bus control device includes:
It monitors the congestion state of each buffer provided on the input line and the degree of vacancy of the output line, and preferentially transmits packets of such a buffer to the output line as soon as the output line becomes free. Characterized packet switch. 2. The packet switch according to claim 1, wherein said packet switch comprises a packet switch of an input line n and an output line m, and said buffer provided on an input line comprises (n + k) buffers. Buffer, the crosspoint element is composed of (n + k) × m crosspoint elements, and k buffers are represented by n
It is used by sharing the input line of this book, and the line of the line that is frequently used and the buffer is likely to overflow is connected to the redundant buffer to reduce the packet loss due to the buffer overflow. (Where n, m, and k are arbitrary integers).