JP2596944B2 - Television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of normalizing an input video signal according to the amount of noise.
The present invention relates to a high-definition television receiver that switches an irregular determination criterion.

[Related Art] In a digital television receiver, various processes such as YC separation and motion correction are performed in synchronization with other circuits using a so-called system clock signal. Generally, such a system clock signal is obtained by frequency-multiplying a continuous wave signal obtained by an APC (automatic phase control) circuit or the like based on a color burst signal, and quadrupling the subcarrier frequency phase-locked to the color burst signal. (Hereinafter, this clock signal is referred to as a burst lock clock signal) having a frequency of 4fsc. Such a burst-locked clock signal has a television standard signal defined as a standard because the video signal does not include jitter (time-axis fluctuation component) with respect to a video signal broadcast on television on the air or the like. The predetermined number accurately corresponds to 1H (horizontal synchronization period), and various processes can be executed in synchronization.

However, recent television receivers are sometimes used by being connected to a video tape recorder or a video disc player. Video signals from such devices can be caused by friction between the head drum and magnetic tape,
There is jitter due to friction between the disc and the turntable or uneven rotation of the motor (hereinafter, a video signal having jitter is referred to as an irregular video signal, and a video signal having almost no jitter in contrast thereto. Is called a regular video signal). When a burst-locked clock signal is formed for such an irregular video signal, the number of clock signals for 1H (one horizontal scanning cycle) is not constant, and various processes cannot be executed in synchronization. .

Therefore, conventionally, a circuit for detecting whether an incoming video signal is an irregular video signal or a regular video signal is provided, and in the case of a regular video signal, a burst lock clock signal is used as a system clock signal, and the On the other hand, a clock signal obtained by frequency-multiplying a horizontal synchronizing signal separated from a video signal (hereinafter referred to as an H-lock clock signal) is used as a system clock signal to execute various processes. Proposed.

[Problems to be Solved by the Invention] Conventionally, whether a video signal is a normal video signal or an irregular video signal is determined by detecting the number of burst lock clock signals in one field period of an incoming video signal. It is performed depending on whether the number is within a predetermined range.

However, when the electric field is weak, a large amount of noise is mixed in the regular video signal obtained from the television broadcast wave due to the weak electric field, and this noise causes the burst lock clock signal and the synchronization separation circuit to cause a noise. The relative relationship between the separated vertical and horizontal synchronization signals is disturbed, the field period determined by the separated vertical synchronization signal fluctuates from the normal period, or the video signal discriminating circuit improperly converts the input video signal. As a result, the H-locked clock signal may be adopted as the system clock. However, for an input video signal determined to be an irregular video signal due to the mixed noise in such a weak electric field state, H
It is a fact that the clock signal of the burst lock is much more stable than the clock signal of the lock, and although the adoption of the burst lock clock signal suitable for the system clock is natural, The apparatus accepts the determination result of the video signal determination circuit as it is and uses the H-locked clock signal. As a result, various signal processings, particularly color demodulation processing, lack accuracy, and unnecessary image quality deterioration is caused. And so on.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is a television receiver which can accurately determine whether a video signal is an irregular video signal or a regular video signal and can appropriately select a system clock signal. The purpose is to provide.

Means for Solving the Problems In order to solve the above problems and to achieve the above object, the present invention provides a method for controlling the number of clock signals phase-locked to a color burst signal in one field period or a period several times as long as the number of times. Is determined, and it is determined whether or not the input video signal is a normal video signal.If the input video signal is a normal video signal, a clock signal phase-locked to the color burst signal is output. A video signal discriminating circuit for adopting the clock signal phase-locked to the synchronization signal as a system clock, and a threshold value discrimination between the magnitude of a field difference signal or a frame difference signal in a vertical synchronization pulse period of the input video signal, A noise amount discriminating means for discriminating the amount of noise contained in the input video signal; Threshold value setting means for changing a threshold value used as a determination reference of the video signal determination means, and setting the threshold value to be larger or smaller as the amount of noise is larger. It is.

[Operation] According to the present invention, the video signal discriminating circuit discriminates the threshold value of the number of clock signals phase-locked to the color burst signal in one field period or a multiple thereof, and determines whether the input video signal is a regular video signal. Whether the clock signal phase-locked to the color burst signal or the clock signal phase-locked to the horizontal synchronization signal is adopted as the system clock, and the amount of noise included in the input video signal determined by the noise amount determination means Is changed based on the amount of the video signal. This relaxes the criterion for a normal video signal at the time of a weak electric field or the like, prevents the normal video signal from being erroneously determined to be a non-regular video signal, and avoids unnecessary image quality deterioration accompanying signal processing such as color demodulation processing. Can be.

Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention, and FIGS. 2 and 3 are timing charts of respective parts of the circuit shown in FIG.

In FIG. 1, a burst lock clock signal CK shown in FIG. 2A formed by a burst lock type clock generation circuit (not shown) is supplied to the counter circuit 1 as a clock signal. The counter circuit 1 is also provided with a pulse signal PUL1 which falls for one cycle of the clock signal CK during the vertical synchronization period shown in FIG. 2 (B) as a reset signal, and at the falling edge of this pulse signal PUL1. It has been made to be reset.

The count value CNT of the counter circuit 1 is given to a latch circuit 2 having a D-type flip-flop circuit configuration. The pulse signal shown in FIG. 2 (C), which rises for a period of one cycle of the clock signal CK before the fall of the pulse signal PUL1 as the latch command signal, is supplied to the latch circuit 2.
PUL2 is supplied, and the latch operation is performed at the falling edge.

Here, the pulse signals PUL1 and PUL2 are formed in synchronization with the clock signal CK based on the vertical synchronization signal separated from the video signal, and have a period of one field of the video signal (exactly). Has an error of ± 1 clock cycle).

Accordingly, the counter circuit 1 is reset at the falling edge of the pulse signal PUL1, and the latch circuit 2 is latched at the falling edge of the pulse signal PUL2.
Is the clock signal CK for one field period of the input video signal
Represents the number of.

This latch signal LAT1 is applied to the subtraction circuit 3. The subtraction circuit 3 is also supplied with a reference signal REF1 representing the number of clock signals CK corresponding to one regular field period.
Thus, the number of clock signals CK for one field period of the input video signal (LAT1) and the number of clock signals CK corresponding to one regular field period (RE
A difference signal SUB1 from F1) is output.

The difference signal SUB1 is converted into an absolute value via an absolute value circuit 4 and is supplied to a comparison circuit 5. The comparison circuit 5 is also provided with a reference signal REF2 from a noise level discrimination circuit 6, which will be described later. When the absolute value signal ABS1 is larger than the reference signal REF2, the comparison circuit 5 takes a logic "H" representing an irregular video signal, When the absolute value signal ABS1 is smaller than the reference signal REF2, a video signal discrimination signal S1 having a logic "L" representing a normal video signal is output.

This is because, in a non-regular video signal, unlike a regular video signal, one field period is a regular one due to jitter.
It is significantly different from the field period, and the different period is represented by the number of clock signals CK, and the number (absolute value signal ABS1) is based on the fact that it becomes equal to or more than a predetermined value (reference signal REF2).

However, even if a normal video signal contains a lot of noise, the normal video signal may be discriminated as an irregular video signal. Therefore, in this embodiment, the value of the reference signal REF2 of the comparison circuit 5 is switched depending on the level of noise.

In the noise level discriminating circuit 6, the video signal VID is supplied to the frame memory 7 and the subtracting circuit 8. The video signal VID 1 delayed by one frame period via the frame memory 7 is also supplied to the subtraction circuit 8. Thus,
The subtraction circuit 8 outputs the frame difference signal SUB2 of the video signals VID and VID1 before and after the delay, and outputs the frame difference signal SUB2.
Is converted into an absolute value through an absolute value circuit 9 and supplied to a latch circuit 10 having a D-type flip-flop circuit configuration. The latch circuit 10 performs a latch operation in response to a clock signal CK, and supplies the latch signal LAT2 to an accumulation circuit including an adder circuit 11 and a latch circuit 12 having a D-type flip-flop circuit configuration.
The adder circuit 11 receives the latch signal LAT2 and the latch circuit 12
And the latch signal 13 is supplied to the latch circuit 13. The latch circuit 12 generates a vertical synchronization pulse shown in FIG. 3B formed from the composite sync signal.
VD1 is received by the clear terminal and cleared at its rising edge. The latch circuit 12 is connected to the clock signal CK described above.
The latch operation is performed in response to the latch signal, and the latch signal LAT3 is supplied to the adder circuit 11 and the latch circuit 13 described above.

Therefore, the latch signal LAT3 indicates the accumulated value of the latch signal LAT2 since the start of the vertical synchronization pulse period.

The latch circuit 13 receives the inverted vertical synchronization pulse VD2 shown in FIG. 3 (C) at the clock terminal and performs a latch operation of the latch signal LAT3. Here, the latch circuit 12 outputs the vertical synchronization pulse
Since the signal is cleared at the rise of VD1, the latch signal LAT4 of the latch circuit 13 is the accumulated value of the latch signal LAT2 during the vertical synchronization pulse period.

The latch signal LAT4 from the latch circuit 13 is given to the comparison circuit 14. The comparison circuit 14 is also provided with a reference signal REF3 of a magnitude that is set to a recommended value according to the destination at the time of factory shipment or optionally set by a serviceman. Signal LAT4 is reference signal RE
When it is larger than F3, it takes logic "H" and latch signal LAT4
Is smaller than the reference signal REF3, a signal having a logic "L" is output as a detection signal S2 indicating the degree of noise.

The reason that the reference signal REF3 is set to a value corresponding to the destination is that the television receiver is shipped to a remote island where the reception electric field intensity is extremely low, or to a region where there are many days that are hit by a sand storm or severe wind and rain. Is also taken into account,
This is because it is desirable to set the reference signal REF3 to be larger than usual for a television receiver shipped to such a weak electric field reception area. Also, if the television receiver is moved from a strong electric field receiving area to a weak electric field receiving area due to moving, etc., request the serviceman to adjust at the moving destination, so that the value of REF3 will be larger than before. It is possible to change. In addition, so that not only service personnel but also those who are interested in home appliances can adjust,
An adjustment knob for the reference signal REF3 may be provided inside the ceiling panel so that the user can make adjustments in accordance with a handling manual.

Here, the frame difference signal obtained from the subtraction circuit 8 is
In effect, since the threshold is determined only during the vertical synchronization pulse period, the moving part of the image is not mistaken for noise as in the case of a moving image signal, and only the amount of the noise component purely superimposed on the video signal is obtained. The signal is supplied from the latch circuit 13 to the comparison circuit 14. For this reason, the latch signal LAT2 viewed during the vertical synchronization pulse
The signal corresponds to the difference signal SUB2 of almost 0 level, and the accumulated value of the vertical synchronization pulse period (latch signal LAT4) is small.
The detection signal S2 becomes logic “L”. Also, on the contrary,
When there is a lot of noise, the latch signal LAT2 seen during the vertical synchronization pulse period corresponds to the large difference signal SUB2,
The accumulated value increases and the detection signal S2 becomes logic "H".

The detection signal S2 output from the comparison circuit 14 is
As a selection command signal. The selection input IN1 smaller than the selection input IN2 applied to the second selection input terminal 15B is provided to the first selection input terminal 15A of the selector circuit 15, and the video signal VID is detected with little noise. When the signal S2 is at logic "L", the first selection input IN1 is selected. On the other hand, the video signal VID has much noise and the detection signal S2 is selected.
Is the logic "H", the second selection input IN2 is selected.

The signal selected by the selector circuit 15 is provided to the comparison circuit 5 as the reference signal REF2. Therefore, when the video signal VID has little noise, the comparison circuit 5 determines whether the video signal VID is a normal video signal or an irregular video signal based on the small-valued reference signal REF2.
If there is a lot of noise, it is determined whether the video signal is a regular video signal or an irregular video signal based on the reference signal REF2 having a large value.

This is because if the video signal VID contains a lot of noise, even if it is a regular video signal, one field period becomes longer or shorter due to noise, or the number of burst lock clock signals CK. This is because the count value CNT of the counter circuit 1 is affected by noise, so that it is desired to loosen the criterion for determining whether the video signal is an irregular video signal or a regular video signal. However, with respect to the reproduction of the video signal VID mixed with much noise, there is a strict difference in stability between the clock signal of the H lock and the clock signal of the burst lock which are equally affected by the noise. It has been found that the clock signal has less fluctuation and is more stable than the clock signal of the H clock. For this reason, even in the weak electric field state, if the video signal is determined to be a normal video signal by relaxing the determination criterion, the signal processing is performed in accordance with the clock signal of the burst lock. Can be suppressed.

In the case of this embodiment, a circuit group obtained by removing the selector circuit 15 from the noise level discriminating circuit 6 constitutes a noise amount discriminating means, and the selector circuit 15 serves as a comparison reference (threshold) REF2 of the comparing circuit 5.
Variably setting means is configured.

In the above configuration, when a normal video signal is input, one field period of the video signal is almost a normal one field period, and the subtraction circuit 3 outputs a difference signal SUB1 containing substantially zero. Then, the comparison circuit 5 outputs a detection signal S1 representing a normal video signal.

On the other hand, when an irregular video signal including a time axis fluctuation component (jitter) such as a reproduction signal of a video tape recorder or a video disk player is input, one field period of the video signal is changed to a regular one field period. The subtraction circuit 3 outputs a difference signal SUB1 corresponding to the difference between the periods, and the comparison circuit 5 outputs a detection signal S1 representing an irregular video signal.

In this state, if the video signal contains much noise, a large reference signal REF2 is given to the comparison circuit 5 from the noise somewhat discrimination circuit 6 in consideration of the fact that the count value CNT slightly changes due to the noise, and the normal video signal is output. An erroneous detection that mistakes the signal as an irregular video signal is prevented.

On the other hand, when the noise included in the video signal is small, the count value CNT is not affected by the noise.
Is supplied to the comparison circuit 5. As a result, similarly to the case where a lot of noise is included, it is possible to prevent the non-regular video signal from being erroneously detected as the regular video signal.

As described above, according to the television receiver, the magnitude of the field difference signal or the frame difference signal in the vertical synchronizing pulse period is determined by a threshold to determine the amount of noise included in the input video signal, and The larger the amount, the larger the threshold value is set, so that when a television broadcast wave is received in a weak electric field receiving area, the signal is transmitted in a field cycle regardless of a regular video signal. Even if a small amount of fluctuation appears, the normal / non-normal discrimination standard of the video signal is relaxed according to the noise amount discrimination result, so that the normal video signal is not erroneously discriminated as the non-regular video signal. Therefore, for example, it is apparent that H is erroneously determined to be an irregular video signal due to noise mixed in a weak electric field state as in the related art, and the stability is much lower than that of a burst lock clock signal.
The clock signal of the lock is used as the system clock, and as a result, various signal processing, especially color demodulation processing, lacks accuracy and does not cause unnecessary image quality deterioration. It is possible.

Also, the criteria for determining the amount of noise should be appropriately changed according to the receiving conditions such as remote islands where the receiving conditions are poor and the receiving electric field strength drops extremely, or regions where the number of days to be affected by sandstorms or severe wind and rain is large. Thus, it is possible to provide a fine-grained response according to the received electric field strength. Furthermore, since the amount of noise is determined according to the magnitude of the field difference signal or the frame difference signal in the flat vertical synchronization pulse period of the signal level where the video signal is not superimposed,
Appropriate noise amount discrimination is possible regardless of whether the signal is a moving image signal or a still image signal, and thereby the accuracy of discriminating an input video signal can be improved.

The noise level determination circuit 6 may be configured to determine the amount of noise included in the input video signal according to the magnitude of the field difference signal in the vertical synchronization pulse period instead of the frame difference signal. In that case, the frame memory 7 may be replaced with a field memory.

Further, in the above embodiment, the normal /
Although the irregularity is determined based on the length of the field period, the determination target period can be extended to a frame period or a several field period longer than that.

Further, in the above-described embodiment, the video signal determination criterion is described in two stages. However, the determination criterion may be continuously changed according to the amount of noise.

[Effects of the Invention] As described above, according to the present invention, the video signal discriminating circuit discriminates the number of clock signals phase-locked to the color burst signal in one field period or a period several times as long as the threshold value. Then, it is determined whether the input video signal is a regular video signal or not, and a clock signal phase-locked to a color burst signal (burst-locked clock signal) or a clock signal phase-locked to a horizontal synchronization signal (H-locked clock signal) is determined. One of them is adopted as the system clock, and the noise amount discriminating means discriminates the magnitude of the noise amount included in the input video signal by discriminating the threshold value of the magnitude of the field difference signal or the frame difference signal in the vertical synchronization pulse period. Since the threshold value is set to be larger as the amount of noise is larger, the threshold value is set in a weak electric field receiving area. In the case where a vision broadcast radio wave is received, even if a slight variation occurs in the field cycle despite the fact that the signal is a regular video signal, the regular / non-regular discrimination standard of the video signal is relaxed according to the noise amount discrimination result. Therefore, it does not rely on the regular video signal to determine the non-regular video signal, so, for example, as in the prior art, it is erroneously determined to be a non-regular video signal due to mixed noise in a weak electric field state, The H-lock clock signal, which is clearly less stable than the burst-lock clock signal, is used as the system clock, and various signal processings, especially the color demodulation processing, are not accurate. It is possible to perform the best signal processing even in the weak electric field condition. By changing the setting appropriately according to the receiving conditions such as remote islands where the electric field strength falls extremely, or local areas where there are many days with sand storms and severe wind and rain, it is possible to respond finely according to the received electric field strength, Since the amount of noise is determined according to the magnitude of the field difference signal or the frame difference signal in the flat vertical synchronization pulse period of the signal level where the video signal is not superimposed, regardless of whether the signal is a moving image signal or a still image signal, Appropriate noise amount discrimination can be performed, thereby providing excellent effects such as improvement in discrimination accuracy of an input video signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a television receiver according to the present invention, and FIGS. 2 and 3 are timing charts of respective parts of the circuit shown in FIG. DESCRIPTION OF SYMBOLS 1 ... Counter circuit 2 ... Latch circuit 3 ... Subtractor circuit 4 ... Absolute value circuit 5 ... Comparison circuit 6 ... Some noise discrimination circuit 15 ... Selector circuit

Claims (1)

(57) [Claims] A threshold value is determined for the number of clock signals phase-locked to a color burst signal in one field period or a period that is several times as long as the threshold value, and whether or not an input video signal is a normal video signal is determined. A video signal discriminating circuit for employing a clock signal phase-locked to the color burst signal in the case of a video signal, and a clock signal phase-locked to a horizontal synchronization signal in the case of an irregular video signal, as a system clock, Noise amount discriminating means for judging the magnitude of a field difference signal or a frame difference signal in a vertical synchronizing pulse period of the input video signal by a threshold value, and judging the amount of noise contained in the input video signal; The threshold value, which is a criterion for the video signal discriminating means, is varied in accordance with the discriminating output of the means, so that the Television receiver characterized by comprising a variable threshold setting means for setting the large the threshold value as.